-------------------------------------------------------------------------------
-- Title      : Sorter Testbench
-- Project    : Prototype implementation of the GTU of the Alice TRD Experiment
-------------------------------------------------------------------------------
-- File       : sorter_tb.vhd
-- Author     : Jan de Cuveland  <cuveland@kip.uni-heidelberg.de>
-- Company    : 
-- Last update: 2003/05/14
-- Platform   : 
-------------------------------------------------------------------------------
-- This is a prototype implementation of the Global Tracking Unit (GTU)
-- of the Alice TRD detector.
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2003/03/10  1.0      cuveland	Created
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gtu_types.all;

-------------------------------------------------------------------------------

entity sorter_tb is

end sorter_tb;

-------------------------------------------------------------------------------

architecture default of sorter_tb is

  component sorter
    generic (
      DEPTH : integer);
    port (
      clk       : in  std_logic;
      rst_n     : in  std_logic;
      valid_in  : in  std_logic;
      y_in      : in  std_logic_vector(9 downto 0);
      idx_in    : in  std_logic_vector(2 downto 0);
      addr_in   : in  std_logic_vector(5 downto 0);
      valid_out : out std_logic;
      y_out     : out std_logic_vector(9 downto 0);
      idx_out   : out std_logic_vector(2 downto 0);
      addr_out  : out std_logic_vector(5 downto 0));
  end component;

  constant DEPTH : integer := 8;

  signal clk_i       : std_logic;
  signal rst_n_i     : std_logic;
  signal valid_in_i  : std_logic;
  signal y_in_i      : std_logic_vector(9 downto 0);
  signal idx_in_i    : std_logic_vector(2 downto 0);
  signal addr_in_i   : std_logic_vector(5 downto 0);
  signal valid_out_i : std_logic;
  signal y_out_i     : std_logic_vector(9 downto 0);
  signal idx_out_i   : std_logic_vector(2 downto 0);
  signal addr_out_i  : std_logic_vector(5 downto 0);

begin  -- default

  DUT: sorter
    generic map (
        DEPTH => DEPTH)
    port map (
        clk       => clk_i,
        rst_n     => rst_n_i,
        valid_in  => valid_in_i,
        y_in      => y_in_i,
        idx_in    => idx_in_i,
        addr_in   => addr_in_i,
        valid_out => valid_out_i,
        y_out     => y_out_i,
        idx_out   => idx_out_i,
        addr_out  => addr_out_i);

  clkgen: process
  begin  -- process clkgen
    clk_i <= '1';
    wait for 5 ns;
    clk_i <= '0';
    wait for 5 ns;
  end process clkgen;
  
  sim: process
  begin
    rst_n_i <= '0';
    valid_in_i <= '0';
    y_in_i <= std_logic_vector(to_signed(0, 10));
    idx_in_i <= std_logic_vector(to_unsigned(0, 3));
    addr_in_i <= std_logic_vector(to_unsigned(0, 6));
    wait for 12 ns;
    rst_n_i <= '1';
    ---------------------------------------------------------------------------

    -- 1st word for index 1
    valid_in_i <= '1';
    y_in_i <= std_logic_vector(to_signed(64, 10));
    idx_in_i <= std_logic_vector(to_unsigned(1, 3));
    addr_in_i <= std_logic_vector(to_unsigned(1, 6));
    wait for 10 ns;

    -- invalid word
    valid_in_i <= '0';
    y_in_i <= std_logic_vector(to_signed(-7, 10));
    idx_in_i <= std_logic_vector(to_unsigned(1, 3));
    addr_in_i <= std_logic_vector(to_unsigned(2, 6));
    wait for 10 ns;

    -- 2nd word for index 1
    valid_in_i <= '1';
    y_in_i <= std_logic_vector(to_signed(-13, 10));
    idx_in_i <= std_logic_vector(to_unsigned(1, 3));
    addr_in_i <= std_logic_vector(to_unsigned(3, 6));
    wait for 10 ns;

    -- index 0 -> ignore!
    valid_in_i <= '1';
    y_in_i <= std_logic_vector(to_signed(-17, 10));
    idx_in_i <= std_logic_vector(to_unsigned(0, 3));
    addr_in_i <= std_logic_vector(to_unsigned(4, 6));
    wait for 10 ns;

    -- 1st word for index 2
    valid_in_i <= '1';
    y_in_i <= std_logic_vector(to_signed(-7, 10));
    idx_in_i <= std_logic_vector(to_unsigned(2, 3));
    addr_in_i <= std_logic_vector(to_unsigned(5, 6));
    wait for 10 ns;

    -- 2nd word for index 2
    valid_in_i <= '1';
    y_in_i <= std_logic_vector(to_signed(-77, 10));
    idx_in_i <= std_logic_vector(to_unsigned(2, 3));
    addr_in_i <= std_logic_vector(to_unsigned(6, 6));
    wait for 10 ns;

    -- 3rd word for index 2
    valid_in_i <= '1';
    y_in_i <= std_logic_vector(to_signed(88, 10));
    idx_in_i <= std_logic_vector(to_unsigned(2, 3));
    addr_in_i <= std_logic_vector(to_unsigned(7, 6));
    wait for 10 ns;

    -- end marker
    valid_in_i <= '1';
    y_in_i <= proj_ypos_end;
    idx_in_i <= std_logic_vector(to_unsigned(6, 3));
    addr_in_i <= std_logic_vector(to_unsigned(8, 6));
    wait for 10 ns;

    -- idle
    valid_in_i <= '0';
    y_in_i <= std_logic_vector(to_signed(0, 10));
    idx_in_i <= std_logic_vector(to_unsigned(6, 3));
    addr_in_i <= std_logic_vector(to_unsigned(8, 6));
    wait for 10 ns;

    ---------------------------------------------------------------------------
    wait;
  end process sim;

end default;

-------------------------------------------------------------------------------