------------------------------------------------------------------------------- -- Title : pt reconstruction unit testbench -- Project : Prototype implementation of the GTU of the Alice TRD Experiment ------------------------------------------------------------------------------- -- File : reconst_tb.vhd -- Author : Jan de Cuveland -- Company : -- Last update: 2003/07/03 -- Platform : ------------------------------------------------------------------------------- -- This is a prototype implementation of the Global Tracking Unit (GTU) -- of the Alice TRD detector. ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003/07/02 1.0 cuveland Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.gtu_types.all; use work.track_types.all; ------------------------------------------------------------------------------- entity reconst_tb is end reconst_tb; ------------------------------------------------------------------------------- architecture default of reconst_tb is component reconst port ( clk : in std_logic; rst_n : in std_logic; valid_in : in std_logic; ready_in : in std_logic; track_in : in std_logic_vector(track_width-1 downto 0); valid_out : out std_logic; ready_out : out std_logic; track_out : out std_logic_vector(track_width-1 downto 0); pt_out : out signed(pt_width-1 downto 0); mem5_addr : out unsigned(addr_width-1 downto 0); mem4_addr : out unsigned(addr_width-1 downto 0); mem3_addr : out unsigned(addr_width-1 downto 0); mem2_addr : out unsigned(addr_width-1 downto 0); mem1_addr : out unsigned(addr_width-1 downto 0); mem0_addr : out unsigned(addr_width-1 downto 0); mem5_ys : in signed(ypos_width-1 downto 0); mem4_ys : in signed(ypos_width-1 downto 0); mem3_ys : in signed(ypos_width-1 downto 0); mem2_ys : in signed(ypos_width-1 downto 0); mem1_ys : in signed(ypos_width-1 downto 0); mem0_ys : in signed(ypos_width-1 downto 0); mem5_pid : in std_logic_vector(pid_width-1 downto 0); mem4_pid : in std_logic_vector(pid_width-1 downto 0); mem3_pid : in std_logic_vector(pid_width-1 downto 0); mem2_pid : in std_logic_vector(pid_width-1 downto 0); mem1_pid : in std_logic_vector(pid_width-1 downto 0); mem0_pid : in std_logic_vector(pid_width-1 downto 0)); end component; signal clk_i : std_logic; signal rst_n_i : std_logic; signal valid_in_i : std_logic; signal ready_in_i : std_logic; signal track_in_i : std_logic_vector(track_width-1 downto 0); signal valid_out_i : std_logic; signal ready_out_i : std_logic; signal track_out_i : std_logic_vector(track_width-1 downto 0); signal pt_out_i : signed(pt_width-1 downto 0); signal mem5_addr_i : unsigned(addr_width-1 downto 0); signal mem4_addr_i : unsigned(addr_width-1 downto 0); signal mem3_addr_i : unsigned(addr_width-1 downto 0); signal mem2_addr_i : unsigned(addr_width-1 downto 0); signal mem1_addr_i : unsigned(addr_width-1 downto 0); signal mem0_addr_i : unsigned(addr_width-1 downto 0); signal mem5_ys_i : signed(ypos_width-1 downto 0); signal mem4_ys_i : signed(ypos_width-1 downto 0); signal mem3_ys_i : signed(ypos_width-1 downto 0); signal mem2_ys_i : signed(ypos_width-1 downto 0); signal mem1_ys_i : signed(ypos_width-1 downto 0); signal mem0_ys_i : signed(ypos_width-1 downto 0); signal mem5_pid_i : std_logic_vector(pid_width-1 downto 0); signal mem4_pid_i : std_logic_vector(pid_width-1 downto 0); signal mem3_pid_i : std_logic_vector(pid_width-1 downto 0); signal mem2_pid_i : std_logic_vector(pid_width-1 downto 0); signal mem1_pid_i : std_logic_vector(pid_width-1 downto 0); signal mem0_pid_i : std_logic_vector(pid_width-1 downto 0); constant clk_period : time := 25 ns; begin -- default -- generate clock process begin clk_i <= '1'; wait for clk_period / 2; clk_i <= '0'; wait for clk_period / 2; end process; -- generate reset process begin rst_n_i <= '0'; wait for 2.5 * clk_period; rst_n_i <= '1'; wait; end process; --From root simulation: --mask = 63 --ys[0] = 2169 --ys[1] = 2355 --ys[2] = 2424 --ys[3] = 2621 --ys[4] = 2688 --ys[5] = 2895 --pt = -567 (-4.429688) -- --mask = 61 --ys[0] = 316 --ys[1] = 394 --ys[2] = 258 --ys[3] = 829 --ys[4] = 190 --ys[5] = 799 --pt = 492 (3.843750) -- generate stimuli process begin valid_in_i <= '0'; ready_in_i <= '0'; wait for 4.5 * clk_period; valid_in_i <= '1'; track_in_i(matchvec_high downto matchvec_low) <= "111111"; wait for clk_period; mem0_ys_i <= conv_signed(2169, ypos_width); mem1_ys_i <= conv_signed(2355, ypos_width); mem2_ys_i <= conv_signed(2424, ypos_width); mem3_ys_i <= conv_signed(2621, ypos_width); mem4_ys_i <= conv_signed(2688, ypos_width); mem5_ys_i <= conv_signed(2895, ypos_width); track_in_i(matchvec_high downto matchvec_low) <= "111101"; wait for clk_period; mem0_ys_i <= conv_signed(316, ypos_width); mem1_ys_i <= conv_signed(394, ypos_width); mem2_ys_i <= conv_signed(258, ypos_width); mem3_ys_i <= conv_signed(829, ypos_width); mem4_ys_i <= conv_signed(190, ypos_width); mem5_ys_i <= conv_signed(799, ypos_width); valid_in_i <= '0'; ready_in_i <= '1'; wait; end process; DUT : reconst port map ( clk => clk_i, rst_n => rst_n_i, valid_in => valid_in_i, ready_in => ready_in_i, track_in => track_in_i, valid_out => valid_out_i, ready_out => ready_out_i, track_out => track_out_i, pt_out => pt_out_i, mem5_addr => mem5_addr_i, mem4_addr => mem4_addr_i, mem3_addr => mem3_addr_i, mem2_addr => mem2_addr_i, mem1_addr => mem1_addr_i, mem0_addr => mem0_addr_i, mem5_ys => mem5_ys_i, mem4_ys => mem4_ys_i, mem3_ys => mem3_ys_i, mem2_ys => mem2_ys_i, mem1_ys => mem1_ys_i, mem0_ys => mem0_ys_i, mem5_pid => mem5_pid_i, mem4_pid => mem4_pid_i, mem3_pid => mem3_pid_i, mem2_pid => mem2_pid_i, mem1_pid => mem1_pid_i, mem0_pid => mem0_pid_i); end default; -------------------------------------------------------------------------------