-------------------------------------------------------------------------------
-- Title      : Testbench for proj_d.vhd
-- Project    : Prototype implementation of the GTU of the Alice TRD Experiment
-------------------------------------------------------------------------------
-- File       : proj_d_tb.vhd
-- Author     : Jan de Cuveland  <cuveland@kip.uni-heidelberg.de>
-- Company    : 
-- Last update: 2003/05/14
-- Platform   : 
-------------------------------------------------------------------------------
-- This is a prototype implementation of the Global Tracking Unit (GTU)
-- of the Alice TRD detector.
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2003/02/06  1.0      cuveland	Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gtu_types.all;

-------------------------------------------------------------------------------

entity proj_d_tb is

end proj_d_tb;

-------------------------------------------------------------------------------

architecture default of proj_d_tb is

  component proj_d
    generic (
      plane : integer);
    port (
      d     : in  deflen_t;
      y     : in  ypos_t;
      d_out : out deflang_t);
  end component;

  constant plane : integer := 5;         -- outer plane

  signal d_i     : deflen_t;
  signal y_i     : ypos_t;
  signal d_out_i : deflang_t;

  signal d_out_expected : std_logic_vector(d_out_i'range);
  
begin  -- default

  DUT: proj_d
    generic map (
        plane => plane)
    port map (
        d     => d_i,
        y     => y_i,
        d_out => d_out_i);

  bla: process
  begin  -- process bla

    d_i <= std_logic_vector(to_signed(40, d_i'length));
    y_i <= std_logic_vector(to_signed(2000, y_i'length));
    d_out_expected <= std_logic_vector(to_signed(30, d_out_expected'length));
    wait for 10 ns;

    d_i <= std_logic_vector(to_signed(40, d_i'length));
    y_i <= std_logic_vector(to_signed(0, y_i'length));
    d_out_expected <= std_logic_vector(to_signed(40, d_out_expected'length));
    wait for 10 ns;

    d_i <= std_logic_vector(to_signed(0, d_i'length));
    y_i <= std_logic_vector(to_signed(2000, y_i'length));
    d_out_expected <= std_logic_vector(to_signed(-10, d_out_expected'length));
    wait for 10 ns;

    d_i <= std_logic_vector(to_signed(0, d_i'length));
    y_i <= std_logic_vector(to_signed(-4000, y_i'length));
    d_out_expected <= std_logic_vector(to_signed(21, d_out_expected'length));
    wait for 10 ns;

  end process bla;
  
end default;

-------------------------------------------------------------------------------