------------------------------------------------------------------------------- -- Title : Testbench for Matching Unit -- Project : Prototype implementation of the GTU of the Alice TRD Experiment ------------------------------------------------------------------------------- -- File : match_tb.vhd -- Author : Jan de Cuveland -- Company : -- Last update: 2003/02/20 -- Platform : ------------------------------------------------------------------------------- -- This is a prototype implementation of the Global Tracking Unit (GTU) -- of the Alice TRD detector. ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003/02/19 1.0 cuveland Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; use ieee.std_logic_arith.conv_std_logic_vector; ------------------------------------------------------------------------------- entity match_tb is end match_tb; ------------------------------------------------------------------------------- architecture default of match_tb is component match generic ( seedline : integer; line_mask : integer; y_window : integer; a_window : integer); port ( i5a, i5b : in std_logic_vector(2 downto 0); i4a, i4b : in std_logic_vector(2 downto 0); i3a, i3b : in std_logic_vector(2 downto 0); i2a, i2b : in std_logic_vector(2 downto 0); i1a, i1b : in std_logic_vector(2 downto 0); i0a, i0b : in std_logic_vector(2 downto 0); y5a, y5b : in std_logic_vector(9 downto 0); y4a, y4b : in std_logic_vector(9 downto 0); y3a, y3b : in std_logic_vector(9 downto 0); y2a, y2b : in std_logic_vector(9 downto 0); y1a, y1b : in std_logic_vector(9 downto 0); y0a, y0b : in std_logic_vector(9 downto 0); a5a, a5b : in std_logic_vector(7 downto 0); a4a, a4b : in std_logic_vector(7 downto 0); a3a, a3b : in std_logic_vector(7 downto 0); a2a, a2b : in std_logic_vector(7 downto 0); a1a, a1b : in std_logic_vector(7 downto 0); a0a, a0b : in std_logic_vector(7 downto 0); inc5 : out std_logic_vector(1 downto 0); inc4 : out std_logic_vector(1 downto 0); inc3 : out std_logic_vector(1 downto 0); inc2 : out std_logic_vector(1 downto 0); inc1 : out std_logic_vector(1 downto 0); inc0 : out std_logic_vector(1 downto 0); match : out std_logic; matchvec : out std_logic_vector(5 downto 0); ab_select : out std_logic_vector(5 downto 0)); end component; constant seedline : integer := 3; constant line_mask : integer := 0; constant y_window : integer := 6; constant a_window : integer := 6; signal i5a_i, i5b_i : std_logic_vector(2 downto 0); signal i4a_i, i4b_i : std_logic_vector(2 downto 0); signal i3a_i, i3b_i : std_logic_vector(2 downto 0); signal i2a_i, i2b_i : std_logic_vector(2 downto 0); signal i1a_i, i1b_i : std_logic_vector(2 downto 0); signal i0a_i, i0b_i : std_logic_vector(2 downto 0); signal y5a_i, y5b_i : std_logic_vector(9 downto 0); signal y4a_i, y4b_i : std_logic_vector(9 downto 0); signal y3a_i, y3b_i : std_logic_vector(9 downto 0); signal y2a_i, y2b_i : std_logic_vector(9 downto 0); signal y1a_i, y1b_i : std_logic_vector(9 downto 0); signal y0a_i, y0b_i : std_logic_vector(9 downto 0); signal a5a_i, a5b_i : std_logic_vector(7 downto 0); signal a4a_i, a4b_i : std_logic_vector(7 downto 0); signal a3a_i, a3b_i : std_logic_vector(7 downto 0); signal a2a_i, a2b_i : std_logic_vector(7 downto 0); signal a1a_i, a1b_i : std_logic_vector(7 downto 0); signal a0a_i, a0b_i : std_logic_vector(7 downto 0); signal inc5_i : std_logic_vector(1 downto 0); signal inc4_i : std_logic_vector(1 downto 0); signal inc3_i : std_logic_vector(1 downto 0); signal inc2_i : std_logic_vector(1 downto 0); signal inc1_i : std_logic_vector(1 downto 0); signal inc0_i : std_logic_vector(1 downto 0); signal match_i : std_logic; signal matchvec_i : std_logic_vector(5 downto 0); signal ab_select_i : std_logic_vector(5 downto 0); begin -- default DUT : match generic map ( seedline => seedline, line_mask => line_mask, y_window => y_window, a_window => a_window) port map ( i5a => i5a_i, i5b => i5b_i, i4a => i4a_i, i4b => i4b_i, i3a => i3a_i, i3b => i3b_i, i2a => i2a_i, i2b => i2b_i, i1a => i1a_i, i1b => i1b_i, i0a => i0a_i, i0b => i0b_i, y5a => y5a_i, y5b => y5b_i, y4a => y4a_i, y4b => y4b_i, y3a => y3a_i, y3b => y3b_i, y2a => y2a_i, y2b => y2b_i, y1a => y1a_i, y1b => y1b_i, y0a => y0a_i, y0b => y0b_i, a5a => a5a_i, a5b => a5b_i, a4a => a4a_i, a4b => a4b_i, a3a => a3a_i, a3b => a3b_i, a2a => a2a_i, a2b => a2b_i, a1a => a1a_i, a1b => a1b_i, a0a => a0a_i, a0b => a0b_i, inc5 => inc5_i, inc4 => inc4_i, inc3 => inc3_i, inc2 => inc2_i, inc1 => inc1_i, inc0 => inc0_i, match => match_i, matchvec => matchvec_i, ab_select => ab_select_i); sim : process begin -- process sim i5a_i <= conv_std_logic_vector(2, 3); i5b_i <= conv_std_logic_vector(2, 3); i4a_i <= conv_std_logic_vector(2, 3); i4b_i <= conv_std_logic_vector(2, 3); i3a_i <= conv_std_logic_vector(2, 3); i3b_i <= conv_std_logic_vector(2, 3); i2a_i <= conv_std_logic_vector(2, 3); i2b_i <= conv_std_logic_vector(2, 3); i1a_i <= conv_std_logic_vector(2, 3); i1b_i <= conv_std_logic_vector(2, 3); i0a_i <= conv_std_logic_vector(2, 3); i0b_i <= conv_std_logic_vector(2, 3); y5a_i <= conv_std_logic_vector(-102, 10); y5b_i <= conv_std_logic_vector(-103, 10); y4a_i <= conv_std_logic_vector(-101, 10); y4b_i <= conv_std_logic_vector(1, 10); y3a_i <= conv_std_logic_vector(-100, 10); y3b_i <= conv_std_logic_vector(0, 10); y2a_i <= conv_std_logic_vector(-99, 10); y2b_i <= conv_std_logic_vector(-98, 10); y1a_i <= conv_std_logic_vector(-1, 10); y1b_i <= conv_std_logic_vector(101, 10); y0a_i <= conv_std_logic_vector(-97, 10); y0b_i <= conv_std_logic_vector(202, 10); a5a_i <= conv_std_logic_vector(-52, 8); a5b_i <= conv_std_logic_vector(-51, 8); a4a_i <= conv_std_logic_vector(1, 8); a4b_i <= conv_std_logic_vector(2, 8); a3a_i <= conv_std_logic_vector(-50, 8); a3b_i <= conv_std_logic_vector(3, 8); a2a_i <= conv_std_logic_vector(-49, 8); a2b_i <= conv_std_logic_vector(4, 8); a1a_i <= conv_std_logic_vector(-48, 8); a1b_i <= conv_std_logic_vector(5, 8); a0a_i <= conv_std_logic_vector(-47, 8); a0b_i <= conv_std_logic_vector(6, 8); wait for 100 ns; y5a_i <= conv_std_logic_vector(-102, 10); y5b_i <= conv_std_logic_vector(-103, 10); y4a_i <= conv_std_logic_vector(-101, 10); y4b_i <= conv_std_logic_vector(1, 10); y3a_i <= conv_std_logic_vector(-100, 10); y3b_i <= conv_std_logic_vector(0, 10); y2a_i <= conv_std_logic_vector(-99, 10); y2b_i <= conv_std_logic_vector(-98, 10); y1a_i <= conv_std_logic_vector(-1, 10); y1b_i <= conv_std_logic_vector(101, 10); y0a_i <= conv_std_logic_vector(-97, 10); y0b_i <= conv_std_logic_vector(202, 10); a5a_i <= conv_std_logic_vector(-52, 8); a5b_i <= conv_std_logic_vector(-51, 8); a4a_i <= conv_std_logic_vector(1, 8); a4b_i <= conv_std_logic_vector(2, 8); a3a_i <= conv_std_logic_vector(-50, 8); a3b_i <= conv_std_logic_vector(3, 8); a2a_i <= conv_std_logic_vector(-49, 8); a2b_i <= conv_std_logic_vector(4, 8); a1a_i <= conv_std_logic_vector(-48, 8); a1b_i <= conv_std_logic_vector(5, 8); a0a_i <= conv_std_logic_vector(-37, 8); a0b_i <= conv_std_logic_vector(6, 8); wait for 100 ns; wait; end process sim; end default; -------------------------------------------------------------------------------