-------------------------------------------------------------------------------
-- Title      : Input Controller Testbench
-- Project    : Prototype implementation of the GTU of the Alice TRD Experiment
-------------------------------------------------------------------------------
-- File       : inputcontrol_tb.vhd
-- Author     : Jan de Cuveland  <cuveland@kip.uni-heidelberg.de>
-- Company    : 
-- Last update: 2003/07/02
-- Platform   : 
-------------------------------------------------------------------------------
-- This is a prototype implementation of the Global Tracking Unit (GTU)
-- of the Alice TRD detector.
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2003/03/14  1.0      cuveland        Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------

entity inputcontrol_tb is

end inputcontrol_tb;

-------------------------------------------------------------------------------

architecture default of inputcontrol_tb is

  component inputcontrol
    port (
      rst_n      : in  std_logic;
      pretrigger : in  std_logic;
      clk_in     : in  std_logic;
      valid_in   : in  std_logic;
      d_in       : in  std_logic_vector(7 downto 0);
      valid_out  : out std_logic;
      d_out      : out std_logic_vector(31 downto 0));
  end component;

  signal rst_n_i      : std_logic;
  signal pretrigger_i : std_logic;
  signal clk_in_i     : std_logic;
  signal valid_in_i   : std_logic;
  signal d_in_i       : std_logic_vector(7 downto 0);
  signal valid_out_i  : std_logic;
  signal d_out_i      : std_logic_vector(31 downto 0);

begin

  DUT : inputcontrol
    port map (
      rst_n      => rst_n_i,
      pretrigger => pretrigger_i,
      clk_in     => clk_in_i,
      valid_in   => valid_in_i,
      d_in       => d_in_i,
      valid_out  => valid_out_i,
      d_out      => d_out_i);

  -- clock generation
  process
  begin
    clk_in_i <= '1';
    wait for 4 ns;
    clk_in_i <= '0';
    wait for 4 ns;
  end process;

  -- reset signal generation
  process
  begin
    rst_n_i <= '0';
    wait for 9 ns;
    rst_n_i <= '1';
    wait;
  end process;

  -- pretrigger generation
  process
  begin
    pretrigger_i <= '0';
    wait for 30 ns;
    pretrigger_i <= '1';
    wait for 20 ns;
    pretrigger_i <= '0';
    wait;
  end process;

  -- input data generation
  process
  begin
    d_in_i     <= "00000000";
    valid_in_i <= '0';
    wait for 82 ns;

    -- falling edge (low byte)
    d_in_i     <= "00100001";
    valid_in_i <= '1';
    wait for 4 ns;
    -- rising edge (high byte)
    d_in_i     <= "01000011";
    valid_in_i <= '1';
    wait for 4 ns;

    -- no word
    d_in_i <= "11111111";
    valid_in_i <= '0';
    wait for 8 ns;

    -- falling edge (low byte)
    d_in_i     <= "01100101";
    valid_in_i <= '1';
    wait for 4 ns;
    -- rising edge (high byte)
    d_in_i     <= "10000111";
    valid_in_i <= '1';
    wait for 4 ns;

    -- falling edge (low byte)
    d_in_i     <= "00100001";
    valid_in_i <= '1';
    wait for 4 ns;
    -- rising edge (high byte)
    d_in_i     <= "01000011";
    valid_in_i <= '1';
    wait for 4 ns;

    -- falling edge (low byte)
    d_in_i     <= "01100101";
    valid_in_i <= '1';
    wait for 4 ns;
    -- rising edge (high byte)
    d_in_i     <= "10000111";
    valid_in_i <= '1';
    wait for 4 ns;

    -- end marker

    -- falling edge (low byte)
    d_in_i     <= "11111111";
    valid_in_i <= '1';
    wait for 4 ns;
    -- rising edge (high byte)
    d_in_i     <= "11111111";
    valid_in_i <= '1';
    wait for 4 ns;

    d_in_i     <= "00000000";
    valid_in_i <= '0';
    wait;

  end process;

end default;

-------------------------------------------------------------------------------