LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; -- assumed in all the examples! ----------------------------------------------- --timer, runs from timeval to 0, sets expired = 1 --when cnt = x"0000" --max can be set with timeval is multiple of --1,6ms --if timeval is set to x0000 timer is stopped, --expired signal always low --refresh sets counter back to 0 ----------------------------------------------- --13.7.2006 inserted 4 bit offset, min timeout 1,6ms max timeout 104,86s entity timeout is port( --clock input clk_in : in std_logic; refresh : in std_logic; timeval : in std_logic_vector(15 downto 0); EN : in std_logic; --clock output expired : out std_logic ); end timeout; architecture atimeout of timeout is signal all0 : std_logic_vector(19 downto 0); --0x0000 signal cnt : std_logic_vector(19 downto 0); --counter register signal expired_i : std_logic; --internal expired signal local_refr : std_logic; --internal slow clock refresh signal begin all0 <=x"0000" & "1111"; --converts fast clock asynchronous refresh to --internal slow clock synchrouous local_refr process(clk_in, refresh) begin if refresh = '1' then local_refr <= '1'; elsif clk_in'event and clk_in = '1' then --sets refresh back to 0 at positive slope if EN = '1' then local_refr <= '0'; ---hmm, works maybe end if; end if; end process; --generates the timeout process(clk_in) begin if clk_in'event and clk_in = '1' then if EN = '1' then --if refresh, set counter to timeval, set exprired to 0 if local_refr='1' then expired_i <= '0'; cnt <= timeval & "1111"; --if not expired and timeval < 0 decrement elsif expired_i='0' and (timeval & "1111") /= all0 then cnt <= cnt - 1; end if; --when counter is 0 set expired to 1 if cnt = all0 and (timeval & "1111") /= all0 then expired_i <= '1'; end if; end if; end if; end process; expired <= expired_i; end atimeout;