LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.all;
use IEEE.numeric_std.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

entity status is
port(
    hamming       : out std_logic_vector(1 downto 0);
    pdcv2	      : in std_logic;    --compatibility with pdc v2
    data_ch1      : in std_logic_vector(38 downto 0);
    data_ch2      : in std_logic_vector(38 downto 0);
    data_ch3      : in std_logic_vector(38 downto 0);
    data_ch4      : in std_logic_vector(38 downto 0);
    data_ch5      : in std_logic_vector(38 downto 0);
    data_ch6      : in std_logic_vector(38 downto 0);
    data_ch7      : in std_logic_vector(38 downto 0);
    data_ch8      : in std_logic_vector(38 downto 0);
    data_ch9      : in std_logic_vector(38 downto 0);
    reset_n : in std_logic;
    clk           : in std_logic;
    str           : in std_logic;
    EN            : in std_logic;
    blink         : out std_logic; --2 hz clock
    serial_in     : in std_logic_vector(8 downto 0);
    s_error       : out std_logic_vector(8 downto 0);  --static error word
    s_active      : out std_logic_vector(8 downto 0);
        s_connected   : out std_logic_vector(8 downto 0);
        d_active          : out std_logic_vector(8 downto 0);
        d_error           : out std_logic_vector(8 downto 0)
--        status_debug  : out std_logic_vector(31 downto 0)
        
    );
end status;

architecture status of status is

--shift register with serial in / parallel out
component shreg2 is
generic(N : Integer := 24);
port(
    rst_n    : in    std_logic;
    SCLK     : in    std_logic;
    SDIN     : in    std_logic;
    SSTR     : in    std_logic;
    EN       : in    std_logic;
    SDOUT    : out   std_logic;
    PAROUT   : out   std_logic_vector(N downto 1)
    );
end component;
--clock divider
component fdiv is
port(
    rst_n : in std_logic;
    clk_in : in std_logic;
    clk_out : out std_logic;
	pulse_out : out std_logic
    );
end component;
--hamming decoder
component hamming_dec_dmem is
    port (
          din            : in  std_logic_vector (38 downto 0); -- data from data memory
          dout           : out std_logic_vector (31 downto 0); -- data to CPU
              state          : out std_logic_vector ( 1 downto 0)
          );
end component;



--signals of the status system
signal serial_in_s  :std_logic;
signal pserial_in   : std_logic_vector(8 downto 0);
signal s_readbuffer : std_logic_vector(38 downto 0); --buffers data from the 2nd serial input register
signal s_address :std_logic_vector(3 downto 0);

signal s_validaddress:std_logic_vector(3 downto 0);

signal s_invreadbuffer:std_logic_vector(38 downto 0);

signal hammingstate:std_logic_vector(1 downto 0);
signal channel :std_logic_vector(3 downto 0);

signal active_i : std_logic_vector(8 downto 0);
signal error_i : std_logic_vector(8 downto 0);
signal connected_i   : std_logic_vector(8 downto 0);
signal p_2hz          : std_logic;


signal errbuf  :        std_logic_vector(8 downto 0);
signal actbuf  :        std_logic_vector(8 downto 0);
signal active_blink  : std_logic_vector(8 downto 0);
signal error_blink   :  std_logic_vector(8 downto 0);


--signal status_debug_i : std_logic_vector(31 downto 0);

signal str_i : std_logic;
signal reset_i: std_logic;
signal clk_i: std_logic;
signal clk_switch : std_logic;
signal sentdata : std_logic_vector(38 downto 0);

signal statusreaddata  : std_logic_vector(38 downto 0);

signal clk_2hz : std_logic;
signal stat: std_logic_vector(2 downto 0);

signal sblink : bit;
signal blink_n :std_logic;
constant blink_on : bit := '1';
constant blink_off: bit := '0';

signal comp_act      : std_logic;
signal comp_con      : std_logic;
signal comp_err      : std_logic;
signal dec_vaddress  : std_logic_vector(8 downto 0);
signal strobe_del    : std_logic;
signal strobe_switch : std_logic;
signal phase_shift   : std_logic;

signal addstat       : std_logic_vector(2 downto 0);


CONSTANT idle     : std_logic_vector(2 downto 0) := "000";
CONSTANT request  : std_logic_vector(2 downto 0) := "001";
CONSTANT frameone : std_logic_vector(2 downto 0) := "010";
CONSTANT frametwo : std_logic_vector(2 downto 0) := "011";
CONSTANT inc      : std_logic_vector(2 downto 0) := "100";


--CONSTANT version  : std_logic_vector(3 DOWNTO 0) := "0000";    --0
CONSTANT ch1     : std_logic_vector(3 DOWNTO 0) := "0000";     --1
CONSTANT ch2     : std_logic_vector(3 DOWNTO 0) := "0001";     --2
CONSTANT ch3     : std_logic_vector(3 DOWNTO 0) := "0010";     --3
CONSTANT ch4     : std_logic_vector(3 DOWNTO 0) := "0011";     --4
CONSTANT ch5     : std_logic_vector(3 DOWNTO 0) := "0100";     --5
CONSTANT ch6     : std_logic_vector(3 DOWNTO 0) := "0101";     --6
CONSTANT ch7     : std_logic_vector(3 DOWNTO 0) := "0110";     --7
CONSTANT ch8     : std_logic_vector(3 DOWNTO 0) := "0111";     --8
CONSTANT ch9     : std_logic_vector(3 DOWNTO 0) := "1000";     --9
begin


fsmaddress: process(clk, str_i, reset_n)
begin
    
    if reset_n = '0' then
    addstat <= idle;
    
    elsif clk'event and clk ='1' then
        if EN = '1' then
            if str_i = '1' then
                case addstat is
                    when idle =>    channel <= ch1;
                                    addstat <= request;
                                    
                    when request =>  if channel > ch9 then
                                        channel <= ch1;
                                     end if;
                                     
                                     s_address <= channel;
                                     addstat <= frameone;
                    
                    when frameone => addstat <= frametwo;
                                       --wait one frame 
                                        
                    when frametwo =>  s_validaddress <= s_address;
                                    
                                     addstat <= inc;
                    when inc      =>if channel < ch9 then
                                        channel <= (channel + 1);
                                    else
                                        channel <= ch1;
                                    end if;
                                    addstat <= request;
                    when others => addstat <= idle;
                end case;
            end if;
        end if;
    end if;
end process;

decoder: process(s_validaddress, addstat)
    begin
        dec_vaddress <= (others => '0');
        if addstat = inc then
            dec_vaddress(conv_integer(s_validaddress)) <= '1';
        end if;
    end process;

    comp_act <= '0' when sentdata = (x"000000000" & "000") else '1';
	comp_con <= '0' when s_readbuffer = (x"fffffffff" & "111") else '1';
    comp_err <= '0' when sentdata = s_readbuffer           else '1';

--for debugging 

--status_debug(3 downto 0) <= "1010" when comp_con <= '1' and dec_vaddress(0) = '1';
 
--status_debug(7 downto 4) <= s_validaddress when comp_con <= '1' and dec_vaddress(0) = '1';
--status_debug(31 downto 8) <= s_readbuffer(31 downto 8);

sdff: for i in 0 to 8 generate
statproc: process(clk)
begin
 if clk'event and clk ='1' then
    if EN = '1' then
        if dec_vaddress(i)='1' then
            active_i(i)    <= comp_act;
            error_i(i)     <= comp_err;
            connected_i(i) <= comp_con;
        end if;
    end if;
 end if;
end process;
end generate;

strobedelay: process(clk)
begin
    if clk'event and clk = '1' then
        if EN = '1' then
			strobe_del <= str_i;
		end if;
    end if;
end process;


--strobe_switch <= strobe_del when pdcv2 = '1' else str_i;
strobe_switch <= str_i;
--clk_switch <= clk when pdcv2 = '0' else not clk;
phase_shift <= EN when pdcv2 = '0' else not EN;
--phase_shift <= not EN;
--provide additional status information
--status_debug(8 downto 0) <= connected_i(8 downto 0);



fsmblinky: process(clk, p_2hz)
begin
 if clk'event and clk ='1' then
    if EN = '1' then
        if p_2hz = '1' then 

            case sblink is

                    when blink_on =>    sblink <= blink_off;
                                                      ---   d_active <= actbuf;
                                                      ---   d_error <= errbuf;


                    when blink_off =>   sblink <= blink_on;
                                                      ----  d_active <= actbuf and active_blink;
                                                      ----  d_error  <= errbuf and error_blink;

            end case;
        end if;
    end if;
  end if;
end process;

blinkff: for i in 0 to 8 generate
blinkproc: process(clk, p_2hz)
variable casesel : std_logic_vector(2 downto 0);
begin
 if clk'event and clk ='1' then
    if EN = '1' then
        if p_2hz = '1' then
        casesel := connected_i(i) & active_i(i) & error_i(i);
        case sblink is
        when blink_on  =>
            case casesel is
            when "000" | "010"  =>
                            d_active(i) <= '1';
                            d_error(i)  <= '1';
            when "001" =>
                            d_active(i) <= '0';
                            d_error(i)  <= '0';
            when "011" =>
                            d_active(i) <= '1';
                            d_error(i)  <= '1';
            when "101" | "100"=>
                            d_active(i) <= '0';
                            d_error(i)  <= '1';
            when "110" =>
                            d_active(i) <= '1';
                            d_error(i)  <= '0';
            when "111" =>
                            d_active(i) <= '1';
                            d_error(i)  <= '1';
            when others =>
                            d_active(i) <= '0';
                            d_error(i)  <= '1';
            end case;
        when blink_off =>
            case casesel is
            when "000" | "010"  =>
                            d_active(i) <= '0';
                            d_error(i)  <= '0';
            when "001" =>
                            d_active(i) <= '0';
                            d_error(i)  <= '0';
            when "011" =>
                            d_active(i) <= '1';
                            d_error(i)  <= '0';
            when "101" | "100"=>
                            d_active(i) <= '1';
                            d_error(i)  <= '0';
            when "110" =>
                            d_active(i) <= '1';
                            d_error(i)  <= '0';
            when "111" =>
                            d_active(i) <= '1';
                            d_error(i)  <= '1';
            when others =>
                            d_active(i) <= '1';
                            d_error(i)  <= '0';
            end case;
        end case;
        end if;
    end if;
 end if;
end process;
end generate;



str_i <= str;

s_error <=error_i;
s_active <=active_i;
--s_connected(8 downto 1) <= connected_i(8 downto 1);
--s_connected(0) <= connected_i(1);
s_connected <= connected_i;

--status_debug <= status_debug_i;
clk_i <= clk;
reset_i <= '1';
blink <= clk_2hz;
--2nd inputmux for status
    with s_address(3 downto 0) select
    serial_in_s <= not SERIAL_IN(0) when ch1,
                   not SERIAL_IN(1) when ch2,
                   not SERIAL_IN(2) when ch3,
                   not SERIAL_IN(3) when ch4,
                   not SERIAL_IN(4) when ch5,
                   not SERIAL_IN(5) when ch6,
                   not SERIAL_IN(6) when ch7,
                   not SERIAL_IN(7) when ch8,
                   not SERIAL_IN(8) when ch9,
                            '-' when others;

    with s_validaddress(3 downto 0) select
        sentdata <= data_ch1  when ch1,
                    data_ch2  when ch2,
                    data_ch3  when ch3,
                    data_ch4  when ch4,
                    data_ch5  when ch5,
                    data_ch6  when ch6,
                    data_ch7  when ch7,
                    data_ch8  when ch8,
                    data_ch9  when ch9,
                   (others => '-') when others;
                   --(x"000000000" & "111") when others;


--statusreadenable: process(clk, str_i)
--begin
--	if  clk'event and clk ='1' then ---
--		if EN = '1' then
--            if  str_i ='1' then ---
--                if s_address = s_reqaddress then
--                    s_validaddress <= s_address;
--                    s_delvalidaddress <= "1111";
--                elsif s_validaddress <= s_address then
 --                   s_delvalidaddress <= s_validaddress;
--                    s_validaddress <= "1111";
--                else                
--                s_address <= s_reqaddress;
--                end if;
--             end if;
--	    end if;
--    end if;
--end process;




--hamming decoder
hammingdec: hamming_dec_dmem
port map(
            din => s_readbuffer,  --invreadbuffer
            --dout => decreadbuffer,
			state => hamming
        );

--shift register
pssreg2: shreg2
    generic map(n => 39)
    port map(
        rst_n => reset_n,
        --SCLK  => clk_switch,
		SCLK  => clk,
        SDIN  => SERIAL_IN_s,
        EN  => phase_shift,
		  
        SSTR  => strobe_switch,
		--SSTR  => str_i,
        Parout =>  s_readbuffer
        );
--clock divider
fdiv40: fdiv
port map(
        rst_n => reset_n,
        clk_in =>clk_i,  --fast clock from avalon bus...
        clk_out => clk_2hz, --slow clock for led blinking
		pulse_out => p_2hz
        );
end;