LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- Last modified 22-06-2006 Jens Steckert
-- Shift register with parallel load and serial output
-- highest bit is shifted out first

entity shreg_parin is
generic(N : Integer := 32);
port(
    --inputs
    rst_n    : in    std_logic;
    PARIN    : in    std_logic_vector(N downto 1);
    CLK      : in    std_logic;
    EN       : in    std_logic;
    --outputs
    SDOUT    : out   std_logic;
    SSTR     : out   std_logic;
    sclk     : out   std_logic
    );
end shreg_parin;

architecture RTL of shreg_parin is

--input register
signal parinreg : std_logic_vector(N-1 downto 0);
signal parbitpos : Integer range 0 to 63;
signal load  : std_logic;

begin
sclk <= clk;

    --shift register
    process(clk)
    begin
        if clk'event and clk='1' then
           if EN = '1' then
            if load='1' then parinreg <= parin;
            else
            parinreg <= parinreg(n-2 downto 0) & parinreg(N-1);
            end if;
           end if;
        end if;
    end process;
    
    --output and load at position 0
    load <= '1' when parbitpos = 0 else '0';
    SDOUT <= parinreg(parinreg'length-1);

    --reset, load and strobe logic
process(CLK, rst_n)
    begin
    if rst_n = '0' then
        --clear register and set strobe back to 0
        parbitpos <= (parinreg'length-1);
        SSTR <= '0';
    elsif CLK'event and CLK = '1' then --at positive clock slope
        if EN = '1' then
            --decrement bit position counter
            
            if parbitpos /= 0 then
                parbitpos <= parbitpos -1;
            end if;
            
            sstr <= '0';
            --reload when counter reaches 0
            if parbitpos = 0 then
                parbitpos <= parinreg'length-1;
                sstr <= '1';

    --       elsif parbitpos =(parinreg'length-1) then
      --          sstr <= '1';
            end if;
        end if;
    end if;
end process;
end RTL;