LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- last modified / 12 jun 2006 / J.Steckert
-- fixed bug with shifted sdout when register longer than data
-- Shift register with serial/parallel load and parallel output

entity shreg2 is
generic(N : Integer := 24);
port(
    rst_n    : in    std_logic;
    SCLK     : in    std_logic;
    SDIN     : in    std_logic;
    SSTR     : in    std_logic;
    EN       : in    std_logic;
    SDOUT7s  : out   std_logic;
    SDOUT    : out   std_logic;
    PAROUTd  : out   std_logic_vector(N downto 1);
    PAROUT   : out   std_logic_vector(N downto 1)
    );
end shreg2;

architecture RTL of shreg2 is

signal sreg, qreg : std_logic_vector(N downto 1);

begin
   process(sclk, rst_n)
        begin
           if rst_n = '0' then
                sreg <= (others => '0');
                qreg <= (others => '0');
           elsif sclk'event and sclk='1' then
                if EN = '1' then
                    sreg <= sreg(N-1 downto 1) & SDIN;
                    if SSTR='1' then qreg <= sreg; end if;
                end if;
           end if;
        end process;
    PAROUTd <= sreg;
    PAROUT <= qreg;
    SDOUT <= sreg(N);
    SDOUT7s <= sreg(N-7);
end RTL;