LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ----------------------------------------------- --dcsboard srg design --connects the srg with the avalon and a clock divider --v03 with write control... --supports serial read on one port --9ports with hamming --13.06.2006 Jens Steckert ----------------------------------------------- --Entity ----------------------------------------------- entity scomm3 is --connections to the outside world port ( --input writedata : in std_logic_vector(31 downto 0); clk : in std_logic; rst_n : in std_logic; write_n : in std_logic; --write control, takes data only when negative... --controlled by avalon bus... read_n : in std_logic; --read control signal from the avalon bus address : in std_logic_vector(3 downto 0);--receives adress for mux -- instr : in std_logic; -- input strobe indata : in std_logic; -- input serial data readdata : out std_logic_vector(31 downto 0); --received data --output -- SERIAL_OUT : out std_logic;--serial output (1 channel) SERIAL_OUT : out std_logic_vector(8 downto 0); --9 output channels STROBE : out std_logic ; --common strobe clkout : out std_logic --common serial clock ); end scomm3; -------------------------------------------------------------- --Architecture -------------------------------------------------------------- architecture a of scomm3 is --shiftregister parin serial out component shreg_parin is generic(N : Integer := 24); port( rst_n : in std_logic; PARIN : in std_logic_vector(N downto 1); CLK : in std_logic; --VALID : in std_logic; SDOUT : out std_logic; SSTR : out std_logic; sclk : out std_logic ); end component; --shift register with serial in / parallel out component shreg is generic(N : Integer := 24); port( rst_n : in std_logic; SCLK : in std_logic; SDIN : in std_logic; SSTR : in std_logic; SDOUT : out std_logic; PAROUT : out std_logic_vector(N downto 1) ); end component; --hamming encoder component hamming_enc_dmem is port ( din : in std_logic_vector (31 downto 0); -- data from the device dout : out std_logic_vector (38 downto 0) -- data to instr. memory ); end component; --hamming decoder component hamming_dec_dmem is port ( din : in std_logic_vector (38 downto 0); -- data from data memory dout : out std_logic_vector (31 downto 0); -- data to CPU state : out std_logic_vector ( 1 downto 0) ); end component; --clock divider component fdiv is port( rst_n : in std_logic; clk_in : in std_logic; clk_out : out std_logic ); end component; --global clock buffer for the 10kHz main clock signal component global is port(a_in : in std_logic; a_out : out std_logic ); end component; ----------------------- --signal definitions... ----------------------- signal serout : std_logic_vector(8 downto 0);--serial data for 1 ch signal CLK_i10k : std_logic:= '0'; --internal clock, not amplified signal clk_i10kg : std_logic:= '0'; --internal clock, after global buffer -- amplified to drive whole design signal strobe_i : std_logic_vector(8 downto 0); signal reset_i : std_logic; signal valid_i : std_logic:= '1'; --signal clkspare : std_logic:= '0'; signal writebuffer : std_logic_vector(31 downto 0);--. signal writeoutbuffer : std_logic_vector(38 downto 0); --contains hamming encoded data signal readbuffer : std_logic_vector(38 downto 0); signal decreadbuffer :std_logic_vector(31 downto 0); signal sinputbuffer : std_logic; signal addressbuffer : std_logic_vector(3 downto 0); CONSTANT refresh : std_logic_vector(3 DOWNTO 0) := "0000"; CONSTANT ch1 : std_logic_vector(3 DOWNTO 0) := "0001"; CONSTANT ch2 : std_logic_vector(3 DOWNTO 0) := "0010"; CONSTANT ch3 : std_logic_vector(3 DOWNTO 0) := "0011"; CONSTANT ch4 : std_logic_vector(3 DOWNTO 0) := "0100"; CONSTANT ch5 : std_logic_vector(3 DOWNTO 0) := "0101"; CONSTANT ch6 : std_logic_vector(3 DOWNTO 0) := "0110"; CONSTANT ch7 : std_logic_vector(3 DOWNTO 0) := "0111"; CONSTANT ch8 : std_logic_vector(3 DOWNTO 0) := "1000"; CONSTANT ch9 : std_logic_vector(3 DOWNTO 0) := "1001"; --CONSTANT ch10 : std_logic_vector(3 DOWNTO 0) := "1010"; CONSTANT timeout : std_logic_vector(3 DOWNTO 0) := "1111"; type data_array is array (0 to 8) of std_logic_vector(38 downto 0); signal wdata_array : data_array; ---------------------------------------------------- --portmapping and connecting the logical blocks ---------------------------------------------------- begin --if bus sets the write_n signal low the data and adress --will be written into the writebuffer register. oproc: process (clk) begin if clk'event and clk ='1' then --rising clock edge if write_n = '0' then writebuffer <= writedata; addressbuffer <= address; end if; if read_n = '0' then readdata <= decreadbuffer; end if; end if; end process; --put those signals out of process... reset_i <= rst_n; clkout <= clk_i10kg; sinputbuffer <= indata; serial_out <= serout; strobe <= strobe_i(1); --copies the readbuffer to the readoutput writemux: PROCESS (addressbuffer, writeoutbuffer) BEGIN -- PROCESS readmux CASE addressbuffer IS -- WHEN refresh => WHEN ch1 => wdata_array(0) <= writeoutbuffer; WHEN ch2 => wdata_array(1) <= writeoutbuffer; WHEN ch3 => wdata_array(2) <= writeoutbuffer; WHEN ch4 => wdata_array(3) <= writeoutbuffer; WHEN ch5 => wdata_array(4) <= writeoutbuffer; WHEN ch6 => wdata_array(5) <= writeoutbuffer; WHEN ch7 => wdata_array(6) <= writeoutbuffer; WHEN ch8 => wdata_array(7) <= writeoutbuffer; WHEN ch9 => wdata_array(8) <= writeoutbuffer; -- WHEN ch10 => wdata_array(10) <= writeoutbuffer; --WHEN timeout => readdata(piowidth-1 DOWNTO 0) <= inputregister; WHEN OTHERS => wdata_array(1) <= writeoutbuffer; --<= (OTHERS => '0'); END CASE; END PROCESS writemux; -------------------------------port maps...<------------------- --------------------------------------------------------- --generates 9 shift registers of type shreg_parin --------------------------------------------------------- multishift: for i in 0 to 8 generate mpsreg: shreg_parin generic map(N => 39) port map( rst_n => reset_i, parin => wdata_array(i), clk => clk_i10kg, sstr => strobe_i(i), sdout => serout(i) ); end generate; --psreg: shreg_parin --generic map(N => 39) --port map( --inputs -- rst_n => reset_i, -- parin => writeoutbuffer, -- clk => clk_i10kg, -- --valid => valid_i, -- --outputs -- sstr => strobe_i, -- sdout => serout -- --sclk => clkspare -- ); pssreg: shreg generic map(n => 39) port map( rst_n => reset_i, SCLK => clk_i10kg, SDIN => sinputbuffer, SSTR => strobe_i(1), Parout => readbuffer ); fdiv40: fdiv port map( rst_n => reset_i, clk_in =>clk, --fast clock from avalon bus... clk_out => clk_i10k --slow clock for srg ); hammigenc: hamming_enc_dmem port map( din => writebuffer, dout => writeoutbuffer ); hammingdec: hamming_dec_dmem port map( din => readbuffer, dout => decreadbuffer ); -------------------------------------------------------------------------------- --!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! --for sim purpose only simclk: process(clk_i10k) begin clk_i10kg <= clk_i10k; end process; --glob: global --port map( -- a_in => clk_i10k, -- a_out => clk_i10kg -- ); end;