LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-----------------------------------------------
--minimal dcsboard srg design
--connects the srg with the avalon and a clock divider
--v03 with write control...
--supports serial read on one port
--only one register w/a hamming
--12.06.2006 Jens Steckert


-----------------------------------------------
--Entity
-----------------------------------------------
entity scomm2 is 

--connections to the outside world
port (
       
        --input
        DATA          : in std_logic_vector(31 downto 0);
        clk           : in std_logic;
        rst_n         : in std_logic;
        write_n       : in std_logic; --write control, takes data only when negative...
                                      --controlled by avalon bus...  
        read_n        : in std_logic; --read control signal from the avalon bus
        
       -- instr         : in std_logic; -- input strobe
        indata        : in std_logic; -- input serial data
        
        recdata       : out std_logic_vector(31 downto 0); --received data
        
        --output
        SERIAL_OUT    : out std_logic;--serial output (1 channel)
        STROBE        : out std_logic ;  --common strobe
        clkout        : out std_logic --common serial clock
        
        );

end scomm2;

--------------------------------------------------------------
--Architecture
--------------------------------------------------------------

architecture a of scomm2 is 


--shiftregister parin serial out
component shreg_parin is 
generic(N : Integer := 24);
port(
    rst_n    : in    std_logic;
    PARIN    : in    std_logic_vector(N downto 1);
    CLK      : in    std_logic;
    VALID    : in    std_logic;
    SDOUT    : out   std_logic;
    SSTR     : out   std_logic;
    sclk     : out   std_logic
    );
end component;

component shreg is
generic(N : Integer := 24);
port(
    rst_n    : in    std_logic;
    SCLK     : in    std_logic;
    SDIN     : in    std_logic;
    SSTR     : in    std_logic;
    SDOUT    : out   std_logic;
    PAROUT   : out   std_logic_vector(N downto 1)
    );
end component;


component fdiv is
port(
    rst_n : in std_logic;
    clk_in : in std_logic;
    clk_out : out std_logic
    );
end component;
--global clock buffer for the 10kHz main clock signal
component global is
port(a_in : in  std_logic;
     a_out : out std_logic
     );
end component;
-----------------------
--signal definitions...
-----------------------
signal serout      : std_logic;--serial data for 1 ch

signal CLK_i10k    : std_logic:= '0'; --internal clock, not amplified
signal clk_i10kg    : std_logic:= '0'; --internal clock, after global buffer
                                       -- amplified to drive whole design
signal strobe_i     : std_logic;
signal reset_i      : std_logic;
signal valid_i      : std_logic:= '1';
signal clkspare     : std_logic:= '0';
signal writebuffer  : std_logic_vector(31 downto 0);--.
signal readbuffer   : std_logic_vector(31 downto 0);
signal sinputbuffer : std_logic;


----------------------------------------------------
--portmapping and connecting the logical blocks
----------------------------------------------------
begin

--if bus sets the write_n signal low the data input will be written into
--the writebuffer register.
writeproc: process (clk)
begin
    if clk'event and clk ='1' then --rising clock edge
        if write_n = '0' then
            writebuffer <= data;
        end if;
    end if;
end process;

outproc:  process(clk_i10kg, rst_n) 
begin
    reset_i <=  rst_n;
    clkout <= clkspare;  ------changed   
    serial_out <= serout;
    strobe <= strobe_i;   
    sinputbuffer <= indata;
    --strinputbuffer <= instr;
        
end process;

--copies the readbuffer to the readoutput
rproc: process(read_n, clk_i10kg)
begin
    recdata <= readbuffer;
end process;


psreg: shreg_parin
generic map(N => 32)
port map(
        --inputs
        rst_n => reset_i,
        parin => writebuffer,
        clk => clk_i10kg,
        valid => valid_i,
        --outputs
        sstr => strobe_i,
        sdout => serout,
        sclk => clkspare        
        );
pssreg: shreg
generic map(n => 32)
port map(
        rst_n => reset_i,
        SCLK  => clk_i10kg,
        SDIN  => sinputbuffer,
        SSTR  => strobe_i,
        Parout => readbuffer
        );
        
fdiv40: fdiv
port map(
        rst_n => reset_i,
        clk_in =>clk,  --fast clock from avalon bus...
        clk_out => clk_i10k --slow clock for srg
        );

        
        
--------------------------------------------------------------------------------
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
--for sim purpose only

simclk: process(clk_i10k)
begin

    clk_i10kg <= clk_i10k;

end process;    
        
        
--glob: global
--port map(
--        a_in => clk_i10k,
--        a_out => clk_i10kg
--       );
        
end;