LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;




-----------------------------------------------
--Entity
-----------------------------------------------
entitiy top is 

--connections to the outside world
port (
        --adress input for multiplexer
        ADR           : in std_logic_vector(3 downto 0);
        --32 bit data to send
        DATA          : in std_logic_vector(31 downto 0);
        
        --maybe some sort of clock...
        clk           : in std_logic;
        
        --serial output (9channels)
        SERIAL_OUT    : out std_logic_vector(9 downto 1);
        --common strobe
        STROBE        : out std_logic ;  
        --common serial clock
        clkout        : out std_logic ;
        
        );

end top;

--------------------------------------------------------------
--Architecture
--------------------------------------------------------------

architecture a of top is 

--some sort of storage register is needed here...



--shiftregister parin serial out
component shreg_parin is 
generic(N : Integer := 24);
port(
    rst_n    : in    std_logic;
    PARIN    : in    std_logic_vector(N downto 1);
    SCLK     : in    std_logic;
    VALID    : in    std_logic;
    SDOUT    : out   std_logic;
    SSTR     : out   std_logic;
    );
end component;

--hamming encoder
component hamming_enc_dmem is
    port (
          din            : in  std_logic_vector (31 downto 0);  -- data from the device
          dout           : out std_logic_vector (38 downto 0)   -- data to instr. memory
          );
end component;

---evtl i2c master but i think that's not needed....

-----------------------
--signal definitions...
-----------------------
Serout      : std_logic_vector(9 downto 1);--serial data for 9 ch
Adress      : std_logic_vector(3 downto 0); --adress
Parin       : std_logic_vector(32 downto 1);--after input register
Parin_ho    : std_logic_vector(39 downto 1);--hamming enc output


CLK         : std_logic;
strobe_i    : std_logic;
reset       : std_logic;

--.
--.
--.

----------------------------------------------------
--portmapping and connecting the logical blocks
----------------------------------------------------
begin
    
    --hmm somehow powerup reset..
    reset <= 1 after ...
    
regs: for i in 1 to 9 generate

psreg(i): shreg_parin
generic map(N => 39)
port map