LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-----------------------------------------------
--frequency divider factor 4000
-----------------------------------------------

entity fdiv is

port(
    --clock input
    clk_in  : in std_logic;
    rst_n   : in std_logic;
    
    --clock output
    clk_out : out std_logic;
    pulse_out : out std_logic;
    en_out   : out std_logic
    );
end fdiv;

architecture afdiv of fdiv is

--for simulation purposes division factor is 40
--constant max : Integer := 1024;
constant max : Integer := 25;
signal cnt : Integer;
signal clockout : std_logic:= '0';
signal enable10k : std_logic:= '0';
--signal LCLK          : std_logic: = '0';
begin
    
    process(clk_in, rst_n)
        begin
            if rst_n = '0' then
                cnt <= 0;
                clockout <= '0';
            elsif clk_in'event and clk_in = '1' then
                if cnt < max then
                    cnt <= cnt +1;
                    pulse_out <= '0';
                else 
                    clockout <= not clockout;
                    cnt <= 0;
                    pulse_out <= '1';
                end if;
            end if;
            
    end process;

process(clockout, rst_n)
    begin
            if rst_n = '0' then
                enable10k <= '0';
            elsif clockout'event and clockout = '1' then
                enable10k <= not enable10k;
            end if;
            
    end process;
clk_out <= clockout;
en_out <= enable10k;    
--en_out <= '1';
end afdiv;