LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
------------------------------------------------------------
--Testbench for the dcs sreg and the actel design
--!!! lean version NO hamming or other options supported !!!
------------------------------------------------------------
entity top_ltop_tb is
generic (sclk_period : Time := 10 ns; lclk_period : Time := 20 ns; use_hamming : Integer := 1);
end top_ltop_tb;

architecture sim of top_ltop_tb is

component ltop is 
    port (
            data                : in    std_logic_vector(31 downto 0);
            clk                 : in    std_logic;
            rst_n               : in    std_logic;
            
            serial_out          : out   std_logic;
            strobe              : out   std_logic;
            clkout              : out   std_logic
            
            );
end component;



component top is
    port (
           LCLK                 : in    std_logic;
           rst                  : in    std_logic;
           mode_sel             : in    std_logic_vector(3 downto 0);
           oddeven              : in    std_logic;

           SSTR                 : inout std_logic;
           SDIN                 : in    std_logic;
           SCLK                 : in    std_logic;

           SDOU                 : out   std_logic;
           state_hm             : out   std_logic_vector(1 downto 0);

           -- I2C to other slave devices
           scl_out              : out std_logic;
           sda_bidir            : inout std_logic;

           MOSgt                : out std_logic_vector(30 downto 1)
           );
end component;



           -- mode_sel(0) is 1/0 for SPI with/without hamming
           -- mode_sel(1) is 1/0 for I2C/SPI
           -- mode_sel(2) is 1/0 for cont. clock or serial clock
           -- mode_sel(3) is 1/0 for Dmode/toggle mode

--no hamming, serial interface, serial clock, toggle mode...
signal mode_sel      : std_logic_vector(3 downto 0) := "0000";


--signal definitions
signal scl_out       : std_logic;
signal sda_bidir     : std_logic;

signal LCLK          : std_logic := '0';
signal rst_n         : std_logic := '0';

signal SSTR          : std_logic;
signal SDIN          : std_logic;

signal SCLK          : std_logic := '0';

signal clk10k        : std_logic := '0';

signal SDOU          : std_logic;


signal cfg           : std_logic_vector(1 downto 0);

signal oddeven       : std_logic;


signal MOSgt         : std_logic_vector(30 downto 1);

signal data2send_i   : std_logic_vector(31 downto 0):= x"00000000";

signal state_hm      : std_logic_vector(1 downto 0);
-- 00 = ok; 01 = parity error; 10 = 2-Bit error; 11 1-Bit error (corrected)
signal rst           : std_logic;

begin
    


    --simulates a power on reset
    rst_n <= '1' after 6.7*sclk_period,
             '0' after 20* sclk_period;
    cfg <= "00" after 1*sclk_period;
        
    oddeven <= '1';

    rst <= not rst_n;
    --generates a clock with the freq of 1/sclk_period and 1/lclk_period
    sclk <= not sclk after sclk_period;
    lclk <= not lclk after lclk_period;

    data2send_i <= x"FFFFFFFF" after 100 * sclk_period,
                x"F0F0F0F0" after 7000 * sclk_period,
                x"0F0F0F0F" after 30000 * sclk_period;
    
itop:
    top
    port map(
           LCLK                 => clk10k,
           rst                  => rst_n,
           mode_sel             => mode_sel,
           oddeven              => oddeven,
           scl_out              => scl_out,
           sda_bidir            => sda_bidir,

           SSTR                 => SSTR,       --strobe
           SDIN                 => SDIN,
           SCLK                 => clk10k,

           SDOU                 => SDOU,
           state_hm             => state_hm,

           MOSgt                => MOSgt
           );
    --connecting the ltop component

iltop:
    ltop
    port map(
            data        => data2send_i,
            clk         => sclk,
            rst_n       => rst,
            serial_out  =>  SDIN, --connection between serial out of dcs with serial
                                  --in of pdc
            strobe      =>  SSTR,  --strobe...
            clkout      =>  clk10k
            );
    

end;