LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ------------------------------------------------------------ --Testbench for the dcs sreg and the actel design --NOW with hamming support ------------------------------------------------------------ entity scomm5_tb is generic (scomm_period : Time := 500 ns; lclk_period : Time := 50 us); end scomm5_tb; architecture sim of scomm5_tb is component scomm5 is port ( --input writedata : in std_logic_vector(31 downto 0); clk : in std_logic; rst_n : in std_logic; write_n : in std_logic; --write control, takes data only when negative... --controlled by avalon bus... read_n : in std_logic; --read control signal from the avalon bus address : in std_logic_vector(3 downto 0);--receives adress for mux SERIAL_IN : in std_logic_vector(8 downto 0); readdata : out std_logic_vector(31 downto 0); --received data state_display : out std_logic_vector(3 downto 0); --output SERIAL_OUT : out std_logic_vector(8 downto 0); --9 output channels status_error : out std_logic_vector(8 downto 0); status_active : out std_logic_vector(8 downto 0); timeout_display: out std_logic; STROBE : out std_logic ; --common strobe clkout : out std_logic --common serial clock ); end component; component top is port ( --Local clock (for debugging) LCLK : in std_logic; --reset (used as power on reset) rst : in std_logic; -- mode selector to configure the chip -- mode_sel(0) is 1/0 for with/without hamming -- mode_sel(1) is 1/0 for I2C/SPI -- mode_sel(2) is 1/0 for cont. clock or serial clock -- mode_sel(3) is 1/0 for Dmode/toggle mode mode_sel : in std_logic_vector(3 downto 0); oddeven : in std_logic; SSTR : in std_logic; -- SSTR input for SPI or data back to --I2C master freq = 300Hz SDIN : in std_logic; -- data in in both cases freq = 10kHz SCLK : in std_logic; -- clock in both cases freq = 10kHz -- SPI out gives out the serial data, for debugging purposes SDOU : out std_logic; --serial data out SDOUT : out std_logic; SDOUT2 : out std_logic; --3 spare signals for further use SOUT0 : out std_logic; --hm0 SOUT1 : out std_logic; --hm1 SOUT2 : out std_logic; --not s -- hamming state state_hm : out std_logic_vector( 1 downto 0); --parallel data out (drives the rectifier channels) MOSgt : out std_logic_vector(30 downto 1) ); end component; component top_old is port ( --Local clock (for debugging) LCLK : in std_logic; --reset (used as power on reset) rst : in std_logic; -- mode selector to configure the chip -- mode_sel(0) is 1/0 for with/without hamming -- mode_sel(1) is 1/0 for I2C/SPI -- mode_sel(2) is 1/0 for cont. clock or serial clock -- mode_sel(3) is 1/0 for Dmode/toggle mode mode_sel : in std_logic_vector(3 downto 0); oddeven : in std_logic; -- I2C to other slave devices -- scl_out : out std_logic; -- sda_bidir : in std_logic; SSTR : in std_logic; -- SSTR input for SPI or data back to --I2C master freq = 300Hz SDIN : in std_logic; -- data in in both cases freq = 10kHz SCLK : in std_logic; -- clock in both cases freq = 10kHz -- SPI out gives out the serial data, for debugging purposes SDOU : out std_logic; --serial data out SDOUT : out std_logic; --SDOUT2 : out std_logic; --3 spare signals for further use SOUT0 : out std_logic; --hm0 SOUT1 : out std_logic; --hm1 SOUT2 : out std_logic; --not s -- hamming state state_hm : out std_logic_vector( 1 downto 0); --parallel data out (drives the rectifier channels) MOSgt : out std_logic_vector(30 downto 1) ); end component; component datadelay is port( input :in std_logic; output : out std_logic ); end component; component datadelay9 is port( input :in std_logic_vector(8 downto 0); output : out std_logic_vector(8 downto 0) ); end component; -- mode_sel(0) is 1/0 for SPI with/without hamming -- mode_sel(1) is 1/0 for I2C/SPI -- mode_sel(2) is 1/0 for cont. clock or serial clock -- mode_sel(3) is 1/0 for Dmode/toggle mode --no hamming, serial interface, serial clock, toggle mode... signal mode_sel_i : std_logic_vector(3 downto 0) := "0000"; --signal definitions signal scl_out : std_logic; signal sda_bidir : std_logic; signal LCLK : std_logic := '0'; signal rst_n : std_logic := '0'; signal scomm_clk : std_logic := '0'; signal SSTR : std_logic; signal SSTRd : std_logic; signal mcu_ser_in : std_logic_vector(8 downto 0); signal mcu_ser_in_d : std_logic_vector(8 downto 0); signal mcu_ser_in_n : std_logic_vector(8 downto 0); signal SDIN : std_logic; signal SCLK : std_logic := '0'; signal clk10k : std_logic := '0'; signal clk10kd : std_logic := '0'; signal SDOU : std_logic_vector(8 downto 0); signal scomm_adress : std_logic_vector(3 downto 0); signal cfg : std_logic_vector(1 downto 0); signal oddeven : std_logic; signal mcu_ser_out : std_logic_vector (8 downto 0); signal mcu_ser_out_d : std_logic_vector (8 downto 0); signal MOSgt : std_logic_vector(30 downto 1); signal data2send_i : std_logic_vector(31 downto 0):= x"00000000"; signal state_hm : std_logic_vector(1 downto 0); -- 00 = ok; 01 = parity error; 10 = 2-Bit error; 11 1-Bit error (corrected) signal rst : std_logic; signal read_n_i :std_logic; --avalon bus control signals signal write_n_i :std_logic; --avalon bus control signals begin scomm_clk <= not scomm_clk after scomm_period; LCLK <= not LCLK after lclk_period; --switch hamming off... mode_sel_i <= "0001"; --set adress to ch1 -- serial_in_i(0) <= '0'; --serial_in_i(7 downto 0) <= "00000000"; mcu_ser_in(6 downto 3) <= "1111"; mcu_ser_in(1 downto 0) <= "11"; --mcu_ser_in(8) <= '1'; --SDIN <= serial_out_i(0); --rst_n <= '1'; --simulates a power on reset rst <= '1'after 16.7*scomm_period, '0' after 120* scomm_period; cfg <= "00" after 1*scomm_period; oddeven <= '1'; mcu_ser_in_n <= not mcu_ser_in_d; --mcu_ser_in_n <= mcu_ser_in; rst_n <= not rst; --generates a clock with the freq of 1/scomm_period and 1/lclk_period -- sclk <= not sclk after scomm_period; -- lclk <= not lclk after lclk_period; write_n_i <= '1' after 100 * scomm_period, '0' after 5000 * scomm_period, '1' after 5010 * scomm_period, '0' after 10000 * scomm_period, '1' after 10010 * scomm_period, '0' after 30000 * scomm_period, '1' after 30010 * scomm_period, '0' after 50000 * scomm_period, '1' after 50010 * scomm_period; --'0' after 10000 * scomm_period, --'1' after 10010 * scomm_period, --'0' after 30000 * scomm_period, --'1' after 30010 * scomm_period, --'0' after 90000 * scomm_period, --'1' after 90010 * scomm_period, --'1' after 120010 * scomm_period; read_n_i <= '1' after 100 * scomm_period, '0' after 15000 * scomm_period, '1' after 15010 * scomm_period, -- '0' after 40000 * scomm_period, --'1' after 40010 * scomm_period, '0' after 789000 * scomm_period, '1' after 789010 * scomm_period; data2send_i <= x"f0f0f0f0" after 5000 * scomm_period, --x"00000001" after 10000 * scomm_period, --x"00000001" after 30000 * scomm_period, -- x"f00ff0fe" after 50000 * scomm_period, -- x"000ffc00" after 10000 * scomm_period, --x"f0f0f0f0" after 30000 * scomm_period, --x"00000010" after 90000 * scomm_period, x"00000000" after 12000000 * scomm_period; scomm_adress <= "1110" after 5000 * scomm_period, --"1000" after 10000 * scomm_period, "0111" after 15000 * scomm_period, "0111" after 30000 * scomm_period, "0111" after 40000 * scomm_period; -- "0010" after 50000 * scomm_period; -- "1110" after 90020 * scomm_period, -- "1111" after 120000 * scomm_period; --read_n_i <= clk10k; --write_n_i <= clk10k; itop: top port map( LCLK => clk10kd, rst => rst, mode_sel => mode_sel_i, oddeven => oddeven, SSTR => SSTRd, --strobe SDIN => mcu_ser_out_d(7), SCLK => clk10kd, SDOUT2 => mcu_ser_in(7), --SDOUT : out std_logic; --SDOUT2 : out std_logic; state_hm => state_hm, MOSgt => MOSgt ); itop2: top port map( LCLK => clk10kd, rst => rst, mode_sel => mode_sel_i, oddeven => oddeven, SSTR => SSTRd, --strobe SDIN => mcu_ser_out_d(2), SCLK => clk10kd, SDOUT2 => mcu_ser_in(2), --SDOUT : out std_logic; --SDOUT2 : out std_logic; state_hm => state_hm, MOSgt => MOSgt ); --connecting the ltop component otop: top_old port map( LCLK => clk10kd, rst => rst, mode_sel => mode_sel_i, oddeven => oddeven, SSTR => SSTRd, --strobe SDIN => mcu_ser_out_d(8), SCLK => clk10kd, SDOUT => mcu_ser_in(8), --SDOUT : out std_logic; --SDOUT2 : out std_logic; --state_hm => state_hm, MOSgt => MOSgt ); iscomm5: scomm5 port map( writedata => data2send_i, clk => scomm_clk, rst_n => rst_n, write_n => write_n_i, read_n => read_n_i, address => scomm_adress, serial_in => mcu_ser_in_n, --connects serial out of pdc with serial in of dcs --readdata => serial_out => mcu_ser_out, --connection between serial out of dcs with serial --in of pdc --the other ports are probably not needed for a short sim... strobe => SSTR, --strobe... clkout => clk10k ); del_clk: datadelay port map(input => clk10k, output => clk10kd); del_str: datadelay port map(input => SSTR, output => SSTRd); del_dat: datadelay9 port map(input => mcu_ser_out, output => mcu_ser_out_d); del_fb: datadelay9 port map(input => mcu_ser_in, output => mcu_ser_in_d); end;