LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; -- Last modified 22-06-2006 Jens Steckert -- Shift register with parallel load and serial output -- highest bit is shifted out first entity datadelay9 is port( --inputs input : in std_logic_vector(8 downto 0); output : out std_logic_vector(8 downto 0) ); end datadelay9; architecture ddl of datadelay9 is signal inp : std_logic_vector(8 downto 0); signal oup : std_logic_vector(8 downto 0); signal buf : std_logic_vector(8 downto 0); begin inp <= input; buf <= transport inp after 20 us; oup <= inp and buf; output <= oup; end ddl;