LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- Last modified 22-06-2006 Jens Steckert
-- Shift register with parallel load and serial output
-- highest bit is shifted out first

entity datadelay is
port(
    --inputs
    input    : in    std_logic;
    output   : out   std_logic
    );
end datadelay;

architecture ddl of datadelay is

signal inp : std_logic;
signal oup : std_logic;
signal buf : std_logic;


begin
inp <= input;
buf <= transport inp after 20 us;
oup <= inp and buf;
output <= oup;


end ddl;