Timing Report Max Delay Analysis Timer Version 2.0 Actel Corporation - Actel Designer Software Release v7.1 (Version 7.1.0.14) Copyright (c) 1989-2006 Date: Fri Mar 02 16:08:13 2007 Design: powerDB Family: 54SXA Die: A54SX08A Package: 100 TQFP Temperature: COM Voltage: COM Speed Grade: -F Design State: Post-Layout Min Operating Condition: BEST Max Operating Condition: WORST ----------------------------------------------------- SUMMARY Clock Domain: LCLK Period (ns): 8.588 Frequency (MHz): 116.442 Required Period (ns): 1000.000 Required Frequency (MHz): 1.000 External Setup (ns): N/A External Hold (ns): N/A Min Clock-To-Out (ns): 3.945 Max Clock-To-Out (ns): 9.532 Clock Domain: SCLK Period (ns): 21.638 Frequency (MHz): 46.215 Required Period (ns): 1000.000 Required Frequency (MHz): 1.000 External Setup (ns): 9.101 External Hold (ns): -0.250 Min Clock-To-Out (ns): 3.281 Max Clock-To-Out (ns): 39.861 Input to Output: Min Delay (ns): Max Delay (ns): END SUMMARY ----------------------------------------------------- Clock Domain LCLK SET Register to Register Path 1 From: sled_reg_delbuf:CLK To: sled_counter20_cnt_ix13:D Delay (ns): 7.456 Slack (ns): 991.412 Arrival (ns): 8.715 Required (ns): 1000.127 Setup (ns): 1.132 Minimum Period (ns): 8.588 Path 2 From: sled_reg_delbuf:CLK To: sled_counter20_cnt_ix7:D Delay (ns): 7.456 Slack (ns): 991.412 Arrival (ns): 8.715 Required (ns): 1000.127 Setup (ns): 1.132 Minimum Period (ns): 8.588 Path 3 From: sled_reg_delbuf:CLK To: sled_counter20_cnt_ix16:D Delay (ns): 7.456 Slack (ns): 991.412 Arrival (ns): 8.715 Required (ns): 1000.127 Setup (ns): 1.132 Minimum Period (ns): 8.588 Path 4 From: sled_reg_sync_slo:CLK To: sled_counter20_cnt_ix13:D Delay (ns): 7.259 Slack (ns): 991.609 Arrival (ns): 8.518 Required (ns): 1000.127 Setup (ns): 1.132 Minimum Period (ns): 8.391 Path 5 From: sled_reg_sync_slo:CLK To: sled_counter20_cnt_ix7:D Delay (ns): 7.259 Slack (ns): 991.609 Arrival (ns): 8.518 Required (ns): 1000.127 Setup (ns): 1.132 Minimum Period (ns): 8.391 Expanded Path 1 From: sled_reg_delbuf:CLK To: sled_counter20_cnt_ix13:D data required time 1000.127 data arrival time - 8.715 slack 991.412 ________________________________________________________ Data arrival time calculation 0.000 LCLK + 1.259 clock network 1.259 sled_reg_delbuf:CLK (r) + 1.207 cell: ADLIB:DFC1B 2.466 sled_reg_delbuf:Q (r) + 0.658 net: sled_delbuf 3.124 ix775:B (r) + 1.480 cell: ADLIB:XOR2 4.604 ix775:Y (r) + 0.164 net: nx774 4.768 ix779:A (r) + 1.480 cell: ADLIB:AOI3A 6.248 ix779:Y (r) + 0.822 net: nx778 7.070 ix791:B (r) + 1.645 cell: ADLIB:NOR2A 8.715 ix791:Y (f) + 0.000 net: nx790 8.715 sled_counter20_cnt_ix13:D (f) 8.715 data arrival time ________________________________________________________ Data required time calculation 1000.000 LCLK + 1.259 clock network 1001.259 sled_counter20_cnt_ix13:CLK (r) - 1.132 Library setup: ADLIB:DFE3C 1000.127 sled_counter20_cnt_ix13:D 1000.127 data required time END SET Register to Register ---------------------------------------------------- SET External Setup No Path END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: sled_counter20_reg_overflow_i:CLK To: LED_out0 Delay (ns): 8.273 Slack (ns): Arrival (ns): 9.532 Required (ns): Clock to Out (ns): 9.532 Path 2 From: sled_bcounter_ix6:CLK To: LED_out2 Delay (ns): 8.532 Slack (ns): Arrival (ns): 9.389 Required (ns): Clock to Out (ns): 9.389 Path 3 From: sled_bcounter_ix9:CLK To: LED_out0 Delay (ns): 7.843 Slack (ns): Arrival (ns): 9.102 Required (ns): Clock to Out (ns): 9.102 Path 4 From: sled_bcounter_ix6:CLK To: LED_out1 Delay (ns): 7.843 Slack (ns): Arrival (ns): 8.700 Required (ns): Clock to Out (ns): 8.700 Expanded Path 1 From: sled_counter20_reg_overflow_i:CLK To: LED_out0 data required time N/C data arrival time - 9.532 slack N/C ________________________________________________________ Data arrival time calculation 0.000 LCLK + 1.259 clock network 1.259 sled_counter20_reg_overflow_i:CLK (r) + 1.207 cell: ADLIB:DFE3C 2.466 sled_counter20_reg_overflow_i:Q (r) + 0.987 net: sled_sclk_BAD 3.453 ix1033:C (r) + 1.480 cell: ADLIB:AO1A 4.933 ix1033:Y (r) + 0.658 net: int_LED_out0 5.591 io_LED_out0:D (r) + 3.941 cell: ADLIB:OUTBUF 9.532 io_LED_out0:PAD (r) + 0.000 net: LED_out0 9.532 LED_out0 (r) 9.532 data arrival time ________________________________________________________ Data required time calculation END SET Clock to Output ---------------------------------------------------- Clock Domain SCLK SET Register to Register Path 1 From: sreg/reg_qreg(23):CLK To: reg_state_hm(1):D Delay (ns): 20.285 Slack (ns): 978.362 Arrival (ns): 21.746 Required (ns): 1000.108 Setup (ns): 1.151 Minimum Period (ns): 21.638 Path 2 From: sreg/reg_qreg(31):CLK To: reg_state_hm(1):D Delay (ns): 19.955 Slack (ns): 978.692 Arrival (ns): 21.416 Required (ns): 1000.108 Setup (ns): 1.151 Minimum Period (ns): 21.308 Path 3 From: sreg/reg_qreg(7):CLK To: reg_state_hm(1):D Delay (ns): 19.955 Slack (ns): 978.692 Arrival (ns): 21.416 Required (ns): 1000.108 Setup (ns): 1.151 Minimum Period (ns): 21.308 Path 4 From: sreg/reg_qreg(15):CLK To: reg_state_hm(1):D Delay (ns): 19.790 Slack (ns): 978.857 Arrival (ns): 21.251 Required (ns): 1000.108 Setup (ns): 1.151 Minimum Period (ns): 21.143 Path 5 From: sreg/reg_qreg(13):CLK To: reg_state_hm(1):D Delay (ns): 19.461 Slack (ns): 979.186 Arrival (ns): 20.922 Required (ns): 1000.108 Setup (ns): 1.151 Minimum Period (ns): 20.814 Expanded Path 1 From: sreg/reg_qreg(23):CLK To: reg_state_hm(1):D data required time 1000.108 data arrival time - 21.746 slack 978.362 ________________________________________________________ Data arrival time calculation 0.000 SCLK + 1.461 clock network 1.461 sreg/reg_qreg(23):CLK (r) + 1.207 cell: ADLIB:DFE3C 2.668 sreg/reg_qreg(23):Q (r) + 0.000 net: sreg/PAROUT_23_ 2.668 sreg:PAROUT<23> (r) + 0.000 net: PAROUT_hi_23_ 2.668 hmdec:din<22> (r) + 1.645 net: hmdec/din_22_ 4.313 hmdec/ix51:C (r) + 1.645 cell: ADLIB:XOR3 5.958 hmdec/ix51:Y (r) + 0.822 net: hmdec/nx50 6.780 hmdec/ix252:A (r) + 1.645 cell: ADLIB:XNOR3 8.425 hmdec/ix252:Y (r) + 0.164 net: hmdec/nx251 8.589 hmdec/ix111:B (r) + 1.480 cell: ADLIB:XNOR2 10.069 hmdec/ix111:Y (r) + 0.658 net: hmdec/nx110 10.727 hmdec/ix115:B (r) + 1.480 cell: ADLIB:XNOR3 12.207 hmdec/ix115:Y (r) + 0.493 net: hmdec/nx114 12.700 hmdec/ix119:C (r) + 1.645 cell: ADLIB:XOR3 14.345 hmdec/ix119:Y (r) + 0.987 net: hmdec/nx118 15.332 hmdec/ix133:B (r) + 1.480 cell: ADLIB:NAND2B 16.812 hmdec/ix133:Y (r) + 0.987 net: hmdec/nx132 17.799 hmdec/ix137:A (r) + 1.151 cell: ADLIB:NAND3C 18.950 hmdec/ix137:Y (r) + 0.000 net: hmdec/state_1_ 18.950 hmdec:state<1> (r) + 1.316 net: state_hm_i_1_ 20.266 ix1037:A (r) + 1.480 cell: ADLIB:AND2 21.746 ix1037:Y (r) + 0.000 net: nx1036 21.746 reg_state_hm(1):D (r) 21.746 data arrival time ________________________________________________________ Data required time calculation 1000.000 SCLK + 1.259 clock network 1001.259 reg_state_hm(1):CLK (r) - 1.151 Library setup: ADLIB:DF1 1000.108 reg_state_hm(1):D 1000.108 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: mode_sel(0) To: reg_state_hm(0):D Delay (ns): 9.209 Slack (ns): Arrival (ns): 9.209 Required (ns): Setup (ns): 1.151 External Setup (ns): 9.101 Path 2 From: mode_sel(0) To: reg_state_hm(1):D Delay (ns): 9.209 Slack (ns): Arrival (ns): 9.209 Required (ns): Setup (ns): 1.151 External Setup (ns): 9.101 Path 3 From: SSTR To: sregparin/reg_sreg(2):D Delay (ns): 8.057 Slack (ns): Arrival (ns): 8.057 Required (ns): Setup (ns): 1.151 External Setup (ns): 7.747 Path 4 From: SSTR To: sregparin/reg_sreg(8):D Delay (ns): 8.057 Slack (ns): Arrival (ns): 8.057 Required (ns): Setup (ns): 1.151 External Setup (ns): 7.747 Path 5 From: SSTR To: sregparin/reg_sreg(6):D Delay (ns): 8.057 Slack (ns): Arrival (ns): 8.057 Required (ns): Setup (ns): 1.151 External Setup (ns): 7.747 Expanded Path 1 From: mode_sel(0) To: reg_state_hm(0):D data required time N/C data arrival time - 9.209 slack N/C ________________________________________________________ Data arrival time calculation 0.000 mode_sel(0) (r) + 0.000 net: mode_sel_0_ 0.000 io_mode_sel(0):PAD (r) + 0.985 cell: ADLIB:INBUF 0.985 io_mode_sel(0):Y (r) + 1.974 net: int_mode_sel_0_ 2.959 ix1335:A (r) + 1.480 cell: ADLIB:BUFA 4.439 ix1335:Y (r) + 3.290 net: nx1336 7.729 ix1039:B (r) + 1.480 cell: ADLIB:AND2 9.209 ix1039:Y (r) + 0.000 net: nx1038 9.209 reg_state_hm(0):D (r) 9.209 data arrival time ________________________________________________________ Data required time calculation N/C SCLK + 1.259 clock network N/C reg_state_hm(0):CLK (r) - 1.151 Library setup: ADLIB:DF1 N/C reg_state_hm(0):D END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: sreg/reg_qreg(23):CLK To: LED_out1 Delay (ns): 38.400 Slack (ns): Arrival (ns): 39.861 Required (ns): Clock to Out (ns): 39.861 Path 2 From: sreg/reg_qreg(23):CLK To: LED_out2 Delay (ns): 38.077 Slack (ns): Arrival (ns): 39.538 Required (ns): Clock to Out (ns): 39.538 Path 3 From: sreg/reg_qreg(31):CLK To: LED_out1 Delay (ns): 38.070 Slack (ns): Arrival (ns): 39.531 Required (ns): Clock to Out (ns): 39.531 Path 4 From: sreg/reg_qreg(7):CLK To: LED_out1 Delay (ns): 38.070 Slack (ns): Arrival (ns): 39.531 Required (ns): Clock to Out (ns): 39.531 Path 5 From: sreg/reg_qreg(31):CLK To: LED_out2 Delay (ns): 37.747 Slack (ns): Arrival (ns): 39.208 Required (ns): Clock to Out (ns): 39.208 Expanded Path 1 From: sreg/reg_qreg(23):CLK To: LED_out1 data required time N/C data arrival time - 39.861 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SCLK + 1.461 clock network 1.461 sreg/reg_qreg(23):CLK (r) + 1.207 cell: ADLIB:DFE3C 2.668 sreg/reg_qreg(23):Q (r) + 0.000 net: sreg/PAROUT_23_ 2.668 sreg:PAROUT<23> (r) + 0.000 net: PAROUT_hi_23_ 2.668 hmdec:din<22> (r) + 1.645 net: hmdec/din_22_ 4.313 hmdec/ix51:C (r) + 1.645 cell: ADLIB:XOR3 5.958 hmdec/ix51:Y (r) + 0.822 net: hmdec/nx50 6.780 hmdec/ix252:A (r) + 1.645 cell: ADLIB:XNOR3 8.425 hmdec/ix252:Y (r) + 0.164 net: hmdec/nx251 8.589 hmdec/ix111:B (r) + 1.480 cell: ADLIB:XNOR2 10.069 hmdec/ix111:Y (r) + 0.658 net: hmdec/nx110 10.727 hmdec/ix115:B (r) + 1.480 cell: ADLIB:XNOR3 12.207 hmdec/ix115:Y (r) + 0.493 net: hmdec/nx114 12.700 hmdec/ix119:C (r) + 1.645 cell: ADLIB:XOR3 14.345 hmdec/ix119:Y (r) + 0.987 net: hmdec/nx118 15.332 hmdec/ix133:B (r) + 1.480 cell: ADLIB:NAND2B 16.812 hmdec/ix133:Y (r) + 0.987 net: hmdec/nx132 17.799 hmdec/ix384:A (r) + 1.480 cell: ADLIB:NAND2A 19.279 hmdec/ix384:Y (r) + 1.480 net: hmdec/nx383 20.759 hmdec/ix303:A (r) + 1.480 cell: ADLIB:AX1 22.239 hmdec/ix303:Y (r) + 0.000 net: hmdec/dout_22_ 22.239 hmdec:dout<22> (r) + 0.493 net: PAROUT_ho_23_ 22.732 ix367:B (r) + 1.480 cell: ADLIB:MX2 24.212 ix367:Y (r) + 0.493 net: nx366 24.705 ix1222:A (r) + 1.645 cell: ADLIB:NOR4 26.350 ix1222:Y (f) + 0.485 net: nx1221 26.835 ix373:A (f) + 1.456 cell: ADLIB:OR5C 28.291 ix373:Y (r) + 0.987 net: nx372 29.278 ix1207:E (r) + 1.480 cell: ADLIB:NOR5C 30.758 ix1207:Y (f) + 0.323 net: nx1206 31.081 ix445:A (f) + 1.132 cell: ADLIB:OR5C 32.213 ix445:Y (r) + 0.987 net: nx444 33.200 ix1359:A (r) + 1.480 cell: ADLIB:CM8INV 34.680 ix1359:Y (f) + 0.000 net: nx1360 34.680 ix585:A (f) + 0.000 cell: ADLIB:AOI3A 34.680 ix585:Y (f) + 0.970 net: int_LED_out1 35.650 io_LED_out1:D (f) + 4.211 cell: ADLIB:OUTBUF 39.861 io_LED_out1:PAD (f) + 0.000 net: LED_out1 39.861 LED_out1 (f) 39.861 data arrival time ________________________________________________________ Data required time calculation END SET Clock to Output ---------------------------------------------------- Path set Pin to Pin SET Input to Output Path 1 From: mode_sel(0) To: LED_out1 Delay (ns): 24.364 Slack (ns): Arrival (ns): 24.364 Required (ns): Path 2 From: mode_sel(0) To: LED_out2 Delay (ns): 24.041 Slack (ns): Arrival (ns): 24.041 Required (ns): Path 3 From: mode_sel(0) To: MOSgt(1) Delay (ns): 19.564 Slack (ns): Arrival (ns): 19.564 Required (ns): Path 4 From: mode_sel(0) To: MOSgt(19) Delay (ns): 19.399 Slack (ns): Arrival (ns): 19.399 Required (ns): Path 5 From: mode_sel(0) To: MOSgt(15) Delay (ns): 19.399 Slack (ns): Arrival (ns): 19.399 Required (ns): Expanded Path 1 From: mode_sel(0) To: LED_out1 data required time N/C data arrival time - 24.364 slack N/C ________________________________________________________ Data arrival time calculation 0.000 mode_sel(0) (r) + 0.000 net: mode_sel_0_ 0.000 io_mode_sel(0):PAD (r) + 0.985 cell: ADLIB:INBUF 0.985 io_mode_sel(0):Y (r) + 1.974 net: int_mode_sel_0_ 2.959 ix1335:A (r) + 1.480 cell: ADLIB:BUFA 4.439 ix1335:Y (r) + 3.290 net: nx1336 7.729 ix349:S (r) + 1.480 cell: ADLIB:MX2 9.209 ix349:Y (r) + 0.164 net: nx348 9.373 ix1222:C (r) + 1.480 cell: ADLIB:NOR4 10.853 ix1222:Y (f) + 0.485 net: nx1221 11.338 ix373:A (f) + 1.456 cell: ADLIB:OR5C 12.794 ix373:Y (r) + 0.987 net: nx372 13.781 ix1207:E (r) + 1.480 cell: ADLIB:NOR5C 15.261 ix1207:Y (f) + 0.323 net: nx1206 15.584 ix445:A (f) + 1.132 cell: ADLIB:OR5C 16.716 ix445:Y (r) + 0.987 net: nx444 17.703 ix1359:A (r) + 1.480 cell: ADLIB:CM8INV 19.183 ix1359:Y (f) + 0.000 net: nx1360 19.183 ix585:A (f) + 0.000 cell: ADLIB:AOI3A 19.183 ix585:Y (f) + 0.970 net: int_LED_out1 20.153 io_LED_out1:D (f) + 4.211 cell: ADLIB:OUTBUF 24.364 io_LED_out1:PAD (f) + 0.000 net: LED_out1 24.364 LED_out1 (f) 24.364 data arrival time ________________________________________________________ Data required time calculation N/C mode_sel(0) (r) cell: top N/C LED_out1 (f) N/C data required time END SET Input to Output ---------------------------------------------------- Path set User Sets