***************************************************************************
                               Status Report
***************************************************************************

Product: Designer
Release: v7.1
Version: 7.1.0.14
File Name: F:\home\angelov\powerDB.svn\actel_54sxa\powerdb.adb
Design Name: powerDB  Design State: fuse

***** Device Data **************************************************

Family: 54SXA  Die: A54SX08A  Package: 100 TQFP
Speed: -F  Voltage (VCCi/VCCa): 3.3/2.5

Restrict JTAG Pins: NO
Restrict Probe Pins: NO

Junction Temperature Range:   COM
Voltage Range:   COM

***** Import Variables *********************************************

Source File(s) Imported on Fri Mar 02 16:07:38 2007:
        F:\home\angelov\powerDB.svn\actel_54sxa\top.edf


***** CAE Variables ************************************************

Back Annotation File: ./powerDB_ba.sdf;Fri Mar 02 16:08:10 2007;342725


***** Fuse Variables ***********************************************

Fuse File: ./powerdb.afm;Fri Mar 02 16:08:14 2007;237158
  Fuse Checksum: D587
  Pin Checksum: 3db022a7_1906936f
  Silicon Signature: UNSET
  Disable Clamping Diode on Unused I/Os: NO


***** Compile Variables ********************************************

Netlist PIN properties overwrite existing properties: 0

Compile Output:
Warning: Top level port mode_sel<2> is not connected to any IO pad
Inserted BUFF before io_spare_2_:D IO pin
Inserted BUFF before io_spare_5_:D, because this macro pin cannot be directly connected to the
routed clock network.
Fanout of 15 exceeds recommended limit of 10 . Net: nx968
Fanout of 16 exceeds recommended limit of 10 . Net: nx1332
Fanout of 16 exceeds recommended limit of 10 . Net: nx1334
Fanout of 16 exceeds recommended limit of 10 . Net: nx1336
Fanout of 16 exceeds recommended limit of 10 . Net: nx1338
Fanout of 16 exceeds recommended limit of 10 . Net: nx1340
Fanout of 15 exceeds recommended limit of 10 . Net: nx1342
Fanout of 16 exceeds recommended limit of 10 . Net: nx1344
Fanout of 16 exceeds recommended limit of 10 . Net: nx1346
Fanout of 16 exceeds recommended limit of 10 . Net: nx1348
Fanout of 15 exceeds recommended limit of 10 . Net: nx1352
Fanout of 16 exceeds recommended limit of 10 . Net: sregparin/nx518
Fanout of 16 exceeds recommended limit of 10 . Net: sregparin/nx520
Fanout of 16 exceeds recommended limit of 10 . Net: sregparin/nx524
Fanout of 16 exceeds recommended limit of 10 . Net: sregparin/nx526
Fanout of 16 exceeds recommended limit of 10 . Net: sreg/nx220
Fanout of 16 exceeds recommended limit of 10 . Net: sreg/nx222
Fanout of 16 exceeds recommended limit of 10 . Net: sreg/nx232
Fanout of 16 exceeds recommended limit of 10 . Net: sreg/nx234
Fanout of 16 exceeds recommended limit of 10 . Net: sreg/nx236
Fanout of 16 exceeds recommended limit of 10 . Net: sreg/nx238
Fanout of 14 exceeds recommended limit of 10 . Net: sreg/nx240
Post-Combiner device utilization:
    SEQUENTIAL      Used:  177  Total:  256   (69.14%)
    COMB            Used:  367  Total:  512   (71.68%)
    LOGIC           Used:  544  Total:  768   (70.83%) (seq+comb)
    IO w/ Clocks    Used:   80  Total:   81
    CLOCK           Used:    2  Total:    2
    HCLOCK          Used:    0  Total:    1

Routed Clock Networks Analysis:
    Direct Reg-to-Reg data paths:  88
    Buffers inserted to direct Reg-to-Reg data paths:  88
    (Number of Buffers inserted depends on the availability of
    COMB modules in the design)

There were 0 error(s) and 1 warning(s) in this design.


***** Layout Variables *********************************************

Mode: STANDARD
Incremental Placement: OFF
Extended Run: NO