LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- last modified: 11:19 / 27-Feb-2007 / V.Angelov

-- Toggle register or toggle logic

entity treg is
generic(N : Integer := 24; regmode : Integer := 0);-- oddeven : Integer := 1);
port(
    rst_n    : in    std_logic;
    CLK      : in    std_logic;
    D        : in    std_logic_vector(N downto 1);
    Dmode    : in    std_logic;
    oddeven  : in    std_logic; -- odd and even bits toggle in opposite phase
    Q        : out   std_logic_vector(N downto 1)
    );
end treg;

architecture RTL of treg is

signal reg   : std_logic_vector(N downto 1);
signal phase : std_logic_vector(N downto 1);

begin


rgmod: if regmode = 1 generate
ti: for i in 1 to N generate

trgi: process(clk, rst_n)
        begin
           if rst_n = '0' then
                reg(i) <= '0';
           elsif clk'event and clk='1' then
                if Dmode='1' then reg(i) <= D(i);            -- normal D-register
                             else reg(i) <= D(i) xor reg(i); -- toggle, TFF
                end if;
           end if;
        end process;
    end generate;
end generate;

gtmod: if regmode /= 1 generate

    process(oddeven)
    begin
        phase <= (others => '0');
        for i in 1 to N loop
            if (i mod 2) = 1 then phase(i) <= oddeven; end if;
        end loop;
    end process;

andi: for i in 1 to N generate
    reg(i) <= (Dmode or (CLK xor phase(i)) ) and D(i);
    end generate;
end generate;

    Q <= reg;
end RTL;