LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- Design hierarchy

-- top
--   |
--   |\_____ shreg
--   |
--   |\_____ shreg_p
--   |
--   |\_____ hamming_dec_dmem
--   |         |
--   |          \___ hamming_enc_dmem
--   |
--   |
--   |\_____ stat_led
--   |         |
--   |          \___ counter_dec20
--   |
--   |\_____ line_supervisor
--   |         |
--   |         |\___ edge_detect
--   |         |
--   |          \___ counter7b
--   |
--    \_____ treg

-- last modified: 21:05 / 14-Mai-2006 / V.Angelov
-- additional comments 16-May-2006 J. Steckert
-- major changes 16-Sep_2006  J. Steckert (removed I2C)

-- Changes:

-- The toggle block has to implementations : with registers and with gates. As now I2C needs more
-- DFFs, the gate-option is the only possible. The clock to the toggle block is divided by 2 SSTR or
-- LCLK, therefore it is symmetrical already.
-- last modified: 10:14 / 24-Mai-2006 / V.Angelov

------------------------------------------------------------------------------------------------
--ENTITY
------------------------------------------------------------------------------------------------
entity top is
--description of the outerconnections of the design
    port (
           --Local clock (for debugging)
           LCLK                 : in  std_logic;
           --reset (used as power on reset)
           rst                  : in  std_logic;
           -- mode selector to configure the chip
           -- mode_sel(0) is 1/0 for with/without hamming
           -- mode_sel(1) is 1/0 for divided/direct sclk for gating of the outputs

           -- mode_sel(2) is not used now
           -- mode_sel(3) is 1/0 for Dmode/toggle mode
           mode_sel             : in  std_logic_vector(3 downto 0);
           oddeven              : in  std_logic;

           SSTR                 : in std_logic; -- SSTR input for SPI or data back to
                                                    --I2C master freq = 300Hz
           SDIN                 : in    std_logic; -- data in in both cases  freq = 10kHz
           SCLK                 : in    std_logic; -- clock in both cases    freq = 10kHz

           -- SPI out gives out the serial data, for debugging purposes
           SDOU                 : out std_logic; -- pin 10, routed to TP14
           --serial data out
           SDOUT                : out std_logic;  -- output of the input shift register
           SDOUT2               : out std_logic;  -- this is the feedback data line
           --3 spare signals for further use
           SOUT2                : out std_logic;  --not s

           LED_out0             : out std_logic;
           LED_out1             : out std_logic;
           LED_out2             : out std_logic;
           LED_out3             : out std_logic;
           -- hamming state
           state_hm             : out std_logic_vector( 1 downto 0);
           dummyout             : out std_logic;
           spare                : out std_logic_vector(5 downto 0);
           TDOp, TCKp, TDIp     : out std_logic;
           TRSTp                : out std_logic;
           TMSpup               : out std_logic_vector(1 downto 0);
           unused_pin           : out std_logic_vector(17 downto 0);
            --parallel data out (drives the rectifier channels)
           MOSgt                : out std_logic_vector(30 downto 1)
           );
end top;

------------------------------------------------------------------------------------------------
-- ARCHITECTURE
------------------------------------------------------------------------------------------------
architecture a of top is


--shift register
component shreg is
generic(N : Integer := 39; Sout2dist : Integer := 7);
port(
    rst_n    : in    std_logic;
    SCLK     : in    std_logic;
    SDIN     : in    std_logic;
    SSTR     : in    std_logic;
    SDOUT    : out   std_logic;
    SDOUT7s  : out   std_logic;
    PAROUTd  : out   std_logic_vector(N downto 1);
    PAROUT   : out   std_logic_vector(N downto 1)
    );
end component;

component shreg_p is
generic(N : Integer := 39; Sout2dist : Integer := 7);
port(
    --inputs
    rst_n    : in    std_logic;

    SCLK     : in    std_logic;
    SDIN     : in    std_logic;
    SSTR     : in    std_logic;
    PARIN    : in    std_logic_vector(N downto 1);
    SDOUT7s  : out   std_logic;
    SDOUT    : out   std_logic
    --outputs
    );
end component;

--togle register output is toggled with 10kHz
--input data arrives with 300Hz
--generates the ac signal for the recitfiers
component treg is
generic(N : Integer := 24; regmode : Integer := 0);
port(
    rst_n    : in    std_logic;
    CLK      : in    std_logic;
    D        : in    std_logic_vector(N downto 1);
    Dmode    : in    std_logic;
    oddeven  : in    std_logic;
    Q        : out   std_logic_vector(N downto 1)
    );
end component;

--clock buffer
component CLKBUF is
port(
    PAD      : in    std_logic;
    Y        : out   std_logic
    );
end component;

--hamming decoder
component hamming_dec_dmem is
    port (
          din            : in  std_logic_vector (38 downto 0); -- data from data memory
          dout           : out std_logic_vector (31 downto 0); -- data to CPU
          state          : out std_logic_vector ( 1 downto 0)
          );
end component;

--status leds
component stat_led is
port (
        local_clock  : in  std_logic;
        serial_clock : in std_logic;

        pardat_dec   : in std_logic_vector(32 downto 1);
        rst          : in std_logic;
        hm_stat      : in std_logic_vector( 1 downto 0);
        sstr_OK      : in  std_logic;
        sdat_OK      : in  std_logic;
        led_0        : out std_logic;
        led_1        : out std_logic;
        led_2        : out std_logic;
        led_3        : out std_logic
        );
end component;

component line_supervisor is
    port (
            sclk    : in std_logic;
            sdat    : in std_logic;
            sstr    : in std_logic;
            reset   : in std_logic;
            div_tc  : in std_logic;
            sstr_OK : out std_logic;
            sdat_OK : out std_logic;
            toggle_clock : out std_logic
            );
end component;

constant use_clk_buff   : Integer := 0; -- better without clock buffer!

--signal definitions
signal PAROUT_hi        : std_logic_vector(39 downto 1);
signal PAROUTd          : std_logic_vector(39 downto 1);
--signal PAROUT_spi       : std_logic_vector(39 downto 1);
signal PAROUT           : std_logic_vector(32 downto 1);
signal PAROUT_ho        : std_logic_vector(32 downto 1);
--signal PAROUT_I2C       : std_logic_vector(40 downto 1);
signal state_hm_i       : std_logic_vector( 1 downto 0);
signal state_hm_d       : std_logic_vector( 1 downto 0);


signal Dmode            : std_logic;
signal SCLK_i           : std_logic;
signal SCLK_i_slow      : std_logic;
signal rst_n            : std_logic;

signal sstr_OK          : std_logic;
signal sdat_OK          : std_logic;

signal LCLK_i           : std_logic; --
signal sdou_i           : std_logic;
signal sdou_i2_hm       : std_logic;
signal sdou_i2_nh       : std_logic;
signal sdou7s_i         : std_logic;

signal toggle_clk       : std_logic;

----------------------------------------------------------------------------------
--portmapping and connecting the logical blocks                            BEGIN--
----------------------------------------------------------------------------------
begin
    unused_pin  <= (others => '0');
    TMSpup <= (others => '1');
    TDOp   <= '0';
    TCKp   <= '0';
    TDIp   <= '0';
    TRSTp  <= '0';
    --negation of the reset signal
    rst_n <= not rst;

--settings for using or omitting clock buffer
cb: if use_clk_buff = 1 generate
clkb: CLKBUF
    port map(
    PAD      => SCLK,
    Y        => SCLK_i
    );
lclkb: CLKBUF
    port map(
    PAD      => LCLK,
    Y        => LCLK_i
    );

    end generate;

ncb: if use_clk_buff /= 1 generate
    SCLK_i <= SCLK;
    LCLK_i <= LCLK;
    end generate;

-- shift register with serial/parallel load and shift
-- receiver, serial to parallel conversion
sreg: shreg
generic map(N => 39, Sout2dist => 7)
port map(
    rst_n    => rst_n,
    SCLK     => SCLK_i,
    SDIN     => SDIN,
    SSTR     => SSTR,
    SDOUT    => SDOU_i,
    SDOUT7s  => sdou7s_i,
    PAROUTd  => PAROUTd,
    PAROUT   => PAROUT_hi
    );

--parallel register, gets the parout of the serial shift register
--delayed by one clock, used to drive the feedback line. If strobe is
--absent the parout value is never been copied to the sregparin, and hence
--the feedback is clock...


sregparin: shreg_p
generic map(N => 39, Sout2dist => 7)
port map(

    rst_n    => rst_n,
    PARIN    => PAROUTd,
    SCLK     => SCLK_i,
    SDIN     => SCLK_i_slow,
    SSTR     => SSTR,
    --outputs
    SDOUT7s  => sdou_i2_nh,
    SDOUT    => sdou_i2_hm

    );
    spare(5) <= SCLK_i;
    spare(4) <= SSTR;
    spare(3) <= SDIN;
    spare(2) <= sdou_i2_hm when mode_sel(0) = '1' else sdou_i2_nh; -- = SDOUT2 feedback
    spare(1) <= sstr_OK;
    spare(0) <= sdat_OK;
    SDOUT2 <= sdou_i2_hm when mode_sel(0) = '1' else sdou_i2_nh; -- this is the feedback data line!

sled: stat_led
port map(
            local_clock  => LCLK_i,
            serial_clock => SCLK_i,
            pardat_dec   => PAROUT,
            rst          => rst,
            hm_stat      => state_hm_d,
            sstr_OK      => sstr_OK,
            sdat_OK      => sdat_OK,
            led_0        => LED_out0,
            led_1        => LED_out1,
            led_2        => LED_out2,
            led_3        => LED_out3
        );

--config of hamming decoder
hmdec: hamming_dec_dmem
    port map(
          din            => PAROUT_hi,
          dout           => PAROUT_ho,
          state          => state_hm_i
          );
    -- when hamming is not used, the status outputs are cleared -- hamming is controlled by mode_sel(0)
    state_hm_d <= "00" when mode_sel(0)='0' else state_hm_i;

    -- update the status pins synchronously, to avoid glitches
    process(SCLK_i)
    begin
        if SCLK_i'event and SCLK_i='1' then
            state_hm <= state_hm_d;
        end if;
    end process;

    ------------------------------------
    --Toggle between hamming or not
    -- mode_sel(0) is 1/0 for with/without hamming

    with mode_sel(0) select
    PAROUT <= PAROUT_hi(32 downto 1) when '0', -- no hamming
              PAROUT_ho(32 downto 1) when '1', -- with hamming
              (others => '-') when others;

    --toggles sdout if hamming is used or not
    with mode_sel(0) select
    SDOU <= sdou7s_i when '0', -- without hamming the serial packet is shorter
            sdou_i   when '1',
            '-'      when others;

    --back channel always raw data output of srg NOT USED NOW!
    SDOUT    <= sdou_i ;
    SOUT2    <= not sdou_i;
    dummyout <= sdou_i or SCLK_i or LCLK_i;

    ---------------------------------------------------
    --Toggle between dmode and toggle register
    -- mode_sel(3) is 1/0 for Dmode/toggle mode
    -- can be overridden by software if jumper is set
--
    Dmode <= PAROUT(31) and mode_sel(3);


-- TFF or DFF array or just gating (if regmode=0)
oreg: treg
    generic map(N => MOSgt'length, regmode => 0)
    port map(
    rst_n    => rst_n,
    CLK      => toggle_CLK,
    Dmode    => Dmode,
    oddeven  => oddeven,
    D        => PAROUT(MOSgt'range),
    Q        => MOSgt
    );

ls: line_supervisor
    port map(
        SCLK     => SCLK_i,
        Sdat     => SDIN,
        SSTR     => SSTR,
        reset    => rst,
        div_tc   => mode_sel(1),
        sstr_OK  => sstr_OK,
        sdat_OK  => sdat_OK,
        toggle_clock => toggle_clk
        );

    --------------------------------------------------------
    --generates slow clock for missing strobe signal
    process(SCLK_i, rst_n)
    begin
        if rst_n = '0' then
            SCLK_i_slow <= '0';
        elsif SCLK_i'event and SCLK_i='1' then
            SCLK_i_slow <= not SCLK_i_slow;
        end if;

    end process;
end;