LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- last modified / 19 sep 2006 / J.Steckert
--
-- Shift register with serial/parallel load and serial output

entity shreg_p is
generic(N : Integer := 39; Sout2dist : Integer := 7);
port(
    rst_n    : in  std_logic;
    SCLK     : in  std_logic;
    SDIN     : in  std_logic;
    SSTR     : in  std_logic;
    SDOUT    : out std_logic;
    SDOUT7s  : out std_logic;
    PARIN    : in  std_logic_vector(N downto 1)
    );
end shreg_p;

architecture RTL of shreg_p is

signal sreg : std_logic_vector(N downto 1);
begin
   process(sclk, rst_n)
        begin
           if rst_n = '0' then
                sreg <= (others => '0');
           elsif sclk'event and sclk='1' then

                if SSTR='1' then
                    sreg <= PARIN;
                else
                    sreg <= sreg(N-1 downto 1) & SDIN;
                end if;

           end if;
        end process;
    SDOUT   <= sreg(N);
    SDOUT7s <= sreg(N-Sout2dist);

end RTL;