LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity line_supervisor is

port (
        sclk    : in std_logic;
        sdat    : in std_logic;
        sstr    : in std_logic;
        reset   : in std_logic;

        div_tc  : in std_logic;

        sstr_OK : out std_logic;
        sdat_OK : out std_logic;
        toggle_clock : out std_logic
        );
end line_supervisor;

architecture l of line_supervisor is

--components...

component counter7b is
    port (
            clk_in     : in std_logic;
            sreset     : in std_logic;
            hard_reset : in std_logic;
            overflow_n : out std_logic

            );
end component;

component edge_detect is
    port (
            clk_in    : in std_logic;
            edge_sig  : in std_logic;
            edgepulse : out std_logic
            );
end component;

--signals

signal c7_dat_ov_n      : std_logic;
signal c7_str_ov_n      : std_logic;
signal dat_edge         : std_logic;
signal str_edge         : std_logic;

signal toggle_clock_d   : std_logic;


begin

--port maps
eddat:  edge_detect
    port map(
        clk_in      => sclk,
        edge_sig    => sdat,
        edgepulse   => dat_edge
        );

sddat:   edge_detect
    port map(
        clk_in      => sclk,
        edge_sig    => sstr,
        edgepulse   => str_edge
        );

counter7dat: counter7b
    port map(
        clk_in      => sclk,
        sreset      => dat_edge,
        hard_reset  => reset,
            --clock output
        overflow_n  => c7_dat_ov_n
    );

counter7str: counter7b
    port map(
        clk_in      => sclk,
        sreset      => str_edge,
        hard_reset  => reset,
            --clock output
        overflow_n  => c7_str_ov_n
    );

    process(sclk, reset)
    begin
        if reset = '1' then
            toggle_clock_d <= '0';
        elsif sclk'event and sclk='1' then
            toggle_clock_d <= not toggle_clock_d;
        end if;
    end process;

    toggle_clock <=      c7_dat_ov_n AND c7_str_ov_n AND sclk            when div_tc='0'
                    else c7_dat_ov_n AND c7_str_ov_n AND toggle_clock_d;

    sstr_OK <= c7_str_ov_n;
    sdat_OK <= c7_dat_ov_n;

end l;