LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
entity edge_detect is

port(
        clk_in    : in std_logic;
        edge_sig  : in std_logic;

        edgepulse : out std_logic
    );
end edge_detect;

architecture adetect of edge_detect is


signal inbuf1, inbuf2, capture1, capture2, delay1, delay2, delay3 : std_logic;

begin

process(clk_in)
begin
    if clk_in'event and clk_in = '1' then
        inbuf1 <= edge_sig;
        inbuf2 <= inbuf1;
    end if;
end process;

process(clk_in)
begin
    if clk_in'event and clk_in = '1' then
        capture1 <= inbuf2;
        capture2 <= capture1;
    end if;
end process;

process(clk_in)
begin
    if clk_in'event and clk_in = '1' then
        delay1 <= capture1 xor capture2;
        delay2 <= delay1;
        delay3 <= delay2;
    end if;
end process;

edgepulse <= delay1 OR delay2 OR delay3;

end adetect;