LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
-----------------------------------------------
--counter 5 bit, stops at dec 20
--static overflow high
--20.12.06 Jens Steckert
-----------------------------------------------

entity counter_dec20 is

port(
    --clock input
    clk_in      : in std_logic;
    sreset      : in std_logic;
    hard_reset  : in std_logic;

    --clock output
    overflow    : out std_logic
    );
end counter_dec20;

architecture acount of counter_dec20 is

constant max : std_logic_vector(4 downto 0) := "10100";
signal   cnt : std_logic_vector(4 downto 0);

signal overflow_i : std_logic;

begin

    process(clk_in, hard_reset)
        begin
            if hard_reset = '1' then
                cnt <= "00000";
                overflow_i <= '0';

            elsif clk_in'event and clk_in = '1' then
              if sreset='1' then
                cnt <= "00000";
                overflow_i <= '0';
              elsif overflow_i = '0' then
                if cnt < max then
                    cnt <= cnt +1;
                else
                    overflow_i <= '1';
                    cnt <= "00000";
                end if;
              end if;
            end if;
    end process;

    overflow <= overflow_i;

end acount;