LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
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--counter 7 bit, static overflow, overflow=0
--positive edge resets
--20.12.06  Jens Steckert
-----------------------------------------------

entity counter7b is

port(
    --clock input
    clk_in     : in std_logic;
    sreset     : in std_logic;
    hard_reset : in std_logic;

    --clock output
    overflow_n : out std_logic
    );
end counter7b;

architecture acount of counter7b is

constant max : std_logic_vector(6 downto 0) := "1111111";
signal cnt : std_logic_vector(6 downto 0);
signal overflow_i  : std_logic;

begin
    process(clk_in, hard_reset)
        begin
            if hard_reset = '1' then
                cnt <= "0000000";
                overflow_i <= '0';

            elsif clk_in'event and clk_in = '1' then
              if sreset = '1' then
                cnt <= "0000000";
                overflow_i <= '0';
              elsif overflow_i = '0' then
                if cnt < max then
                    cnt <= cnt + 1;
                else
                    overflow_i <= '1';
                    cnt <= "0000000";
                end if;
              end if;
            end if;

    end process;

    overflow_n <= not overflow_i;

end acount;