-- "$Header: 54sx.vhd@@/main/4 $" -- Actel Vital 95 library for R2-2001 release. library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; package COMPONENTS is constant DefaultTimingChecksOn : Boolean := True; constant DefaultXGenerationOn : Boolean := False; constant DefaultXon : Boolean := False; constant DefaultMsgOn : Boolean := True; component AND2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND4B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND4C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND4D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND5A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND5B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND5C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO10 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO11 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO12 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO13 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO14 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO15 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO16 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO17 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO18 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO1D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO1E generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO2C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO2D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO2E generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO5A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO6 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO6A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO7 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO8 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO9 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI1D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI5 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AX1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AX1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AX1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AX1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AX1D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AX1E generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXO1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXO2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXO3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXO5 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXO6 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXO7 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXOI1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXOI2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXOI3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXOI4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXOI5 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AXOI7 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component BIBUF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_PAD : VitalDelayType01z := (0.000 ns, 0.000 ns, 1.000 ns, 1.000 ns, 1.000 ns, 1.000 ns); tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; PAD : inout STD_ULOGIC; Y : out STD_ULOGIC); end component; component BUFA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component BUFD generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component BUFF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CLKBUF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CLKBUFI generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CLKINT generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CLKINTI generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CM7 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CM8 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CM8F generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S11_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; FY : out STD_ULOGIC; Y : out STD_ULOGIC); end component; component CM8INV generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMA9 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMAF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMB3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMB7 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMBB generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMBF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMEA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; D3 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMEB generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMEE generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMEF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; DB : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMF1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMF2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMF3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMF4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D2 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMF5 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; D2 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMF6 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMF7 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMF8 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMF9 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMFA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMFB generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMFC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMFD generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CMFE generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CS1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CS2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CY2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; B0 : in STD_ULOGIC; B1 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CY2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; B0 : in STD_ULOGIC; B1 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component DF1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DF1_CC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DF1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFC1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFC1B_CC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFC1D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE3D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE4F generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE4G generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFEG generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFEH generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFP1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFP1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFP1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFP1B_CC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFP1D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFPC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFPCB generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFPCC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DL1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DL1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DL2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DL2C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLC1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLC1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLCA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLE2C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_E_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLE3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_E_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLE3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_E_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLP1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLP1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLP1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLP1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component FA1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); end component; component FA1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); end component; component FA1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); end component; component FA2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); end component; component GAND2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component GMX4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0 : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component GNAND2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component GND generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True); port( Y : out STD_ULOGIC := '0'); end component; component GNOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component GOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component GXOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component HA1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); end component; component HA1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); end component; component HA1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); end component; component HA1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); end component; component HCLKBUF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component INBUF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component INV generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component INVA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component INVD generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component JKF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component MAJ3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MAJ3X generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MAJ3XI generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MIN3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MIN3X generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MIN3XI generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MX2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MX2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MX2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MX2C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MX4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0 : in STD_ULOGIC; S1 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND4B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND4C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND4D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND5B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND5C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR4B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR4C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR4D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR5B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR5C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA5 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OAI1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OAI2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OAI3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OAI3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR4B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR4C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR4D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR5A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR5B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR5C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OUTBUF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; PAD : out STD_ULOGIC); end component; component TF1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_T_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_T_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_T : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( T : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component TF1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_T_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_T_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_T : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( T : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component TRIBUFF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_PAD : VitalDelayType01z := (0.000 ns, 0.000 ns, 1.000 ns, 1.000 ns, 1.000 ns, 1.000 ns); tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; PAD : out STD_ULOGIC); end component; component VCC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True); port( Y : out STD_ULOGIC := '1'); end component; component XA1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XA1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XA1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XA1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XAI1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XAI1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XNOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XNOR3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XO1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XO1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XOR3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component ZOR3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component ZOR3I generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; end COMPONENTS; ---------------------------------------------------------------- -- -- ---------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; package VTABLES is CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DF1_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( L, H, H, x, H ), ( H, x, x, x, S ), ( x, x, L, x, S )); CONSTANT DFC1B_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, H, H, x, H ), ( H, H, x, x, x, S ), ( H, x, x, L, x, S ), ( x, L, L, H, x, L )); CONSTANT DFE1B_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, L ), ( L, L, x, H, H, x, L ), ( L, H, H, x, H, x, H ), ( L, H, x, H, H, x, H ), ( L, x, L, L, H, x, L ), ( L, x, H, L, H, x, H ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L )); CONSTANT DFE4F_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, H, H, x, x, H, x, H ), ( L, H, x, H, x, H, x, H ), ( L, x, L, L, H, H, x, L ), ( L, x, H, L, x, H, x, H ), ( H, x, x, x, H, x, x, S ), ( x, x, x, x, L, x, x, H ), ( x, x, x, x, H, L, x, S )); CONSTANT DFEG_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, x, L ), ( H, L, H, H, x, x, H, x, H ), ( H, L, H, x, H, x, H, x, H ), ( H, L, x, H, L, x, H, x, H ), ( H, H, x, x, x, H, x, x, S ), ( H, x, x, x, x, L, x, x, H ), ( H, x, x, x, x, H, L, x, S ), ( x, L, L, L, x, H, H, x, L ), ( x, L, L, x, H, H, H, x, L ), ( x, L, x, L, L, H, H, x, L )); CONSTANT DFP1_Q_tab : VitalStateTableType := ( ( L, L, L, H, x, L ), ( L, H, x, H, x, H ), ( H, x, L, x, x, S ), ( x, x, L, L, x, S ), ( x, x, H, x, x, H )); CONSTANT DFP1B_Q_tab : VitalStateTableType := ( ( L, L, H, H, x, L ), ( L, H, x, H, x, H ), ( H, x, H, x, x, S ), ( x, x, L, x, x, H ), ( x, x, H, L, x, S )); CONSTANT DFPC_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, L ), ( H, L, H, x, H, x, H ), ( H, H, x, L, x, x, S ), ( H, x, x, L, L, x, S ), ( H, x, x, H, x, x, H ), ( x, L, L, L, H, x, L )); CONSTANT DFPCB_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, L ), ( H, L, H, x, H, x, H ), ( H, H, x, H, x, x, S ), ( H, x, x, L, x, x, H ), ( H, x, x, H, L, x, S ), ( x, L, L, H, H, x, L )); CONSTANT DL1_Q_tab : VitalStateTableType := ( ( L, H, x, L ), ( H, H, x, H ), ( x, L, x, S )); CONSTANT DL1B_Q_tab : VitalStateTableType := ( ( L, L, x, L ), ( L, H, x, H ), ( H, x, x, S )); CONSTANT DL2A_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, H, x, H, x, H ), ( H, x, L, L, x, S ), ( H, x, H, x, x, H ), ( x, L, L, H, x, L )); CONSTANT DL2C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, H, x, x, H ), ( H, H, x, L, x, S ), ( H, x, x, H, x, H ), ( x, L, L, L, x, L )); CONSTANT DLC_Q_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, H, H, x, H ), ( H, x, L, x, S ), ( x, L, H, x, L )); CONSTANT DLC1_Q_tab : VitalStateTableType := ( ( L, H, x, x, L ), ( H, H, L, x, H ), ( x, L, L, x, S ), ( x, x, H, x, L )); CONSTANT DLC1A_Q_tab : VitalStateTableType := ( ( L, L, x, x, L ), ( L, H, L, x, H ), ( H, x, L, x, S ), ( x, x, H, x, L )); CONSTANT DLCA_Q_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, L, H, x, H ), ( H, H, x, x, S ), ( x, L, L, x, L )); CONSTANT DLE2C_Q_tab : VitalStateTableType := ( ( L, L, L, x, x, L ), ( L, L, H, L, x, H ), ( H, x, x, L, x, S ), ( x, H, x, L, x, S ), ( x, x, x, H, x, L )); CONSTANT DLE3B_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, L ), ( L, L, H, x, x, H ), ( H, x, x, L, x, S ), ( x, H, x, L, x, S ), ( x, x, x, H, x, H )); CONSTANT DLE3C_Q_tab : VitalStateTableType := ( ( L, L, L, H, x, L ), ( L, L, H, x, x, H ), ( H, x, x, H, x, S ), ( x, H, x, H, x, S ), ( x, x, x, L, x, H )); CONSTANT DLP1_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( H, x, H, x, H ), ( x, L, L, x, S ), ( x, H, x, x, H )); CONSTANT DLP1A_Q_tab : VitalStateTableType := ( ( L, L, L, x, L ), ( L, H, x, x, H ), ( H, x, L, x, S ), ( x, x, H, x, H )); CONSTANT DLP1B_Q_tab : VitalStateTableType := ( ( L, H, H, x, L ), ( H, x, H, x, H ), ( x, L, x, x, H ), ( x, H, L, x, S )); CONSTANT DLP1C_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( L, H, x, x, H ), ( H, x, H, x, S ), ( x, x, L, x, H )); CONSTANT TF1A_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, L ), ( H, L, L, H, H, x, H ), ( H, L, H, L, H, x, H ), ( H, H, x, x, x, x, S ), ( H, x, x, x, L, x, S ), ( x, L, L, L, H, x, L ), ( x, L, H, H, H, x, L )); end VTABLES; ---- end of VITAL tables library ---- ----- CELL AND2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND2 : entity is TRUE; end AND2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND2_VITAL of AND2 is for VITAL_ACT end for; end CFG_AND2_VITAL; ----- CELL AND2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND2A : entity is TRUE; end AND2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND ((NOT A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND2A_VITAL of AND2A is for VITAL_ACT end for; end CFG_AND2A_VITAL; ----- CELL AND2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND2B : entity is TRUE; end AND2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND2B_VITAL of AND2B is for VITAL_ACT end for; end CFG_AND2B_VITAL; ----- CELL AND3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND3 : entity is TRUE; end AND3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND (A_ipd) AND (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND3_VITAL of AND3 is for VITAL_ACT end for; end CFG_AND3_VITAL; ----- CELL AND3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND3A : entity is TRUE; end AND3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND ((NOT A_ipd)) AND (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND3A_VITAL of AND3A is for VITAL_ACT end for; end CFG_AND3A_VITAL; ----- CELL AND3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND3B : entity is TRUE; end AND3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND3B_VITAL of AND3B is for VITAL_ACT end for; end CFG_AND3B_VITAL; ----- CELL AND3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND3C : entity is TRUE; end AND3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND3C_VITAL of AND3C is for VITAL_ACT end for; end CFG_AND3C_VITAL; ----- CELL AND4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND4 : entity is TRUE; end AND4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND (A_ipd) AND (C_ipd) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND4_VITAL of AND4 is for VITAL_ACT end for; end CFG_AND4_VITAL; ----- CELL AND4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND4A : entity is TRUE; end AND4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND ((NOT A_ipd)) AND (C_ipd) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND4A_VITAL of AND4A is for VITAL_ACT end for; end CFG_AND4A_VITAL; ----- CELL AND4B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND4B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND4B : entity is TRUE; end AND4B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND4B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND4B_VITAL of AND4B is for VITAL_ACT end for; end CFG_AND4B_VITAL; ----- CELL AND4C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND4C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND4C : entity is TRUE; end AND4C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND4C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND4C_VITAL of AND4C is for VITAL_ACT end for; end CFG_AND4C_VITAL; ----- CELL AND4D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND4D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND4D : entity is TRUE; end AND4D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND4D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)) AND ((NOT D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND4D_VITAL of AND4D is for VITAL_ACT end for; end CFG_AND4D_VITAL; ----- CELL AND5A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND5A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND5A : entity is TRUE; end AND5A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND5A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND ((NOT A_ipd)) AND (C_ipd) AND (D_ipd) AND (E_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND5A_VITAL of AND5A is for VITAL_ACT end for; end CFG_AND5A_VITAL; ----- CELL AND5B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND5B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND5B : entity is TRUE; end AND5B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND5B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd) AND (D_ipd) AND (E_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND5B_VITAL of AND5B is for VITAL_ACT end for; end CFG_AND5B_VITAL; ----- CELL AND5C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND5C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND5C : entity is TRUE; end AND5C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AND5C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)) AND (D_ipd) AND (E_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND5C_VITAL of AND5C is for VITAL_ACT end for; end CFG_AND5C_VITAL; ----- CELL AO1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO1 : entity is TRUE; end AO1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((B_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO1_VITAL of AO1 is for VITAL_ACT end for; end CFG_AO1_VITAL; ----- CELL AO10 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO10 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO10 : entity is TRUE; end AO10; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO10 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((E_ipd) OR (D_ipd)) AND ((C_ipd) OR ((B_ipd) AND (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO10_VITAL of AO10 is for VITAL_ACT end for; end CFG_AO10_VITAL; ----- CELL AO11 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO11 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO11 : entity is TRUE; end AO11; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO11 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((C_ipd) AND ((B_ipd) OR (A_ipd))) OR ((B_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO11_VITAL of AO11 is for VITAL_ACT end for; end CFG_AO11_VITAL; ----- CELL AO12 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO12 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO12 : entity is TRUE; end AO12; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO12 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (((NOT C_ipd)) AND ((NOT A_ipd))) OR ((B_ipd) AND ((NOT A_ipd))) OR (((NOT B_ipd)) AND (A_ipd) AND (C_ipd)) OR (((NOT C_ipd)) AND (B_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO12_VITAL of AO12 is for VITAL_ACT end for; end CFG_AO12_VITAL; ----- CELL AO13 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO13 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO13 : entity is TRUE; end AO13; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO13 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (((NOT C_ipd)) AND (A_ipd)) OR ((B_ipd) AND (A_ipd)) OR (((NOT C_ipd)) AND (B_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO13_VITAL of AO13 is for VITAL_ACT end for; end CFG_AO13_VITAL; ----- CELL AO14 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO14 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO14 : entity is TRUE; end AO14; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO14 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (((NOT C_ipd)) AND (A_ipd)) OR ((B_ipd) AND (A_ipd)) OR (((NOT C_ipd)) AND (B_ipd)) OR (((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO14_VITAL of AO14 is for VITAL_ACT end for; end CFG_AO14_VITAL; ----- CELL AO15 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO15 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO15 : entity is TRUE; end AO15; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO15 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((B_ipd) AND ((NOT A_ipd)) AND (C_ipd)) OR (((NOT B_ipd)) AND (A_ipd) AND (C_ipd)) OR (((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO15_VITAL of AO15 is for VITAL_ACT end for; end CFG_AO15_VITAL; ----- CELL AO16 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO16 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO16 : entity is TRUE; end AO16; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO16 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd)) OR ((B_ipd) AND (A_ipd) AND ((NOT C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO16_VITAL of AO16 is for VITAL_ACT end for; end CFG_AO16_VITAL; ----- CELL AO17 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO17 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO17 : entity is TRUE; end AO17; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO17 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((B_ipd) AND ((NOT A_ipd)) AND ((NOT C_ipd))) OR ((B_ipd) AND (A_ipd) AND (C_ipd)) OR (((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO17_VITAL of AO17 is for VITAL_ACT end for; end CFG_AO17_VITAL; ----- CELL AO18 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO18 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO18 : entity is TRUE; end AO18; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO18 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (((NOT C_ipd)) AND ((NOT A_ipd))) OR ((B_ipd) AND ((NOT A_ipd))) OR (((NOT C_ipd)) AND (B_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO18_VITAL of AO18 is for VITAL_ACT end for; end CFG_AO18_VITAL; ----- CELL AO1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO1A : entity is TRUE; end AO1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((B_ipd) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO1A_VITAL of AO1A is for VITAL_ACT end for; end CFG_AO1A_VITAL; ----- CELL AO1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO1B : entity is TRUE; end AO1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR ((B_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO1B_VITAL of AO1B is for VITAL_ACT end for; end CFG_AO1B_VITAL; ----- CELL AO1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO1C : entity is TRUE; end AO1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR ((B_ipd) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO1C_VITAL of AO1C is for VITAL_ACT end for; end CFG_AO1C_VITAL; ----- CELL AO1D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO1D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO1D : entity is TRUE; end AO1D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO1D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR (((NOT B_ipd)) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO1D_VITAL of AO1D is for VITAL_ACT end for; end CFG_AO1D_VITAL; ----- CELL AO1E ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO1E is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO1E : entity is TRUE; end AO1E; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO1E is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR (((NOT B_ipd)) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO1E_VITAL of AO1E is for VITAL_ACT end for; end CFG_AO1E_VITAL; ----- CELL AO2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO2 : entity is TRUE; end AO2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((B_ipd) AND (A_ipd)) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO2_VITAL of AO2 is for VITAL_ACT end for; end CFG_AO2_VITAL; ----- CELL AO2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO2A : entity is TRUE; end AO2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((B_ipd) AND ((NOT A_ipd))) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO2A_VITAL of AO2A is for VITAL_ACT end for; end CFG_AO2A_VITAL; ----- CELL AO2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO2B : entity is TRUE; end AO2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR (((NOT B_ipd)) AND ((NOT A_ipd))) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO2B_VITAL of AO2B is for VITAL_ACT end for; end CFG_AO2B_VITAL; ----- CELL AO2C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO2C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO2C : entity is TRUE; end AO2C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO2C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR ((B_ipd) AND ((NOT A_ipd))) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO2C_VITAL of AO2C is for VITAL_ACT end for; end CFG_AO2C_VITAL; ----- CELL AO2D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO2D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO2D : entity is TRUE; end AO2D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO2D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR (((NOT B_ipd)) AND ((NOT A_ipd))) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO2D_VITAL of AO2D is for VITAL_ACT end for; end CFG_AO2D_VITAL; ----- CELL AO2E ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO2E is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO2E : entity is TRUE; end AO2E; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO2E is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR (((NOT B_ipd)) AND ((NOT A_ipd))) OR ((NOT D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO2E_VITAL of AO2E is for VITAL_ACT end for; end CFG_AO2E_VITAL; ----- CELL AO3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO3 : entity is TRUE; end AO3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (D_ipd) OR ((B_ipd) AND ((NOT A_ipd)) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO3_VITAL of AO3 is for VITAL_ACT end for; end CFG_AO3_VITAL; ----- CELL AO3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO3A : entity is TRUE; end AO3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (D_ipd) OR ((B_ipd) AND (A_ipd) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO3A_VITAL of AO3A is for VITAL_ACT end for; end CFG_AO3A_VITAL; ----- CELL AO3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO3B : entity is TRUE; end AO3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (D_ipd) OR (((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO3B_VITAL of AO3B is for VITAL_ACT end for; end CFG_AO3B_VITAL; ----- CELL AO3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO3C : entity is TRUE; end AO3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (D_ipd) OR (((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO3C_VITAL of AO3C is for VITAL_ACT end for; end CFG_AO3C_VITAL; ----- CELL AO4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO4A : entity is TRUE; end AO4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of AO4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((C_ipd) AND (A_ipd) AND (D_ipd)) OR ((B_ipd) AND ((NOT A_ipd)) AND (C_ipd)) OR ((C_ipd) AND (B_ipd) AND (D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO4A_VITAL of AO4A is for VITAL_ACT end for; end CFG_AO4A_VITAL; ----- CELL AO5A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO5A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO5A : entity is TRUE; end AO5A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of AO5A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((C_ipd) AND (A_ipd)) OR ((B_ipd) AND ((NOT A_ipd))) OR ((C_ipd) AND (B_ipd)) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO5A_VITAL of AO5A is for VITAL_ACT end for; end CFG_AO5A_VITAL; ----- CELL AO6 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO6 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO6 : entity is TRUE; end AO6; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO6 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((D_ipd) AND (C_ipd)) OR ((B_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO6_VITAL of AO6 is for VITAL_ACT end for; end CFG_AO6_VITAL; ----- CELL AO6A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO6A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO6A : entity is TRUE; end AO6A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO6A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (((NOT D_ipd)) AND (C_ipd)) OR ((B_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO6A_VITAL of AO6A is for VITAL_ACT end for; end CFG_AO6A_VITAL; ----- CELL AO7 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO7 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO7 : entity is TRUE; end AO7; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO7 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (D_ipd) OR ((B_ipd) AND (A_ipd) AND (C_ipd)) OR (E_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO7_VITAL of AO7 is for VITAL_ACT end for; end CFG_AO7_VITAL; ----- CELL AO8 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO8 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO8 : entity is TRUE; end AO8; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO8 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (((NOT D_ipd)) AND ((NOT C_ipd))) OR ((B_ipd) AND (A_ipd)) OR (E_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE), 3 => (D_ipd'last_event, tpd_D_Y, TRUE), 4 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO8_VITAL of AO8 is for VITAL_ACT end for; end CFG_AO8_VITAL; ----- CELL AO9 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO9 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO9 : entity is TRUE; end AO9; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AO9 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((B_ipd) AND (A_ipd)) OR (D_ipd) OR (E_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO9_VITAL of AO9 is for VITAL_ACT end for; end CFG_AO9_VITAL; ----- CELL AOI1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI1 : entity is TRUE; end AOI1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AOI1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) OR ((B_ipd) AND (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI1_VITAL of AOI1 is for VITAL_ACT end for; end CFG_AOI1_VITAL; ----- CELL AOI1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI1A : entity is TRUE; end AOI1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AOI1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) OR ((B_ipd) AND ((NOT A_ipd))))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI1A_VITAL of AOI1A is for VITAL_ACT end for; end CFG_AOI1A_VITAL; ----- CELL AOI1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI1B : entity is TRUE; end AOI1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AOI1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT C_ipd)) OR ((B_ipd) AND (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI1B_VITAL of AOI1B is for VITAL_ACT end for; end CFG_AOI1B_VITAL; ----- CELL AOI1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI1C : entity is TRUE; end AOI1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AOI1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) OR (((NOT B_ipd)) AND ((NOT A_ipd))))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI1C_VITAL of AOI1C is for VITAL_ACT end for; end CFG_AOI1C_VITAL; ----- CELL AOI1D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI1D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI1D : entity is TRUE; end AOI1D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AOI1D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT C_ipd)) OR (((NOT B_ipd)) AND ((NOT A_ipd))))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI1D_VITAL of AOI1D is for VITAL_ACT end for; end CFG_AOI1D_VITAL; ----- CELL AOI2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI2A : entity is TRUE; end AOI2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AOI2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) OR ((B_ipd) AND ((NOT A_ipd))) OR (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI2A_VITAL of AOI2A is for VITAL_ACT end for; end CFG_AOI2A_VITAL; ----- CELL AOI2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI2B : entity is TRUE; end AOI2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AOI2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT C_ipd)) OR ((B_ipd) AND ((NOT A_ipd))) OR (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI2B_VITAL of AOI2B is for VITAL_ACT end for; end CFG_AOI2B_VITAL; ----- CELL AOI3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI3A : entity is TRUE; end AOI3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AOI3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((D_ipd) OR (A_ipd)) AND ((B_ipd) OR (A_ipd) OR (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI3A_VITAL of AOI3A is for VITAL_ACT end for; end CFG_AOI3A_VITAL; ----- CELL AOI4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI4 : entity is TRUE; end AOI4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AOI4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((D_ipd) AND (C_ipd)) OR ((B_ipd) AND (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI4_VITAL of AOI4 is for VITAL_ACT end for; end CFG_AOI4_VITAL; ----- CELL AOI4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI4A : entity is TRUE; end AOI4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AOI4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((D_ipd) AND ((NOT C_ipd))) OR ((B_ipd) AND (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE), 3 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI4A_VITAL of AOI4A is for VITAL_ACT end for; end CFG_AOI4A_VITAL; ----- CELL AOI5 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI5 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI5 : entity is TRUE; end AOI5; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AOI5 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((((NOT B_ipd)) AND (A_ipd) AND ((NOT C_ipd))) OR ((B_ipd) AND ((NOT A_ipd)) AND (C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI5_VITAL of AOI5 is for VITAL_ACT end for; end CFG_AOI5_VITAL; ----- CELL AX1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AX1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AX1 : entity is TRUE; end AX1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AX1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) XOR ((B_ipd) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AX1_VITAL of AX1 is for VITAL_ACT end for; end CFG_AX1_VITAL; ----- CELL AX1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AX1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AX1A : entity is TRUE; end AX1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AX1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) XOR ((B_ipd) AND ((NOT A_ipd))))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AX1A_VITAL of AX1A is for VITAL_ACT end for; end CFG_AX1A_VITAL; ----- CELL AX1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AX1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AX1B : entity is TRUE; end AX1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AX1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) XOR (((NOT B_ipd)) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AX1B_VITAL of AX1B is for VITAL_ACT end for; end CFG_AX1B_VITAL; ----- CELL AX1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AX1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AX1C : entity is TRUE; end AX1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AX1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) XOR ((B_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AX1C_VITAL of AX1C is for VITAL_ACT end for; end CFG_AX1C_VITAL; ----- CELL AX1D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AX1D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AX1D : entity is TRUE; end AX1D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AX1D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) XOR ((B_ipd) OR (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AX1D_VITAL of AX1D is for VITAL_ACT end for; end CFG_AX1D_VITAL; ----- CELL AX1E ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AX1E is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AX1E : entity is TRUE; end AX1E; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AX1E is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) XOR ((B_ipd) AND (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AX1E_VITAL of AX1E is for VITAL_ACT end for; end CFG_AX1E_VITAL; ----- CELL AXO1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXO1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXO1 : entity is TRUE; end AXO1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXO1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := ((C_ipd) XOR (B_ipd)) OR ((B_ipd) AND (A_ipd)); Y_zd := ((C_ipd) XOR (B_ipd)) OR ((B_ipd) AND (A_ipd)) OR ((A_ipd) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXO1_VITAL of AXO1 is for VITAL_ACT end for; end CFG_AXO1_VITAL; ----- CELL AXO2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXO2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXO2 : entity is TRUE; end AXO2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXO2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := ((C_ipd) XOR (B_ipd)) OR ((B_ipd) AND ((NOT A_ipd))); Y_zd := ((C_ipd) XOR (B_ipd)) OR ((B_ipd) AND ((NOT A_ipd))) OR ((NOT A_ipd) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXO2_VITAL of AXO2 is for VITAL_ACT end for; end CFG_AXO2_VITAL; ----- CELL AXO3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXO3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXO3 : entity is TRUE; end AXO3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXO3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := ((C_ipd) XOR (B_ipd)) OR (((NOT B_ipd)) AND (A_ipd)); Y_zd := ((C_ipd) XOR (B_ipd)) OR (((NOT B_ipd)) AND (A_ipd)) OR ((A_ipd) AND (NOT C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXO3_VITAL of AXO3 is for VITAL_ACT end for; end CFG_AXO3_VITAL; ----- CELL AXO5 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXO5 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXO5 : entity is TRUE; end AXO5; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXO5 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := ((C_ipd) XOR ((NOT B_ipd))) OR ((B_ipd) AND ((NOT A_ipd))); Y_zd := ((C_ipd) XOR ((NOT B_ipd))) OR ((B_ipd) AND ((NOT A_ipd))) OR ((NOT A_ipd) AND (NOT C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXO5_VITAL of AXO5 is for VITAL_ACT end for; end CFG_AXO5_VITAL; ----- CELL AXO6 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXO6 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXO6 : entity is TRUE; end AXO6; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXO6 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := ((C_ipd) XOR ((NOT B_ipd))) OR (((NOT B_ipd)) AND (A_ipd)); Y_zd := ((C_ipd) XOR ((NOT B_ipd))) OR (((NOT B_ipd)) AND (A_ipd)) OR ((A_ipd) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXO6_VITAL of AXO6 is for VITAL_ACT end for; end CFG_AXO6_VITAL; ----- CELL AXO7 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXO7 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXO7 : entity is TRUE; end AXO7; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXO7 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := ((C_ipd) XOR (B_ipd)) OR (((NOT B_ipd)) AND ((NOT A_ipd))); Y_zd := ((C_ipd) XOR (B_ipd)) OR (((NOT B_ipd)) AND ((NOT A_ipd))) OR ((NOT A_ipd) AND (NOT C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXO7_VITAL of AXO7 is for VITAL_ACT end for; end CFG_AXO7_VITAL; ----- CELL AXOI1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXOI1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXOI1 : entity is TRUE; end AXOI1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXOI1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := (NOT (((C_ipd) XOR (B_ipd)) OR ((B_ipd) AND (A_ipd)))); Y_zd := (NOT (((C_ipd) XOR (B_ipd)) OR ((B_ipd) AND (A_ipd)) OR ((A_ipd) AND (C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXOI1_VITAL of AXOI1 is for VITAL_ACT end for; end CFG_AXOI1_VITAL; ----- CELL AXOI2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXOI2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXOI2 : entity is TRUE; end AXOI2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXOI2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (NOT (((C_ipd) XOR (B_ipd)) OR ((B_ipd) AND ((NOT A_ipd))))); Y_zd := (NOT (((C_ipd) XOR (B_ipd)) OR ((B_ipd) AND ((NOT A_ipd))) OR ((NOT A_ipd) AND (C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXOI2_VITAL of AXOI2 is for VITAL_ACT end for; end CFG_AXOI2_VITAL; ----- CELL AXOI3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXOI3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXOI3 : entity is TRUE; end AXOI3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXOI3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (NOT (((C_ipd) XOR (B_ipd)) OR (((NOT B_ipd)) AND (A_ipd)))); Y_zd := (NOT (((C_ipd) XOR (B_ipd)) OR (((NOT B_ipd)) AND (A_ipd)) OR ((A_ipd) AND (NOT C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXOI3_VITAL of AXOI3 is for VITAL_ACT end for; end CFG_AXOI3_VITAL; ----- CELL AXOI4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXOI4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXOI4 : entity is TRUE; end AXOI4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXOI4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (NOT (((C_ipd) XOR ((NOT B_ipd))) OR ((B_ipd) AND (A_ipd)))); Y_zd := (NOT (((C_ipd) XOR ((NOT B_ipd))) OR ((B_ipd) AND (A_ipd)) OR ((A_ipd) AND (NOT C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXOI4_VITAL of AXOI4 is for VITAL_ACT end for; end CFG_AXOI4_VITAL; ----- CELL AXOI5 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXOI5 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXOI5 : entity is TRUE; end AXOI5; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXOI5 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (NOT (((C_ipd) XOR ((NOT B_ipd))) OR ((B_ipd) AND ((NOT A_ipd))))); Y_zd := (NOT (((C_ipd) XOR ((NOT B_ipd))) OR ((B_ipd) AND ((NOT A_ipd))) OR ((NOT A_ipd) AND (NOT C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXOI5_VITAL of AXOI5 is for VITAL_ACT end for; end CFG_AXOI5_VITAL; ----- CELL AXOI7 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AXOI7 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AXOI7 : entity is TRUE; end AXOI7; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of AXOI7 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (NOT (((C_ipd) XOR (B_ipd)) OR (((NOT B_ipd)) AND ((NOT A_ipd))))); Y_zd := (NOT (((C_ipd) XOR (B_ipd)) OR (((NOT B_ipd)) AND ((NOT A_ipd))) OR ((NOT A_ipd) AND (NOT C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AXOI7_VITAL of AXOI7 is for VITAL_ACT end for; end CFG_AXOI7_VITAL; ----- CELL BIBUF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity BIBUF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_PAD : VitalDelayType01z := (0.000 ns, 0.000 ns, 1.000 ns, 1.000 ns, 1.000 ns, 1.000 ns); tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; PAD : inout STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of BIBUF : entity is TRUE; end BIBUF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of BIBUF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL PAD_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (PAD_ipd, PAD, tipd_PAD); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, PAD_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS PAD_zd : STD_LOGIC is Results(1); ALIAS Y_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE PAD_GlitchData : VitalGlitchDataType; VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- PAD_zd := VitalBUFIF0 (data => D_ipd, enable => (NOT E_ipd)); Y_zd := TO_X01(PAD_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01Z ( OutSignal => PAD, GlitchData => PAD_GlitchData, OutSignalName => "PAD", OutTemp => PAD_zd, Paths => (0 => (E_ipd'last_event, tpd_E_PAD, TRUE), 1 => (D_ipd'last_event, VitalExtendToFillDelay(tpd_D_PAD), TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING, OutputMap => "UX01ZWLH-"); VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (PAD_ipd'last_event, tpd_PAD_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_BIBUF_VITAL of BIBUF is for VITAL_ACT end for; end CFG_BIBUF_VITAL; ----- CELL BUFA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity BUFA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of BUFA : entity is TRUE; end BUFA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of BUFA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_BUFA_VITAL of BUFA is for VITAL_ACT end for; end CFG_BUFA_VITAL; ----- CELL BUFD ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity BUFD is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of BUFD : entity is TRUE; end BUFD; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of BUFD is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_BUFD_VITAL of BUFD is for VITAL_ACT end for; end CFG_BUFD_VITAL; ----- CELL BUFF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity BUFF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of BUFF : entity is TRUE; end BUFF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of BUFF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_BUFF_VITAL of BUFF is for VITAL_ACT end for; end CFG_BUFF_VITAL; ----- CELL CLKBUF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CLKBUF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CLKBUF : entity is TRUE; end CLKBUF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CLKBUF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL PAD_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (PAD_ipd, PAD, tipd_PAD); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (PAD_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(PAD_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (PAD_ipd'last_event, tpd_PAD_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CLKBUF_VITAL of CLKBUF is for VITAL_ACT end for; end CFG_CLKBUF_VITAL; ----- CELL CLKBUFI ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CLKBUFI is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CLKBUFI : entity is TRUE; end CLKBUFI; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CLKBUFI is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL PAD_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (PAD_ipd, PAD, tipd_PAD); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (PAD_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT PAD_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (PAD_ipd'last_event, tpd_PAD_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CLKBUFI_VITAL of CLKBUFI is for VITAL_ACT end for; end CFG_CLKBUFI_VITAL; ----- CELL CLKINT ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CLKINT is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CLKINT : entity is TRUE; end CLKINT; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CLKINT is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CLKINT_VITAL of CLKINT is for VITAL_ACT end for; end CFG_CLKINT_VITAL; ----- CELL CLKINTI ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CLKINTI is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CLKINTI : entity is TRUE; end CLKINTI; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CLKINTI is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CLKINTI_VITAL of CLKINTI is for VITAL_ACT end for; end CFG_CLKINTI_VITAL; ----- CELL CM7 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CM7 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CM7 : entity is TRUE; end CM7; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CM7 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S0_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S0_ipd, S0, tipd_S0); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, D3_ipd, S0_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S0_ipd) AND (D3_ipd)) OR (((NOT -- S0_ipd)) AND (D2_ipd)))) OR (((NOT ((S11_ipd) OR (S10_ipd)))) AND -- (((S0_ipd) AND (D1_ipd)) OR (((NOT S0_ipd)) AND (D0_ipd)))); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, D0_ipd, S0_ipd); MUX2_Out := VitalMUX2(D3_ipd, D2_ipd, S0_ipd); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S0_ipd'last_event, tpd_S0_Y, TRUE), 3 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 4 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 5 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 6 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CM7_VITAL of CM7 is for VITAL_ACT end for; end CFG_CM7_VITAL; ----- CELL CM8 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CM8 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CM8 : entity is TRUE; end CM8; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CM8 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, D3_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S01_ipd) AND (S00_ipd) AND (D3_ipd)) -- OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D2_ipd)))) OR (((NOT -- ((S11_ipd) OR (S10_ipd)))) AND (((S01_ipd) AND (S00_ipd) AND -- (D1_ipd)) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D0_ipd)))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, D0_ipd, AND_Out); MUX2_Out := VitalMUX2(D3_ipd, D2_ipd, AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 6 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 7 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CM8_VITAL of CM8 is for VITAL_ACT end for; end CFG_CM8_VITAL; ----- CELL CM8F ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CM8F is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S11_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_FY : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; FY : out STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CM8F : entity is TRUE; end CM8F; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CM8F is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, D3_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; VARIABLE FY_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, D0_ipd, AND_Out); MUX2_Out := VitalMUX2(D3_ipd, D2_ipd, AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 6 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 7 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => FY, GlitchData => FY_GlitchData, OutSignalName => "FY", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_FY, TRUE), 1 => (S10_ipd'last_event, tpd_S10_FY, TRUE), 2 => (S01_ipd'last_event, tpd_S01_FY, TRUE), 3 => (S00_ipd'last_event, tpd_S00_FY, TRUE), 4 => (D3_ipd'last_event, tpd_D3_FY, TRUE), 5 => (D2_ipd'last_event, tpd_D2_FY, TRUE), 6 => (D1_ipd'last_event, tpd_D1_FY, TRUE), 7 => (D0_ipd'last_event, tpd_D0_FY, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CM8F_VITAL of CM8F is for VITAL_ACT end for; end CFG_CM8F_VITAL; ----- CELL CM8INV ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CM8INV is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CM8INV : entity is TRUE; end CM8INV; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CM8INV is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CM8INV_VITAL of CM8INV is for VITAL_ACT end for; end CFG_CM8INV_VITAL; ----- CELL CMA9 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMA9 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMA9 : entity is TRUE; end CMA9; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of CMA9 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, DB_ipd, D3_ipd, S01_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; CONSTANT CMA9_table : VitalTruthTableType(0 to 10, 0 to 5) := -- Input Pattern Response -- D0 DB D3 S01 S11 Y (( '-', '0', '-', '0', '-', '1'), --0 ( '-', '1', '-', '-', '1', '0'), ( '-', '0', '0', '1', '-', '0'), ( '1', '1', '-', '-', '0', '1'), ( '1', '-', '1', '-', '0', '1'), ( '-', '0', '1', '-', '-', '1'), --5 ( '0', '1', '-', '-', '-', '0'), ( '0', '-', '0', '1', '-', '0'), ( '1', '-', '-', '0', '0', '1'), ( '-', '0', '1', '1', '-', '1'), ( '-', '-', '0', '1', '1', '0')); --10 begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalTruthTable( TruthTable => CMA9_table, DataIn => ( D0_ipd, DB_ipd, D3_ipd, S01_ipd, S11_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 2 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 3 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 4 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMA9_VITAL of CMA9 is for VITAL_ACT end for; end CFG_CMA9_VITAL; ----- CELL CMAF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMAF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMAF : entity is TRUE; end CMAF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMAF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, DB_ipd, D2_ipd, D3_ipd, S01_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; CONSTANT CMAF_table : VitalTruthTableType(0 to 25, 0 to 6) := -- Input Pattern Response -- D0 D2 D3 DB S01 S11 Y (( '0', '0', '0', '-', '-', '-', '0'), --0 ( '1', '1', '1', '-', '-', '-', '1'), ( '0', '0', '-', '-', '0', '0', '0'), ( '1', '1', '-', '-', '0', '0', '1'), ( '0', '0', '-', '1', '-', '-', '0'), ( '1', '1', '-', '1', '-', '-', '1'), --5 ( '0', '0', '-', '-', '0', '-', '0'), ( '1', '1', '-', '-', '0', '-', '1'), ( '-', '0', '0', '-', '1', '1', '0'), ( '-', '1', '1', '-', '1', '1', '1'), ( '-', '0', '0', '0', '-', '-', '0'), --10 ( '-', '1', '1', '0', '-', '-', '1'), ( '-', '0', '0', '-', '-', '1', '0'), ( '-', '1', '1', '-', '-', '1', '1'), ( '0', '-', '0', '-', '1', '0', '0'), ( '1', '-', '1', '-', '1', '0', '1'), --15 ( '-', '0', '-', '0', '0', '-', '0'), ( '-', '1', '-', '0', '0', '-', '1'), ( '-', '0', '-', '1', '-', '1', '0'), ( '-', '1', '-', '1', '-', '1', '1'), ( '-', '0', '-', '-', '0', '1', '0'), --20 ( '-', '1', '-', '-', '0', '1', '1'), ( '-', '-', '0', '0', '1', '-', '0'), ( '-', '-', '1', '0', '1', '-', '1'), ( '0', '-', '-', '1', '-', '0', '0'), ( '1', '-', '-', '1', '-', '0', '1')); --25 begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalTruthTable( TruthTable => CMAF_table, DataIn => ( D0_ipd, D2_ipd, D3_ipd, DB_ipd, S01_ipd, S11_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 2 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 3 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 4 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 5 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMAF_VITAL of CMAF is for VITAL_ACT end for; end CFG_CMAF_VITAL; ----- CELL CMB3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMB3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMB3 : entity is TRUE; end CMB3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMB3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, DB_ipd, S00_ipd, S01_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (DB_ipd) OR (((NOT ((S11_ipd) OR (DB_ipd)))) AND (((S01_ipd) AND -- (S00_ipd) AND (D1_ipd)) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND -- (D0_ipd)))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2((NOT DB_ipd), S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, D0_ipd, AND_Out); MUX2_Out := VitalMUX2((NOT DB_ipd), (NOT DB_ipd), AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 2 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 3 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 4 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 5 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMB3_VITAL of CMB3 is for VITAL_ACT end for; end CFG_CMB3_VITAL; ----- CELL CMB7 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMB7 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMB7 : entity is TRUE; end CMB7; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMB7 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, DB_ipd, S00_ipd, S01_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; CONSTANT CMB7_table : VitalTruthTableType(0 to 24, 0 to 7) := -- Input Pattern Response -- D0 D1 D2 DB S00 S01 S11 Y (( '0', '0', '0', '1', '-', '-', '-', '0'), --0 ( '-', '-', '1', '0', '-', '-', '-', '1'), ( '-', '0', '-', '1', '1', '1', '0', '0'), ( '-', '1', '-', '-', '1', '1', '0', '1'), ( '0', '-', '-', '1', '0', '-', '0', '0'), ( '0', '-', '-', '1', '-', '0', '0', '0'), --5 ( '1', '-', '-', '1', '0', '-', '0', '1'), ( '1', '-', '-', '1', '-', '0', '0', '1'), ( '-', '-', '-', '1', '1', '1', '1', '0'), ( '-', '-', '-', '0', '1', '1', '-', '1'), ( '-', '-', '0', '0', '0', '-', '-', '0'), --10 ( '-', '-', '0', '0', '-', '0', '-', '0'), ( '-', '-', '0', '-', '0', '-', '1', '0'), ( '-', '-', '0', '-', '-', '0', '1', '0'), ( '0', '-', '0', '-', '0', '-', '-', '0'), ( '0', '-', '0', '-', '-', '0', '-', '0'), --15 ( '1', '-', '1', '-', '0', '-', '-', '1'), ( '1', '-', '1', '-', '-', '0', '-', '1'), ( '-', '-', '1', '-', '0', '-', '1', '1'), ( '-', '-', '1', '-', '-', '0', '1', '1'), ( '-', '0', '-', '1', '1', '1', '-', '0'), --20 ( '0', '0', '-', '1', '-', '-', '0', '0'), ( '1', '1', '-', '1', '-', '-', '0', '1'), ( '-', '-', '0', '1', '-', '-', '1', '0'), ( '1', '1', '1', '-', '-', '-', '0', '1')); begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalTruthTable ( TruthTable => CMB7_table, DataIn => ( D0_ipd, D1_ipd, D2_ipd, DB_ipd, S00_ipd, S01_ipd, S11_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 2 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 3 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 4 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 5 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 6 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMB7_VITAL of CMB7 is for VITAL_ACT end for; end CFG_CMB7_VITAL; ----- CELL CMBB ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMBB is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMBB : entity is TRUE; end CMBB; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMBB is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, DB_ipd, D3_ipd, S00_ipd, S01_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; CONSTANT CMBB_table : VitalTruthTableType(0 to 23, 0 to 7) := -- Input Pattern Response -- D0 D1 DB D3 S00 S01 S11 Y (( '0', '0', '1', '0', '-', '-', '-', '0'), --0 ( '-', '-', '0', '1', '-', '-', '-', '1'), ( '-', '-', '0', '-', '-', '0', '-', '1'), ( '-', '-', '1', '-', '-', '0', '1', '0'), ( '-', '-', '0', '-', '0', '-', '-', '1'), ( '-', '-', '1', '-', '0', '-', '1', '0'), --5 ( '0', '-', '1', '-', '-', '0', '0', '0'), ( '1', '-', '-', '-', '-', '0', '0', '1'), ( '0', '-', '1', '-', '0', '-', '0', '0'), ( '1', '-', '-', '-', '0', '-', '0', '1'), ( '-', '0', '1', '-', '1', '1', '0', '0'), --10 ( '-', '1', '1', '-', '1', '1', '0', '1'), ( '-', '-', '-', '0', '1', '1', '1', '0'), ( '-', '-', '-', '1', '1', '1', '1', '1'), ( '-', '-', '0', '0', '1', '1', '-', '0'), ( '-', '-', '0', '1', '1', '1', '-', '1'), --15 ( '-', '-', '1', '0', '-', '-', '1', '0'), ( '-', '0', '-', '0', '1', '1', '-', '0'), ( '-', '1', '-', '1', '1', '1', '-', '1'), ( '0', '-', '1', '-', '0', '-', '-', '0'), ( '0', '0', '1', '-', '-', '-', '0', '0'), --20 ( '1', '1', '1', '-', '-', '-', '0', '1'), ( '0', '-', '1', '-', '-', '0', '-', '0'), ( '1', '1', '-', '1', '-', '-', '0', '1')); begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalTruthTable( TruthTable => CMBB_table, DataIn => ( D0_ipd, D1_ipd, DB_ipd, D3_ipd, S00_ipd, S01_ipd, S11_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 2 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 3 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 6 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMBB_VITAL of CMBB is for VITAL_ACT end for; end CFG_CMBB_VITAL; ----- CELL CMBF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMBF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMBF : entity is TRUE; end CMBF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMBF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, D3_ipd, DB_ipd, S00_ipd, S01_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR ((NOT DB_ipd))) AND (((S01_ipd) AND (S00_ipd) AND -- (D3_ipd)) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D2_ipd)))) OR -- (((NOT ((S11_ipd) OR ((NOT DB_ipd))))) AND (((S01_ipd) AND (S00_ipd) -- AND (D1_ipd)) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D0_ipd)))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2((NOT DB_ipd), S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, D0_ipd, AND_Out); MUX2_Out := VitalMUX2(D3_ipd, D2_ipd, AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 2 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 3 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 6 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 7 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMBF_VITAL of CMBF is for VITAL_ACT end for; end CFG_CMBF_VITAL; ----- CELL CMEA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMEA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; D3 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMEA : entity is TRUE; end CMEA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMEA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (DB_ipd, D1_ipd, D3_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; CONSTANT CMEA_table : VitalTruthTableType(0 to 9, 0 to 6) := -- Input Pattern Response -- DB D1 D3 S01 S10 S11 Y (( '1', '-', '-', '-', '-', '-', '0'), --0 ( '0', '1', '1', '-', '-', '-', '1'), ( '0', '0', '-', '1', '0', '0', '0'), ( '0', '1', '-', '-', '0', '0', '1'), ( '0', '-', '0', '1', '1', '-', '0'), ( '0', '-', '0', '1', '-', '1', '0'), --5 ( '0', '-', '-', '0', '-', '-', '1'), ( '-', '0', '0', '1', '-', '-', '0'), ( '0', '-', '1', '-', '1', '-', '1'), ( '0', '-', '1', '-', '-', '1', '1')); begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalTruthTable( TruthTable => CMEA_table, DataIn => ( DB_ipd, D1_ipd, D3_ipd, S01_ipd, S10_ipd, S11_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 4 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 5 => (DB_ipd'last_event, tpd_DB_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMEA_VITAL of CMEA is for VITAL_ACT end for; end CFG_CMEA_VITAL; ----- CELL CMEB ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMEB is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMEB : entity is TRUE; end CMEB; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMEB is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, DB_ipd, D3_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; CONSTANT CMEB_table : VitalTruthTableType(0 to 24, 0 to 7) := -- Input Pattern Response -- D0 D1 DB D3 S01 S10 S11 Y (( '0', '0', '1', '0', '-', '-', '-', '0'), --0 ( '1', '1', '0', '1', '-', '-', '-', '1'), ( '0', '-', '-', '-', '0', '0', '0', '0'), ( '1', '-', '-', '-', '0', '0', '0', '1'), ( '0', '-', '1', '-', '-', '0', '0', '0'), ( '1', '-', '1', '-', '-', '0', '0', '1'), --5 ( '-', '-', '0', '1', '1', '1', '-', '1'), ( '-', '-', '0', '1', '1', '-', '1', '1'), ( '-', '0', '0', '-', '1', '0', '0', '0'), ( '-', '1', '0', '-', '1', '0', '0', '1'), ( '-', '-', '-', '0', '1', '1', '-', '0'), --10 ( '-', '-', '-', '0', '1', '-', '1', '0'), ( '-', '-', '1', '-', '-', '1', '-', '0'), ( '-', '-', '1', '-', '-', '-', '1', '0'), ( '-', '-', '0', '-', '0', '1', '-', '1'), ( '-', '0', '0', '0', '1', '-', '-', '0'), --15 ( '-', '1', '0', '1', '1', '-', '-', '1'), ( '0', '0', '-', '-', '-', '0', '0', '0'), ( '1', '1', '-', '-', '-', '0', '0', '1'), ( '0', '-', '1', '-', '-', '-', '-', '0'), ( '1', '-', '0', '-', '0', '-', '-', '1'), --20 ( '-', '-', '0', '1', '-', '1', '-', '1'), ( '-', '-', '0', '1', '-', '-', '1', '1'), ( '-', '-', '0', '-', '0', '-', '1', '1'), ( '0', '0', '-', '0', '1', '-', '-', '0')); begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalTruthTable( TruthTable => CMEB_table, DataIn => ( D0_ipd, D1_ipd, DB_ipd, D3_ipd, S01_ipd, S10_ipd, S11_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 6 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMEB_VITAL of CMEB is for VITAL_ACT end for; end CFG_CMEB_VITAL; ----- CELL CMEE ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMEE is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMEE : entity is TRUE; end CMEE; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMEE is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (DB_ipd, D1_ipd, D2_ipd, D3_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; CONSTANT CMEE_table : VitalTruthTableType(0 to 27, 0 to 7) := -- Input Pattern Response -- DB D1 D2 D3 S01 S10 S11 Y (( '1', '0', '0', '0', '-', '-', '-', '0'), --0 ( '0', '1', '1', '1', '-', '-', '-', '1'), ( '-', '0', '-', '-', '1', '0', '0', '0'), ( '0', '1', '-', '-', '1', '0', '0', '1'), ( '0', '-', '-', '0', '1', '1', '-', '0'), ( '0', '-', '-', '1', '1', '1', '-', '1'), --5 ( '0', '-', '-', '0', '1', '-', '1', '0'), ( '0', '-', '-', '1', '1', '-', '1', '1'), ( '1', '-', '-', '-', '-', '0', '0', '0'), ( '0', '-', '-', '-', '0', '0', '0', '1'), ( '-', '-', '0', '-', '0', '-', '1', '0'), --10 ( '-', '-', '1', '-', '0', '-', '1', '1'), ( '-', '-', '0', '-', '0', '1', '-', '0'), ( '-', '-', '1', '-', '0', '1', '-', '1'), ( '1', '-', '0', '-', '-', '-', '1', '0'), ( '1', '-', '1', '-', '-', '-', '1', '1'), --15 ( '1', '-', '0', '-', '-', '1', '-', '0'), ( '1', '-', '1', '-', '-', '1', '-', '1'), ( '1', '-', '0', '-', '-', '-', '-', '0'), ( '0', '-', '1', '-', '0', '-', '-', '1'), ( '-', '-', '0', '0', '-', '1', '-', '0'), --20 ( '-', '-', '1', '1', '-', '1', '-', '1'), ( '-', '-', '0', '0', '-', '-', '1', '0'), ( '0', '0', '-', '0', '1', '-', '-', '0'), ( '0', '1', '-', '1', '1', '-', '-', '1'), ( '-', '-', '1', '1', '-', '-', '1', '1'), --25 ( '0', '1', '-', '-', '-', '0', '0', '1'), ( '-', '0', '0', '0', '1', '-', '-', '0')); begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalTruthTable( TruthTable => CMEE_table, DataIn => ( DB_ipd, D1_ipd, D2_ipd, D3_ipd, S01_ipd, S10_ipd, S11_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 6 => (D1_ipd'last_event, tpd_D1_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMEE_VITAL of CMEE is for VITAL_ACT end for; end CFG_CMEE_VITAL; ----- CELL CMEF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMEF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; DB : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMEF : entity is TRUE; end CMEF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMEF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, D3_ipd, DB_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S01_ipd) AND ((NOT DB_ipd)) AND -- (D3_ipd)) OR (((NOT ((S01_ipd) AND ((NOT DB_ipd))))) AND (D2_ipd)))) -- OR (((NOT ((S11_ipd) OR (S10_ipd)))) AND (((S01_ipd) AND ((NOT -- DB_ipd)) AND (D1_ipd)) OR (((NOT ((S01_ipd) AND ((NOT DB_ipd))))) -- AND (D0_ipd)))); AND_Out := VitalAND2((NOT DB_ipd), S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, D0_ipd, AND_Out); MUX2_Out := VitalMUX2(D3_ipd, D2_ipd, AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 6 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 7 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMEF_VITAL of CMEF is for VITAL_ACT end for; end CFG_CMEF_VITAL; ----- CELL CMF1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMF1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMF1 : entity is TRUE; end CMF1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMF1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, DB_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (DB_ipd)) OR (((NOT ((S11_ipd) OR -- (S10_ipd)))) AND (((S01_ipd) AND (S00_ipd) AND (DB_ipd)) OR (((NOT -- ((S01_ipd) AND (S00_ipd)))) AND (D0_ipd)))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2((NOT DB_ipd), D0_ipd, AND_Out); MUX2_Out := VitalMUX2((NOT DB_ipd), (NOT DB_ipd), AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 5 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMF1_VITAL of CMF1 is for VITAL_ACT end for; end CFG_CMF1_VITAL; ----- CELL CMF2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMF2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMF2 : entity is TRUE; end CMF2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMF2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (DB_ipd, D1_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (DB_ipd)) OR (((NOT ((S11_ipd) OR -- (S10_ipd)))) AND (((S01_ipd) AND (S00_ipd) AND (D1_ipd)) OR (((NOT -- ((S01_ipd) AND (S00_ipd)))) AND (DB_ipd)))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, (NOT DB_ipd), AND_Out); MUX2_Out := VitalMUX2((NOT DB_ipd), (NOT DB_ipd), AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 5 => (DB_ipd'last_event, tpd_DB_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMF2_VITAL of CMF2 is for VITAL_ACT end for; end CFG_CMF2_VITAL; ----- CELL CMF3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMF3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMF3 : entity is TRUE; end CMF3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMF3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, DB_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND ((NOT DB_ipd))) OR (((NOT ((S11_ipd) OR -- (S10_ipd)))) AND (((S01_ipd) AND (S00_ipd) AND (D1_ipd)) OR (((NOT -- ((S01_ipd) AND (S00_ipd)))) AND (D0_ipd)))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, D0_ipd, AND_Out); MUX2_Out := VitalMUX2((NOT DB_ipd), (NOT DB_ipd), AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 5 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 6 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMF3_VITAL of CMF3 is for VITAL_ACT end for; end CFG_CMF3_VITAL; ----- CELL CMF4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMF4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D2 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMF4 : entity is TRUE; end CMF4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMF4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (DB_ipd, D2_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S01_ipd) AND (S00_ipd) AND (DB_ipd)) -- OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D2_ipd)))) OR (((NOT -- ((S11_ipd) OR (S10_ipd)))) AND (DB_ipd)); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2((NOT DB_ipd), (NOT DB_ipd), AND_Out); MUX2_Out := VitalMUX2((NOT DB_ipd), D2_ipd, AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 5 => (DB_ipd'last_event, tpd_DB_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMF4_VITAL of CMF4 is for VITAL_ACT end for; end CFG_CMF4_VITAL; ----- CELL CMF5 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMF5 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; D2 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMF5 : entity is TRUE; end CMF5; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMF5 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, DB_ipd, D2_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- ((S01_ipd) AND (S00_ipd) AND ((NOT DB_ipd))) OR (((NOT ((S01_ipd) AND -- (S00_ipd)))) AND ((((S11_ipd) OR (S10_ipd)) AND (D2_ipd)) OR (((NOT -- ((S11_ipd) OR (S10_ipd)))) AND (D0_ipd)))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2((NOT DB_ipd), D0_ipd, AND_Out); MUX2_Out := VitalMUX2((NOT DB_ipd), D2_ipd, AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 5 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 6 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMF5_VITAL of CMF5 is for VITAL_ACT end for; end CFG_CMF5_VITAL; ----- CELL CMF6 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMF6 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMF6 : entity is TRUE; end CMF6; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMF6 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (DB_ipd, D1_ipd, D2_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S01_ipd) AND (S00_ipd) AND ((NOT -- DB_ipd))) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D2_ipd)))) OR -- (((NOT ((S11_ipd) OR (S10_ipd)))) AND (((S01_ipd) AND (S00_ipd) AND -- (D1_ipd)) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND ((NOT -- DB_ipd))))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, (NOT DB_ipd), AND_Out); MUX2_Out := VitalMUX2((NOT DB_ipd), D2_ipd, AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 5 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 6 => (DB_ipd'last_event, tpd_DB_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMF6_VITAL of CMF6 is for VITAL_ACT end for; end CFG_CMF6_VITAL; ----- CELL CMF7 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMF7 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; DB : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMF7 : entity is TRUE; end CMF7; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMF7 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, DB_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S01_ipd) AND (S00_ipd) AND ((NOT -- DB_ipd))) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D2_ipd)))) OR -- (((NOT ((S11_ipd) OR (S10_ipd)))) AND (((S01_ipd) AND (S00_ipd) AND -- (D1_ipd)) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D0_ipd)))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, D0_ipd, AND_Out); MUX2_Out := VitalMUX2((NOT DB_ipd), D2_ipd, AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 5 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 6 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 7 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMF7_VITAL of CMF7 is for VITAL_ACT end for; end CFG_CMF7_VITAL; ----- CELL CMF8 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMF8 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMF8 : entity is TRUE; end CMF8; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMF8 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (DB_ipd, D3_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S01_ipd) AND (S00_ipd) AND (D3_ipd)) -- OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (DB_ipd)))) OR (((NOT -- ((S11_ipd) OR (S10_ipd)))) AND (DB_ipd)); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2((NOT DB_ipd), (NOT DB_ipd), AND_Out); MUX2_Out := VitalMUX2(D3_ipd, (NOT DB_ipd), AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 5 => (D3_ipd'last_event, tpd_D3_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMF8_VITAL of CMF8 is for VITAL_ACT end for; end CFG_CMF8_VITAL; ----- CELL CMF9 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMF9 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMF9 : entity is TRUE; end CMF9; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMF9 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, DB_ipd, D3_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S01_ipd) AND (S00_ipd) AND (D3_ipd)) -- OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND ((NOT DB_ipd))))) OR -- (((NOT ((S11_ipd) OR (S10_ipd)))) AND (((S01_ipd) AND (S00_ipd) AND -- ((NOT DB_ipd))) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND -- (D0_ipd)))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2((NOT DB_ipd), D0_ipd, AND_Out); MUX2_Out := VitalMUX2(D3_ipd, (NOT DB_ipd), AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 6 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMF9_VITAL of CMF9 is for VITAL_ACT end for; end CFG_CMF9_VITAL; ----- CELL CMFA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMFA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMFA : entity is TRUE; end CMFA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMFA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (DB_ipd, D1_ipd, D3_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- ((S01_ipd) AND (S00_ipd) AND ((((S11_ipd) OR (S10_ipd)) AND (D3_ipd)) -- OR (((NOT ((S11_ipd) OR (S10_ipd)))) AND (D1_ipd)))) OR (((NOT -- ((S01_ipd) AND (S00_ipd)))) AND ((NOT DB_ipd))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, (NOT DB_ipd), AND_Out); MUX2_Out := VitalMUX2(D3_ipd, (NOT DB_ipd), AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 6 => (DB_ipd'last_event, tpd_DB_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMFA_VITAL of CMFA is for VITAL_ACT end for; end CFG_CMFA_VITAL; ----- CELL CMFB ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMFB is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; DB : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMFB : entity is TRUE; end CMFB; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMFB is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, DB_ipd, D3_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S01_ipd) AND (S00_ipd) AND (D3_ipd)) -- OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND ((NOT DB_ipd))))) OR -- (((NOT ((S11_ipd) OR (S10_ipd)))) AND (((S01_ipd) AND (S00_ipd) AND -- (D1_ipd)) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D0_ipd)))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, D0_ipd, AND_Out); MUX2_Out := VitalMUX2(D3_ipd, (NOT DB_ipd), AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 6 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 7 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMFB_VITAL of CMFB is for VITAL_ACT end for; end CFG_CMFB_VITAL; ----- CELL CMFC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMFC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMFC : entity is TRUE; end CMFC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMFC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (DB_ipd, D2_ipd, D3_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S01_ipd) AND (S00_ipd) AND (D3_ipd)) -- OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D2_ipd)))) OR (((NOT -- ((S11_ipd) OR (S10_ipd)))) AND ((NOT DB_ipd))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2((NOT DB_ipd), (NOT DB_ipd), AND_Out); MUX2_Out := VitalMUX2(D3_ipd, D2_ipd, AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 6 => (DB_ipd'last_event, tpd_DB_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMFC_VITAL of CMFC is for VITAL_ACT end for; end CFG_CMFC_VITAL; ----- CELL CMFD ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMFD is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; DB : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMFD : entity is TRUE; end CMFD; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMFD is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, DB_ipd, D2_ipd, D3_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S01_ipd) AND (S00_ipd) AND (D3_ipd)) -- OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D2_ipd)))) OR (((NOT -- ((S11_ipd) OR (S10_ipd)))) AND (((S01_ipd) AND (S00_ipd) AND ((NOT -- DB_ipd))) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D0_ipd)))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2((NOT DB_ipd), D0_ipd, AND_Out); MUX2_Out := VitalMUX2(D3_ipd, D2_ipd, AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 6 => (DB_ipd'last_event, tpd_DB_Y, TRUE), 7 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMFD_VITAL of CMFD is for VITAL_ACT end for; end CFG_CMFD_VITAL; ----- CELL CMFE ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CMFE is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S11_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S10_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S01_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S00_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_DB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_DB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S00 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S01 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S10 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S11 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( DB : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S00 : in STD_ULOGIC; S01 : in STD_ULOGIC; S10 : in STD_ULOGIC; S11 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CMFE : entity is TRUE; end CMFE; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CMFE is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL DB_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S00_ipd : STD_ULOGIC := 'X'; SIGNAL S01_ipd : STD_ULOGIC := 'X'; SIGNAL S10_ipd : STD_ULOGIC := 'X'; SIGNAL S11_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (DB_ipd, DB, tipd_DB); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S00_ipd, S00, tipd_S00); VitalWireDelay (S01_ipd, S01, tipd_S01); VitalWireDelay (S10_ipd, S10, tipd_S10); VitalWireDelay (S11_ipd, S11, tipd_S11); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (DB_ipd, D1_ipd, D2_ipd, D3_ipd, S00_ipd, S01_ipd, S10_ipd, S11_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S11_ipd) OR (S10_ipd)) AND (((S01_ipd) AND (S00_ipd) AND (D3_ipd)) -- OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND (D2_ipd)))) OR (((NOT -- ((S11_ipd) OR (S10_ipd)))) AND (((S01_ipd) AND (S00_ipd) AND -- (D1_ipd)) OR (((NOT ((S01_ipd) AND (S00_ipd)))) AND ((NOT -- DB_ipd))))); AND_Out := VitalAND2(S00_ipd, S01_ipd); OR_Out := VitalOR2(S10_ipd, S11_ipd); MUX1_Out := VitalMUX2(D1_ipd, (NOT DB_ipd), AND_Out); MUX2_Out := VitalMUX2(D3_ipd, D2_ipd, AND_Out); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S11_ipd'last_event, tpd_S11_Y, TRUE), 1 => (S10_ipd'last_event, tpd_S10_Y, TRUE), 2 => (S01_ipd'last_event, tpd_S01_Y, TRUE), 3 => (S00_ipd'last_event, tpd_S00_Y, TRUE), 4 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 5 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 6 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 7 => (DB_ipd'last_event, tpd_DB_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CMFE_VITAL of CMFE is for VITAL_ACT end for; end CFG_CMFE_VITAL; ----- CELL CS1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CS1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CS1 : entity is TRUE; end CS1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CS1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, S_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- ((((B_ipd) AND (S_ipd)) OR (A_ipd)) AND (D_ipd)) OR ((C_ipd) AND -- ((NOT (((B_ipd) AND (S_ipd)) OR (A_ipd))))); AND_Out := VitalAND2(B_ipd, S_ipd); OR_Out := VitalOR2(A_ipd, AND_Out); Y_zd := VitalMUX2(D_ipd, C_ipd, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S_ipd'last_event, tpd_S_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE), 3 => (D_ipd'last_event, tpd_D_Y, TRUE), 4 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CS1_VITAL of CS1 is for VITAL_ACT end for; end CFG_CS1_VITAL; ----- CELL CS2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CS2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CS2 : entity is TRUE; end CS2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CS2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, S_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE AND_Out, OR_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- ((B_ipd) AND ((S_ipd) OR (A_ipd)) AND (D_ipd)) OR ((C_ipd) AND ((NOT -- ((B_ipd) AND ((S_ipd) OR (A_ipd)))))); OR_Out := VitalOR2(A_ipd, S_ipd); AND_Out := VitalAND2(B_ipd, OR_Out); Y_zd := VitalMUX2(D_ipd, C_ipd, AND_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S_ipd'last_event, tpd_S_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE), 3 => (D_ipd'last_event, tpd_D_Y, TRUE), 4 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CS2_VITAL of CS2 is for VITAL_ACT end for; end CFG_CS2_VITAL; ----- CELL CY2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CY2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; B0 : in STD_ULOGIC; B1 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CY2A : entity is TRUE; end CY2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CY2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A0_ipd : STD_ULOGIC := 'X'; SIGNAL A1_ipd : STD_ULOGIC := 'X'; SIGNAL B0_ipd : STD_ULOGIC := 'X'; SIGNAL B1_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A0_ipd, A0, tipd_A0); VitalWireDelay (A1_ipd, A1, tipd_A1); VitalWireDelay (B0_ipd, B0, tipd_B0); VitalWireDelay (B1_ipd, B1, tipd_B1); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A0_ipd, A1_ipd, B0_ipd, B1_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((B0_ipd) AND (A0_ipd) AND (A1_ipd)) OR ((B1_ipd) AND (A1_ipd)) OR ((B0_ipd) AND (A0_ipd) AND (B1_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B1_ipd'last_event, tpd_B1_Y, TRUE), 1 => (B0_ipd'last_event, tpd_B0_Y, TRUE), 2 => (A1_ipd'last_event, tpd_A1_Y, TRUE), 3 => (A0_ipd'last_event, tpd_A0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CY2A_VITAL of CY2A is for VITAL_ACT end for; end CFG_CY2A_VITAL; ----- CELL CY2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CY2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; B0 : in STD_ULOGIC; B1 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CY2B : entity is TRUE; end CY2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of CY2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A0_ipd : STD_ULOGIC := 'X'; SIGNAL A1_ipd : STD_ULOGIC := 'X'; SIGNAL B0_ipd : STD_ULOGIC := 'X'; SIGNAL B1_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A0_ipd, A0, tipd_A0); VitalWireDelay (A1_ipd, A1, tipd_A1); VitalWireDelay (B0_ipd, B0, tipd_B0); VitalWireDelay (B1_ipd, B1, tipd_B1); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A0_ipd, A1_ipd, B0_ipd, B1_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((A1_ipd) AND ((B0_ipd) OR (A0_ipd))) OR ((B1_ipd) AND (A1_ipd)) OR ((B1_ipd) AND ((B0_ipd) OR (A0_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B1_ipd'last_event, tpd_B1_Y, TRUE), 1 => (B0_ipd'last_event, tpd_B0_Y, TRUE), 2 => (A1_ipd'last_event, tpd_A1_Y, TRUE), 3 => (A0_ipd'last_event, tpd_A0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CY2B_VITAL of CY2B is for VITAL_ACT end for; end CFG_CY2B_VITAL; ----- CELL DF1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DF1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DF1 : entity is TRUE; end DF1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of DF1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DF1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DF1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DF1_Q_tab, DataIn => ( CLK_delayed, D_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DF1_VITAL of DF1 is for VITAL_ACT end for; end CFG_DF1_VITAL; ----- CELL DF1_CC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DF1_CC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DF1_CC : entity is TRUE; end DF1_CC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DF1_CC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DF1_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( L, H, H, x, H ), ( H, x, x, x, S ), ( x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DF1_CC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DF1_CC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DF1_Q_tab, DataIn => ( CLK_delayed, D_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DF1_CC_VITAL of DF1_CC is for VITAL_ACT end for; end CFG_DF1_CC_VITAL; ----- CELL DF1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DF1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DF1B : entity is TRUE; end DF1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of DF1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DF1_Q_tab, DataIn => ( CLK_ipd, D_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DF1B_VITAL of DF1B is for VITAL_ACT end for; end CFG_DF1B_VITAL; ----- CELL DFC1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFC1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFC1B : entity is TRUE; end DFC1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFC1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1B_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, H, H, x, H ), ( H, H, x, x, x, S ), ( H, x, x, L, x, S ), ( x, L, L, H, x, L ), ( U, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFC1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFC1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFC1B_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, D_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFC1B_VITAL of DFC1B is for VITAL_ACT end for; end CFG_DFC1B_VITAL; ----- CELL DFC1B_CC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFC1B_CC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFC1B_CC : entity is TRUE; end DFC1B_CC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFC1B_CC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1B_CC_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, H, H, x, H ), ( H, H, x, x, x, S ), ( H, x, x, L, x, S ), ( x, L, L, H, x, L ), ( U, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1B_CC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1B_CC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFC1B_CC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFC1B_CC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFC1B_CC_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, D_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFC1B_CC_VITAL of DFC1B_CC is for VITAL_ACT end for; end CFG_DFC1B_CC_VITAL; ----- CELL DFC1D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFC1D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFC1D : entity is TRUE; end DFC1D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFC1D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1B_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, H, H, x, H ), ( H, H, x, x, x, S ), ( H, x, x, L, x, S ), ( x, L, L, H, x, L ), ( U, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFC1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFC1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFC1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFC1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFC1B_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, D_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFC1D_VITAL of DFC1D is for VITAL_ACT end for; end CFG_DFC1D_VITAL; ----- CELL DFE1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE1B : entity is TRUE; end DFE1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE1B_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, L ), ( L, L, x, H, H, x, L ), ( L, H, H, x, H, x, H ), ( L, H, x, H, H, x, H ), ( L, x, L, L, H, x, L ), ( L, x, H, L, H, x, H ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT E_ipd)) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFE1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE1B_Q_tab, DataIn => ( CLK_delayed, Q_zd, D_delayed, E_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE1B_VITAL of DFE1B is for VITAL_ACT end for; end CFG_DFE1B_VITAL; ----- CELL DFE1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE1C : entity is TRUE; end DFE1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE1B_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, L ), ( L, L, x, H, H, x, L ), ( L, H, H, x, H, x, H ), ( L, H, x, H, H, x, H ), ( L, x, L, L, H, x, L ), ( L, x, H, L, H, x, H ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT E_ipd)) /= '0' , RefTransition => 'F', HeaderMsg => InstancePath & "/DFE1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFE1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Tviol_E_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE1B_Q_tab, DataIn => ( CLK_ipd, Q_zd, D_delayed, E_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE1C_VITAL of DFE1C is for VITAL_ACT end for; end CFG_DFE1C_VITAL; ----- CELL DFE3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE3C : entity is TRUE; end DFE3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L ), ( U, x, L, x, x, x, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((CLR_ipd) AND (NOT E_ipd)) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3C_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, Q_zd, D_delayed, E_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE3C_VITAL of DFE3C is for VITAL_ACT end for; end CFG_DFE3C_VITAL; ----- CELL DFE3D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE3D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE3D : entity is TRUE; end DFE3D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE3D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L ), ( U, x, L, x, x, x, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01((CLR_ipd) AND (NOT E_ipd)) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFE3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFE3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Tviol_E_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3C_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, Q_zd, D_delayed, E_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE3D_VITAL of DFE3D is for VITAL_ACT end for; end CFG_DFE3D_VITAL; ----- CELL DFE4F ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE4F is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE4F : entity is TRUE; end DFE4F; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE4F is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE4F_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, H, H, x, x, H, x, H ), ( L, H, x, H, x, H, x, H ), ( L, x, L, L, H, H, x, L ), ( L, x, H, L, x, H, x, H ), ( H, x, x, x, H, x, x, S ), ( x, x, x, x, L, x, x, H ), ( x, x, x, x, H, L, x, S ), ( x, H, x, x, U, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((PRE_ipd) AND (NOT E_ipd)) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE4F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE4F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFE4F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFE4F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_negedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE4F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE4F_Q_tab, DataIn => ( CLK_delayed, Q_zd, D_delayed, E_delayed, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE4F_VITAL of DFE4F is for VITAL_ACT end for; end CFG_DFE4F_VITAL; ----- CELL DFE4G ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE4G is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE4G : entity is TRUE; end DFE4G; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE4G is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE4F_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, H, H, x, x, H, x, H ), ( L, H, x, H, x, H, x, H ), ( L, x, L, L, H, H, x, L ), ( L, x, H, L, x, H, x, H ), ( H, x, x, x, H, x, x, S ), ( x, x, x, x, L, x, x, H ), ( x, x, x, x, H, L, x, S ), ( x, H, x, x, U, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01((PRE_ipd) AND (NOT E_ipd)) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE4G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE4G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFE4G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFE4G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_negedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE4G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_E_CLK_negedge or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE4F_Q_tab, DataIn => ( CLK_ipd, Q_zd, D_delayed, E_delayed, PRE_ipd, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE4G_VITAL of DFE4G is for VITAL_ACT end for; end CFG_DFE4G_VITAL; ----- CELL DFEG ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFEG is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFEG : entity is TRUE; end DFEG; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFEG is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFEG_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, x, L ), ( H, L, H, H, x, x, H, x, H ), ( H, L, H, x, H, x, H, x, H ), ( H, L, x, H, L, x, H, x, H ), ( H, H, x, x, x, H, x, x, S ), ( H, x, x, x, x, L, x, x, H ), ( H, x, x, x, x, H, L, x, S ), ( x, L, L, L, x, H, H, x, L ), ( x, L, L, x, H, H, H, x, L ), ( x, L, x, L, L, H, H, x, L ), ( U, x, L, x, x, H, x, x, L ), ( H, x, H, x, x, U, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(( (PRE_ipd) ) AND ( (CLR_ipd) ) AND ( (NOT E_ipd) ) ) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DFEG", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TO_X01(( (PRE_ipd) ) AND ( (CLR_ipd) ) ) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DFEG", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TO_X01(CLR_ipd) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DFEG", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFEG", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( (PRE_ipd) ) AND ( (CLR_ipd) ) ) /= '0', HeaderMsg => InstancePath &"/DFEG", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_negedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(CLR_ipd) /= '0', HeaderMsg => InstancePath &"/DFEG", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFEG", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Tviol_PRE_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_PRE or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFEG_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, Q_zd, D_delayed, E_delayed, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFEG_VITAL of DFEG is for VITAL_ACT end for; end CFG_DFEG_VITAL; ----- CELL DFEH ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFEH is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFEH : entity is TRUE; end DFEH; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFEH is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFEG_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, x, L ), ( H, L, H, H, x, x, H, x, H ), ( H, L, H, x, H, x, H, x, H ), ( H, L, x, H, L, x, H, x, H ), ( H, H, x, x, x, H, x, x, S ), ( H, x, x, x, x, L, x, x, H ), ( H, x, x, x, x, H, L, x, S ), ( x, L, L, L, x, H, H, x, L ), ( x, L, L, x, H, H, H, x, L ), ( x, L, x, L, L, H, H, x, L ), ( U, x, L, x, x, H, x, x, L ), ( H, x, H, x, x, U, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(( (PRE_ipd) ) AND ( (CLR_ipd) ) AND ( (NOT E_ipd) ) ) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DFEH", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TO_X01(( (PRE_ipd) ) AND ( (CLR_ipd) ) ) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DFEH", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TO_X01(CLR_ipd) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DFEH", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFEH", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( (PRE_ipd) ) AND ( (CLR_ipd) ) ) /= '0', HeaderMsg => InstancePath &"/DFEH", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_negedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(CLR_ipd) /= '0', HeaderMsg => InstancePath &"/DFEH", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFEH", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_E_CLK_negedge or Tviol_PRE_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFEG_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, Q_zd, D_delayed, E_delayed, PRE_ipd, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFEH_VITAL of DFEH is for VITAL_ACT end for; end CFG_DFEH_VITAL; ----- CELL DFP1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1 : entity is TRUE; end DFP1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1_Q_tab : VitalStateTableType := ( ( L, L, L, H, x, L ), ( L, H, x, H, x, H ), ( H, x, L, x, x, S ), ( x, x, L, L, x, S ), ( x, x, H, x, x, H ), ( x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFP1_Q_tab, DataIn => ( CLK_delayed, D_delayed, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1_VITAL of DFP1 is for VITAL_ACT end for; end CFG_DFP1_VITAL; ----- CELL DFP1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1A : entity is TRUE; end DFP1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1_Q_tab : VitalStateTableType := ( ( L, L, L, H, x, L ), ( L, H, x, H, x, H ), ( H, x, L, x, x, S ), ( x, x, L, L, x, S ), ( x, x, H, x, x, H ), ( x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFP1_Q_tab, DataIn => ( CLK_ipd, D_delayed, PRE_ipd, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1A_VITAL of DFP1A is for VITAL_ACT end for; end CFG_DFP1A_VITAL; ----- CELL DFP1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1B : entity is TRUE; end DFP1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1B_Q_tab : VitalStateTableType := ( ( L, L, H, H, x, L ), ( L, H, x, H, x, H ), ( H, x, H, x, x, S ), ( x, x, L, x, x, H ), ( x, x, H, L, x, S ), ( x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFP1B_Q_tab, DataIn => ( CLK_delayed, D_delayed, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1B_VITAL of DFP1B is for VITAL_ACT end for; end CFG_DFP1B_VITAL; ----- CELL DFP1B_CC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1B_CC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1B_CC : entity is TRUE; end DFP1B_CC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1B_CC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1B_CC_Q_tab : VitalStateTableType := ( ( L, L, H, H, x, L ), ( L, H, x, H, x, H ), ( H, x, H, x, x, S ), ( x, x, L, x, x, H ), ( x, x, H, L, x, S ), ( x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1B_CC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1B_CC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFP1B_CC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1B_CC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFP1B_CC_Q_tab, DataIn => ( CLK_delayed, D_delayed, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1B_CC_VITAL of DFP1B_CC is for VITAL_ACT end for; end CFG_DFP1B_CC_VITAL; ----- CELL DFP1D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1D : entity is TRUE; end DFP1D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1B_Q_tab : VitalStateTableType := ( ( L, L, H, H, x, L ), ( L, H, x, H, x, H ), ( H, x, H, x, x, S ), ( x, x, L, x, x, H ), ( x, x, H, L, x, S ), ( x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFP1B_Q_tab, DataIn => ( CLK_ipd, D_delayed, PRE_ipd, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1D_VITAL of DFP1D is for VITAL_ACT end for; end CFG_DFP1D_VITAL; ----- CELL DFPC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFPC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFPC : entity is TRUE; end DFPC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFPC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFPC_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, L ), ( H, L, H, x, H, x, H ), ( H, H, x, L, x, x, S ), ( H, x, x, L, L, x, S ), ( H, x, x, H, x, x, H ), ( x, L, L, L, H, x, L ), ( U, x, x, x, x, L, L ), ( H, x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_PRE_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_PRE or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFPC_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, D_delayed, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFPC_VITAL of DFPC is for VITAL_ACT end for; end CFG_DFPC_VITAL; ----- CELL DFPCB ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFPCB is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFPCB : entity is TRUE; end DFPCB; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFPCB is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFPCB_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, L ), ( H, L, H, x, H, x, H ), ( H, H, x, H, x, x, S ), ( H, x, x, L, x, x, H ), ( H, x, x, H, L, x, S ), ( x, L, L, H, H, x, L ), ( U, x, x, x, x, L, L ), ( H, x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(( (NOT PRE_ipd) ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFPCB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFPCB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFPCB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( (NOT PRE_ipd) ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DFPCB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_negedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFPCB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFPCB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_PRE_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_PRE or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFPCB_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, D_delayed, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFPCB_VITAL of DFPCB is for VITAL_ACT end for; end CFG_DFPCB_VITAL; ----- CELL DFPCC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFPCC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFPCC : entity is TRUE; end DFPCC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFPCC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFPCB_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, L ), ( H, L, H, x, H, x, H ), ( H, H, x, H, x, x, S ), ( H, x, x, L, x, x, H ), ( H, x, x, H, L, x, S ), ( x, L, L, H, H, x, L ), ( U, x, x, x, x, L, L ), ( H, x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(( (NOT PRE_ipd) ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFPCC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFPCC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFPCC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( (NOT PRE_ipd) ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DFPCC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_negedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFPCC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFPCC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_PRE_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFPCB_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, D_delayed, PRE_ipd, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFPCC_VITAL of DFPCC is for VITAL_ACT end for; end CFG_DFPCC_VITAL; ----- CELL DL1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL1 : entity is TRUE; end DL1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of DL1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 1); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DL1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DL1_Q_tab, DataIn => ( D_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL1_VITAL of DL1 is for VITAL_ACT end for; end CFG_DL1_VITAL; ----- CELL DL1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL1B : entity is TRUE; end DL1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of DL1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 1); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DL1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DL1B_Q_tab, DataIn => ( G_ipd, D_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL1B_VITAL of DL1B is for VITAL_ACT end for; end CFG_DL1B_VITAL; ----- CELL DL2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL2A : entity is TRUE; end DL2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DL2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DL2A_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, H, x, H, x, H ), ( H, x, L, L, x, S ), ( H, x, H, x, x, H ), ( x, L, L, H, x, L ), ( U, x, x, x, L, L ), ( H, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_negedge, TimingData => Tmkr_PRE_G_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_negedge_negedge, Removal => thold_PRE_G_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_negedge, TimingData => Tmkr_CLR_G_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_posedge_negedge, Removal => thold_CLR_G_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_PRE_G_negedge or Pviol_PRE or Tviol_CLR_G_negedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DL2A_Q_tab, DataIn => ( CLR_ipd, D_ipd, PRE_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 3 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL2A_VITAL of DL2A is for VITAL_ACT end for; end CFG_DL2A_VITAL; ----- CELL DL2C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL2C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL2C : entity is TRUE; end DL2C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DL2C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DL2C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, H, x, x, H ), ( H, H, x, L, x, S ), ( H, x, x, H, x, H ), ( x, L, L, L, x, L ), ( U, x, x, x, L, L ), ( H, x, x, U, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_negedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_posedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Tviol_CLR_G_posedge or Pviol_PRE or Pviol_G or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DL2C_Q_tab, DataIn => ( CLR_ipd, G_ipd, D_ipd, PRE_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 3 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL2C_VITAL of DL2C is for VITAL_ACT end for; end CFG_DL2C_VITAL; ----- CELL DLC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLC : entity is TRUE; end DLC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLC_Q_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, H, H, x, H ), ( H, x, L, x, S ), ( x, L, H, x, L ), ( U, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_negedge, TimingData => Tmkr_CLR_G_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_posedge_negedge, Removal => thold_CLR_G_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DLC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_CLR_G_negedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLC_Q_tab, DataIn => ( CLR_ipd, D_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLC_VITAL of DLC is for VITAL_ACT end for; end CFG_DLC_VITAL; ----- CELL DLC1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLC1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLC1 : entity is TRUE; end DLC1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLC1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLC1_Q_tab : VitalStateTableType := ( ( L, H, x, x, L ), ( H, H, L, x, H ), ( x, L, L, x, S ), ( x, x, H, x, L ), ( x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_negedge, TimingData => Tmkr_CLR_G_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_negedge, Removal => thold_CLR_G_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DLC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_CLR_G_negedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLC1_Q_tab, DataIn => ( D_ipd, G_ipd, CLR_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLC1_VITAL of DLC1 is for VITAL_ACT end for; end CFG_DLC1_VITAL; ----- CELL DLC1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLC1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLC1A : entity is TRUE; end DLC1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLC1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLC1A_Q_tab : VitalStateTableType := ( ( L, L, x, x, L ), ( L, H, L, x, H ), ( H, x, L, x, S ), ( x, x, H, x, L ), ( x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DLC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_CLR_G_posedge or Pviol_G or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLC1A_Q_tab, DataIn => ( G_ipd, D_ipd, CLR_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLC1A_VITAL of DLC1A is for VITAL_ACT end for; end CFG_DLC1A_VITAL; ----- CELL DLCA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLCA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLCA : entity is TRUE; end DLCA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLCA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLCA_Q_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, L, H, x, H ), ( H, H, x, x, S ), ( x, L, L, x, L ), ( U, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_posedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DLCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_CLR_G_posedge or Pviol_G or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLCA_Q_tab, DataIn => ( CLR_ipd, G_ipd, D_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLCA_VITAL of DLCA is for VITAL_ACT end for; end CFG_DLCA_VITAL; ----- CELL DLE2C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLE2C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_E_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLE2C : entity is TRUE; end DLE2C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLE2C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLE2C_Q_tab : VitalStateTableType := ( ( L, L, L, x, x, L ), ( L, L, H, L, x, H ), ( H, x, x, L, x, S ), ( x, H, x, L, x, S ), ( x, x, x, H, x, L ), ( x, x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd OR E_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_posedge, TimingData => Tmkr_D_E_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_posedge, SetupLow => tsetup_D_E_noedge_posedge, HoldHigh => thold_D_E_noedge_posedge, HoldLow => thold_D_E_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd OR G_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_E_posedge, TimingData => Tmkr_CLR_E_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, Recovery => trecovery_CLR_E_negedge_posedge, Removal => thold_CLR_E_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_E_negedge, CheckEnabled => TO_X01(CLR_ipd OR G_ipd) /= '1', HeaderMsg => InstancePath &"/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(CLR_ipd OR E_ipd) /= '1', HeaderMsg => InstancePath &"/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_CLR_G_posedge or Pviol_E or Tviol_D_E_posedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLE2C_Q_tab, DataIn => ( G_ipd, E_ipd, D_ipd, CLR_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE), 3 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLE2C_VITAL of DLE2C is for VITAL_ACT end for; end CFG_DLE2C_VITAL; ----- CELL DLE3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLE3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_E_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLE3B : entity is TRUE; end DLE3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLE3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLE3B_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, L ), ( L, L, H, x, x, H ), ( H, x, x, L, x, S ), ( x, H, x, L, x, S ), ( x, x, x, H, x, H ), ( x, x, x, U, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd OR E_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_posedge, TimingData => Tmkr_D_E_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_posedge, SetupLow => tsetup_D_E_noedge_posedge, HoldHigh => thold_D_E_noedge_posedge, HoldLow => thold_D_E_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd OR G_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_negedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_E_posedge, TimingData => Tmkr_PRE_E_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, Recovery => trecovery_PRE_E_negedge_posedge, Removal => thold_PRE_E_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_E_negedge, CheckEnabled => TO_X01(PRE_ipd OR G_ipd) /= '1', HeaderMsg => InstancePath &"/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(PRE_ipd OR E_ipd) /= '1', HeaderMsg => InstancePath &"/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Pviol_E or Pviol_PRE or Tviol_D_E_posedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLE3B_Q_tab, DataIn => ( G_ipd, E_ipd, D_ipd, PRE_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE), 3 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLE3B_VITAL of DLE3B is for VITAL_ACT end for; end CFG_DLE3B_VITAL; ----- CELL DLE3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLE3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_E_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLE3C : entity is TRUE; end DLE3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLE3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLE3C_Q_tab : VitalStateTableType := ( ( L, L, L, H, x, L ), ( L, L, H, x, x, H ), ( H, x, x, H, x, S ), ( x, H, x, H, x, S ), ( x, x, x, L, x, H ), ( x, x, x, U, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) OR E_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_posedge, TimingData => Tmkr_D_E_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_posedge, SetupLow => tsetup_D_E_noedge_posedge, HoldHigh => thold_D_E_noedge_posedge, HoldLow => thold_D_E_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) OR G_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_posedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_E_posedge, TimingData => Tmkr_PRE_E_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, Recovery => trecovery_PRE_E_posedge_posedge, Removal => thold_PRE_E_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_E_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) OR G_ipd ) /= '1', HeaderMsg => InstancePath &"/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) OR E_ipd ) /= '1', HeaderMsg => InstancePath &"/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Pviol_E or Pviol_PRE or Tviol_D_E_posedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLE3C_Q_tab, DataIn => ( G_ipd, E_ipd, D_ipd, PRE_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE), 3 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLE3C_VITAL of DLE3C is for VITAL_ACT end for; end CFG_DLE3C_VITAL; ----- CELL DLP1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLP1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLP1 : entity is TRUE; end DLP1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLP1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLP1_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( H, x, H, x, H ), ( x, L, L, x, S ), ( x, H, x, x, H ), ( x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_negedge, TimingData => Tmkr_PRE_G_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_negedge_negedge, Removal => thold_PRE_G_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DLP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_PRE_G_negedge or Pviol_PRE or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLP1_Q_tab, DataIn => ( D_ipd, PRE_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLP1_VITAL of DLP1 is for VITAL_ACT end for; end CFG_DLP1_VITAL; ----- CELL DLP1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLP1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLP1A : entity is TRUE; end DLP1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLP1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLP1A_Q_tab : VitalStateTableType := ( ( L, L, L, x, L ), ( L, H, x, x, H ), ( H, x, L, x, S ), ( x, x, H, x, H ), ( x, x, U, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_negedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DLP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Pviol_PRE or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLP1A_Q_tab, DataIn => ( G_ipd, D_ipd, PRE_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLP1A_VITAL of DLP1A is for VITAL_ACT end for; end CFG_DLP1A_VITAL; ----- CELL DLP1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLP1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLP1B : entity is TRUE; end DLP1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLP1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLP1B_Q_tab : VitalStateTableType := ( ( L, H, H, x, L ), ( H, x, H, x, H ), ( x, L, x, x, H ), ( x, H, L, x, S ), ( x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_negedge, TimingData => Tmkr_PRE_G_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_posedge_negedge, Removal => thold_PRE_G_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DLP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_PRE_G_negedge or Pviol_PRE or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLP1B_Q_tab, DataIn => ( D_ipd, PRE_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLP1B_VITAL of DLP1B is for VITAL_ACT end for; end CFG_DLP1B_VITAL; ----- CELL DLP1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLP1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLP1C : entity is TRUE; end DLP1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLP1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLP1C_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( L, H, x, x, H ), ( H, x, H, x, S ), ( x, x, L, x, H ), ( x, x, U, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_posedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DLP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Pviol_PRE or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLP1C_Q_tab, DataIn => ( G_ipd, D_ipd, PRE_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLP1C_VITAL of DLP1C is for VITAL_ACT end for; end CFG_DLP1C_VITAL; ----- CELL FA1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity FA1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); attribute VITAL_LEVEL0 of FA1 : entity is TRUE; end FA1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of FA1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL CI_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (CI_ipd, CI, tipd_CI); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, CI_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS S_zd : STD_LOGIC is Results(1); ALIAS CO_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE S_GlitchData : VitalGlitchDataType; VARIABLE CO_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- S_zd := (B_ipd) XOR (A_ipd) XOR (CI_ipd); CO_zd := ((CI_ipd) AND (A_ipd)) OR ((A_ipd) AND (B_ipd)) OR ((CI_ipd) AND (B_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_S, TRUE), 1 => (B_ipd'last_event, tpd_B_S, TRUE), 2 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_CO, TRUE), 1 => (B_ipd'last_event, tpd_B_CO, TRUE), 2 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_FA1_VITAL of FA1 is for VITAL_ACT end for; end CFG_FA1_VITAL; ----- CELL FA1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity FA1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); attribute VITAL_LEVEL0 of FA1A : entity is TRUE; end FA1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of FA1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL CI_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (CI_ipd, CI, tipd_CI); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, CI_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS S_zd : STD_LOGIC is Results(1); ALIAS CO_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE S_GlitchData : VitalGlitchDataType; VARIABLE CO_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- S_zd := (((NOT A_ipd)) AND ((((NOT B_ipd)) AND (A_ipd)) OR (((NOT B_ipd)) AND (CI_ipd) AND ((NOT A_ipd))) OR ((CI_ipd) AND (B_ipd) AND (A_ipd))) AND (CI_ipd)) OR (((NOT A_ipd)) AND (B_ipd) AND ((NOT CI_ipd))) OR ((A_ipd) AND ((((NOT B_ipd)) AND (A_ipd)) OR (((NOT B_ipd)) AND (CI_ipd) AND ((NOT A_ipd))) OR ((CI_ipd) AND (B_ipd) AND (A_ipd))) AND ((NOT CI_ipd))) OR ((A_ipd) AND (B_ipd) AND (CI_ipd)); CO_zd := (((NOT B_ipd)) AND (A_ipd)) OR (((NOT B_ipd)) AND (CI_ipd)) OR ((CI_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_S, TRUE), 1 => (B_ipd'last_event, tpd_B_S, TRUE), 2 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_CO, TRUE), 1 => (B_ipd'last_event, tpd_B_CO, TRUE), 2 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_FA1A_VITAL of FA1A is for VITAL_ACT end for; end CFG_FA1A_VITAL; ----- CELL FA1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity FA1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); attribute VITAL_LEVEL0 of FA1B : entity is TRUE; end FA1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of FA1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL CI_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (CI_ipd, CI, tipd_CI); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, CI_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS S_zd : STD_LOGIC is Results(1); ALIAS CO_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE S_GlitchData : VitalGlitchDataType; VARIABLE CO_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- S_zd := ((((((CI_ipd) AND ((NOT B_ipd)) AND (A_ipd)) OR ((((CI_ipd) AND (B_ipd)) OR ((NOT B_ipd))) AND ((NOT A_ipd)))) AND (CI_ipd)) OR ((B_ipd) AND ((NOT CI_ipd)))) AND (A_ipd)) OR ((((B_ipd) AND (CI_ipd)) OR ((((CI_ipd) AND ((NOT B_ipd)) AND (A_ipd)) OR ((((CI_ipd) AND (B_ipd)) OR ((NOT B_ipd))) AND ((NOT A_ipd)))) AND ((NOT CI_ipd)))) AND ((NOT A_ipd))); CO_zd := ((CI_ipd) AND ((NOT B_ipd))) OR ((CI_ipd) AND ((NOT A_ipd))) OR (((NOT B_ipd)) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_S, TRUE), 1 => (B_ipd'last_event, tpd_B_S, TRUE), 2 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_CO, TRUE), 1 => (B_ipd'last_event, tpd_B_CO, TRUE), 2 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_FA1B_VITAL of FA1B is for VITAL_ACT end for; end CFG_FA1B_VITAL; ----- CELL FA2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity FA2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); attribute VITAL_LEVEL0 of FA2A : entity is TRUE; end FA2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of FA2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A0_ipd : STD_ULOGIC := 'X'; SIGNAL A1_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL CI_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A0_ipd, A0, tipd_A0); VitalWireDelay (A1_ipd, A1, tipd_A1); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (CI_ipd, CI, tipd_CI); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A0_ipd, A1_ipd, B_ipd, CI_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS S_zd : STD_LOGIC is Results(1); ALIAS CO_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE S_GlitchData : VitalGlitchDataType; VARIABLE CO_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- S_zd := (((NOT ((A1_ipd) OR (A0_ipd)))) AND ((((A1_ipd) OR (A0_ipd)) AND ((NOT B_ipd))) OR (((NOT B_ipd)) AND (CI_ipd) AND ((NOT ((A1_ipd) OR (A0_ipd))))) OR ((CI_ipd) AND (B_ipd) AND ((A1_ipd) OR (A0_ipd)))) AND (CI_ipd)) OR (((NOT ((A1_ipd) OR (A0_ipd)))) AND (B_ipd) AND ((NOT CI_ipd))) OR (((A1_ipd) OR (A0_ipd)) AND ((((A1_ipd) OR (A0_ipd)) AND ((NOT B_ipd))) OR (((NOT B_ipd)) AND (CI_ipd) AND ((NOT ((A1_ipd) OR (A0_ipd))))) OR ((CI_ipd) AND (B_ipd) AND ((A1_ipd) OR (A0_ipd)))) AND ((NOT CI_ipd))) OR (((A1_ipd) OR (A0_ipd)) AND (B_ipd) AND (CI_ipd)); --CO_zd := -- (((A1_ipd) OR (A0_ipd)) AND ((NOT B_ipd))) OR (((NOT B_ipd)) AND -- (CI_ipd) AND ((NOT ((A1_ipd) OR (A0_ipd))))) OR ((CI_ipd) AND -- (B_ipd) AND ((A1_ipd) OR (A0_ipd))); CO_zd := (((A1_ipd) AND (NOT B_ipd)) OR ((A0_ipd) AND (NOT B_ipd)) OR ((A0_ipd) AND (CI_ipd)) OR ((A1_ipd) AND (CI_ipd)) OR ((NOT B_ipd) AND (CI_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_S, TRUE), 1 => (B_ipd'last_event, tpd_B_S, TRUE), 2 => (A1_ipd'last_event, tpd_A1_S, TRUE), 3 => (A0_ipd'last_event, tpd_A0_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_CO, TRUE), 1 => (B_ipd'last_event, tpd_B_CO, TRUE), 2 => (A1_ipd'last_event, tpd_A1_CO, TRUE), 3 => (A0_ipd'last_event, tpd_A0_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_FA2A_VITAL of FA2A is for VITAL_ACT end for; end CFG_FA2A_VITAL; ----- CELL GAND2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GAND2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GAND2 : entity is TRUE; end GAND2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of GAND2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (G_ipd) AND (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GAND2_VITAL of GAND2 is for VITAL_ACT end for; end CFG_GAND2_VITAL; ----- CELL GMX4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GMX4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0 : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GMX4 : entity is TRUE; end GMX4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of GMX4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S0_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S0_ipd, S0, tipd_S0); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, D3_ipd, S0_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalMUX (data => (D3_ipd, D1_ipd, D2_ipd, D0_ipd), dselect => (S0_ipd, G_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (S0_ipd'last_event, tpd_S0_Y, TRUE), 2 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 3 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 4 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 5 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GMX4_VITAL of GMX4 is for VITAL_ACT end for; end CFG_GMX4_VITAL; ----- CELL GNAND2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GNAND2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GNAND2 : entity is TRUE; end GNAND2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of GNAND2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((G_ipd) AND (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GNAND2_VITAL of GNAND2 is for VITAL_ACT end for; end CFG_GNAND2_VITAL; ----- CELL GND ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GND is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True); port( Y : out STD_ULOGIC := '0'); attribute VITAL_LEVEL0 of GND : entity is TRUE; end GND; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of GND is attribute VITAL_LEVEL0 of VITAL_ACT : architecture is TRUE; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin -- empty end block; -------------------- -- BEHAVIOR SECTION -------------------- Y <= '0'; end VITAL_ACT; configuration CFG_GND_VITAL of GND is for VITAL_ACT end for; end CFG_GND_VITAL; ----- CELL GNOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GNOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GNOR2 : entity is TRUE; end GNOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of GNOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((G_ipd) OR (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GNOR2_VITAL of GNOR2 is for VITAL_ACT end for; end CFG_GNOR2_VITAL; ----- CELL GOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GOR2 : entity is TRUE; end GOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of GOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (G_ipd) OR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GOR2_VITAL of GOR2 is for VITAL_ACT end for; end CFG_GOR2_VITAL; ----- CELL GXOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GXOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GXOR2 : entity is TRUE; end GXOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of GXOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (G_ipd) XOR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GXOR2_VITAL of GXOR2 is for VITAL_ACT end for; end CFG_GXOR2_VITAL; ----- CELL HA1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity HA1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); attribute VITAL_LEVEL0 of HA1 : entity is TRUE; end HA1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of HA1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS CO_zd : STD_LOGIC is Results(1); ALIAS S_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE CO_GlitchData : VitalGlitchDataType; VARIABLE S_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- CO_zd := (B_ipd) AND (A_ipd); S_zd := (B_ipd) XOR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (B_ipd'last_event, tpd_B_CO, TRUE), 1 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (B_ipd'last_event, tpd_B_S, TRUE), 1 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_HA1_VITAL of HA1 is for VITAL_ACT end for; end CFG_HA1_VITAL; ----- CELL HA1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity HA1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); attribute VITAL_LEVEL0 of HA1A : entity is TRUE; end HA1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of HA1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS CO_zd : STD_LOGIC is Results(1); ALIAS S_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE CO_GlitchData : VitalGlitchDataType; VARIABLE S_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- CO_zd := (B_ipd) AND ((NOT A_ipd)); S_zd := (NOT ((B_ipd) XOR (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (B_ipd'last_event, tpd_B_CO, TRUE), 1 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (B_ipd'last_event, tpd_B_S, TRUE), 1 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_HA1A_VITAL of HA1A is for VITAL_ACT end for; end CFG_HA1A_VITAL; ----- CELL HA1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity HA1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); attribute VITAL_LEVEL0 of HA1B : entity is TRUE; end HA1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of HA1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS CO_zd : STD_LOGIC is Results(1); ALIAS S_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE CO_GlitchData : VitalGlitchDataType; VARIABLE S_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- CO_zd := (NOT ((B_ipd) AND (A_ipd))); S_zd := (NOT ((B_ipd) XOR (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (B_ipd'last_event, tpd_B_CO, TRUE), 1 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (B_ipd'last_event, tpd_B_S, TRUE), 1 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_HA1B_VITAL of HA1B is for VITAL_ACT end for; end CFG_HA1B_VITAL; ----- CELL HA1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity HA1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); attribute VITAL_LEVEL0 of HA1C : entity is TRUE; end HA1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of HA1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS CO_zd : STD_LOGIC is Results(1); ALIAS S_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE CO_GlitchData : VitalGlitchDataType; VARIABLE S_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- CO_zd := (NOT ((B_ipd) AND (A_ipd))); S_zd := (B_ipd) XOR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (B_ipd'last_event, tpd_B_CO, TRUE), 1 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (B_ipd'last_event, tpd_B_S, TRUE), 1 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_HA1C_VITAL of HA1C is for VITAL_ACT end for; end CFG_HA1C_VITAL; ----- CELL HCLKBUF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity HCLKBUF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of HCLKBUF : entity is TRUE; end HCLKBUF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of HCLKBUF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL PAD_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (PAD_ipd, PAD, tipd_PAD); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (PAD_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(PAD_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (PAD_ipd'last_event, tpd_PAD_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_HCLKBUF_VITAL of HCLKBUF is for VITAL_ACT end for; end CFG_HCLKBUF_VITAL; ----- CELL INBUF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity INBUF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of INBUF : entity is TRUE; end INBUF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of INBUF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL PAD_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (PAD_ipd, PAD, tipd_PAD); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (PAD_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(PAD_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (PAD_ipd'last_event, tpd_PAD_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_INBUF_VITAL of INBUF is for VITAL_ACT end for; end CFG_INBUF_VITAL; ----- CELL INV ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity INV is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of INV : entity is TRUE; end INV; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of INV is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_INV_VITAL of INV is for VITAL_ACT end for; end CFG_INV_VITAL; ----- CELL INVA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity INVA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of INVA : entity is TRUE; end INVA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of INVA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_INVA_VITAL of INVA is for VITAL_ACT end for; end CFG_INVA_VITAL; ----- CELL INVD ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity INVD is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of INVD : entity is TRUE; end INVD; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of INVD is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_INVD_VITAL of INVD is for VITAL_ACT end for; end CFG_INVD_VITAL; ----- CELL JKF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF : entity is TRUE; end JKF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of JKF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_J_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_posedge, TimingData => Tmkr_J_CLK_posedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_posedge, SetupLow => tsetup_J_CLK_noedge_posedge, HoldHigh => thold_J_CLK_noedge_posedge, HoldLow => thold_J_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/JKF", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_posedge, TimingData => Tmkr_K_CLK_posedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_posedge, SetupLow => tsetup_K_CLK_noedge_posedge, HoldHigh => thold_K_CLK_noedge_posedge, HoldLow => thold_K_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/JKF", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_posedge or Tviol_K_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE1B_Q_tab, DataIn => ( CLK_delayed, K_delayed, J_delayed, Q_zd, CLK_ipd)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF_VITAL of JKF is for VITAL_ACT end for; end CFG_JKF_VITAL; ----- CELL JKF1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF1B : entity is TRUE; end JKF1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of JKF1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_J_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_negedge, TimingData => Tmkr_J_CLK_negedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_negedge, SetupLow => tsetup_J_CLK_noedge_negedge, HoldHigh => thold_J_CLK_noedge_negedge, HoldLow => thold_J_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/JKF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_negedge, TimingData => Tmkr_K_CLK_negedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_negedge, SetupLow => tsetup_K_CLK_noedge_negedge, HoldHigh => thold_K_CLK_noedge_negedge, HoldLow => thold_K_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/JKF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_negedge or Tviol_K_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE1B_Q_tab, DataIn => ( CLK_ipd, K_delayed, J_delayed, Q_zd, CLK_delayed)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF1B_VITAL of JKF1B is for VITAL_ACT end for; end CFG_JKF1B_VITAL; ----- CELL JKF2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF2A : entity is TRUE; end JKF2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_J_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L ), ( U, x, x, x, L, x, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_posedge, TimingData => Tmkr_J_CLK_posedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_posedge, SetupLow => tsetup_J_CLK_noedge_posedge, HoldHigh => thold_J_CLK_noedge_posedge, HoldLow => thold_J_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_posedge, TimingData => Tmkr_K_CLK_posedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_posedge, SetupLow => tsetup_K_CLK_noedge_posedge, HoldHigh => thold_K_CLK_noedge_posedge, HoldLow => thold_K_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/JKF2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/JKF2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_posedge or Tviol_CLR_CLK_posedge or Tviol_K_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3C_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, K_delayed, J_delayed, Q_zd, CLK_ipd)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF2A_VITAL of JKF2A is for VITAL_ACT end for; end CFG_JKF2A_VITAL; ----- CELL JKF2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF2B : entity is TRUE; end JKF2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_J_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L ), ( U, x, x, x, L, x, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_negedge, TimingData => Tmkr_J_CLK_negedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_negedge, SetupLow => tsetup_J_CLK_noedge_negedge, HoldHigh => thold_J_CLK_noedge_negedge, HoldLow => thold_J_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_negedge, TimingData => Tmkr_K_CLK_negedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_negedge, SetupLow => tsetup_K_CLK_noedge_negedge, HoldHigh => thold_K_CLK_noedge_negedge, HoldLow => thold_K_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/JKF2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/JKF2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_negedge or Tviol_K_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3C_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, K_delayed, J_delayed, Q_zd, CLK_delayed)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF2B_VITAL of JKF2B is for VITAL_ACT end for; end CFG_JKF2B_VITAL; ----- CELL JKF3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF3A : entity is TRUE; end JKF3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_J_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM4A_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, H, H, x, x, H, x, H ), ( L, H, x, H, x, H, x, H ), ( L, x, L, L, H, H, x, L ), ( L, x, H, L, x, H, x, H ), ( H, x, x, x, H, x, x, S ), ( x, x, x, x, L, x, x, H ), ( x, x, x, x, H, L, x, S ), ( x, x, x, H, U, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_posedge, TimingData => Tmkr_J_CLK_posedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_posedge, SetupLow => tsetup_J_CLK_noedge_posedge, HoldHigh => thold_J_CLK_noedge_posedge, HoldLow => thold_J_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_posedge, TimingData => Tmkr_K_CLK_posedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_posedge, SetupLow => tsetup_K_CLK_noedge_posedge, HoldHigh => thold_K_CLK_noedge_posedge, HoldLow => thold_K_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/JKF3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/JKF3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_posedge or Pviol_PRE or Tviol_K_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM4A_Q_tab, DataIn => ( CLK_delayed, K_delayed, J_delayed, Q_zd, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF3A_VITAL of JKF3A is for VITAL_ACT end for; end CFG_JKF3A_VITAL; ----- CELL JKF3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF3B : entity is TRUE; end JKF3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_J_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM4A_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, H, H, x, x, H, x, H ), ( L, H, x, H, x, H, x, H ), ( L, x, L, L, H, H, x, L ), ( L, x, H, L, x, H, x, H ), ( H, x, x, x, H, x, x, S ), ( x, x, x, x, L, x, x, H ), ( x, x, x, x, H, L, x, S ), ( x, x, x, H, U, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_negedge, TimingData => Tmkr_J_CLK_negedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_negedge, SetupLow => tsetup_J_CLK_noedge_negedge, HoldHigh => thold_J_CLK_noedge_negedge, HoldLow => thold_J_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_negedge, TimingData => Tmkr_K_CLK_negedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_negedge, SetupLow => tsetup_K_CLK_noedge_negedge, HoldHigh => thold_K_CLK_noedge_negedge, HoldLow => thold_K_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/JKF3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/JKF3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_negedge or Tviol_K_CLK_negedge or Pviol_PRE or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM4A_Q_tab, DataIn => ( CLK_ipd, K_delayed, J_delayed, Q_zd, PRE_ipd, CLK_delayed)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF3B_VITAL of JKF3B is for VITAL_ACT end for; end CFG_JKF3B_VITAL; ----- CELL MAJ3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MAJ3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MAJ3 : entity is TRUE; end MAJ3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of MAJ3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((C_ipd) AND (B_ipd)) OR ((B_ipd) AND (A_ipd)) OR ((C_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MAJ3_VITAL of MAJ3 is for VITAL_ACT end for; end CFG_MAJ3_VITAL; ----- CELL MAJ3X ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MAJ3X is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MAJ3X : entity is TRUE; end MAJ3X; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of MAJ3X is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (((NOT B_ipd)) AND (A_ipd) AND (C_ipd)) OR ((B_ipd) AND (A_ipd) AND ((NOT C_ipd))) OR ((B_ipd) AND ((NOT A_ipd)) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MAJ3X_VITAL of MAJ3X is for VITAL_ACT end for; end CFG_MAJ3X_VITAL; ----- CELL MAJ3XI ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MAJ3XI is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MAJ3XI : entity is TRUE; end MAJ3XI; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of MAJ3XI is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((((NOT B_ipd)) AND (A_ipd) AND (C_ipd)) OR ((B_ipd) AND (A_ipd) AND ((NOT C_ipd))) OR ((B_ipd) AND ((NOT A_ipd)) AND (C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MAJ3XI_VITAL of MAJ3XI is for VITAL_ACT end for; end CFG_MAJ3XI_VITAL; ----- CELL MIN3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MIN3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MIN3 : entity is TRUE; end MIN3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of MIN3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (((NOT C_ipd)) AND ((NOT A_ipd))) OR (((NOT B_ipd)) AND ((NOT A_ipd))) OR (((NOT C_ipd)) AND ((NOT B_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MIN3_VITAL of MIN3 is for VITAL_ACT end for; end CFG_MIN3_VITAL; ----- CELL MIN3X ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MIN3X is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MIN3X : entity is TRUE; end MIN3X; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of MIN3X is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((B_ipd) AND ((NOT A_ipd)) AND ((NOT C_ipd))) OR (((NOT B_ipd)) AND (A_ipd) AND ((NOT C_ipd))) OR (((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MIN3X_VITAL of MIN3X is for VITAL_ACT end for; end CFG_MIN3X_VITAL; ----- CELL MIN3XI ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MIN3XI is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MIN3XI : entity is TRUE; end MIN3XI; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of MIN3XI is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((B_ipd) AND ((NOT A_ipd)) AND ((NOT C_ipd))) OR (((NOT B_ipd)) AND (A_ipd) AND ((NOT C_ipd))) OR (((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MIN3XI_VITAL of MIN3XI is for VITAL_ACT end for; end CFG_MIN3XI_VITAL; ----- CELL MX2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MX2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MX2 : entity is TRUE; end MX2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of MX2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalMUX (data => (B_ipd, A_ipd), dselect => (0 => S_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S_ipd'last_event, tpd_S_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MX2_VITAL of MX2 is for VITAL_ACT end for; end CFG_MX2_VITAL; ----- CELL MX2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MX2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MX2A : entity is TRUE; end MX2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of MX2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((S_ipd) AND (B_ipd)) OR (((NOT S_ipd)) AND ((NOT A_ipd))) OR ((B_ipd) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S_ipd'last_event, tpd_S_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MX2A_VITAL of MX2A is for VITAL_ACT end for; end CFG_MX2A_VITAL; ----- CELL MX2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MX2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MX2B : entity is TRUE; end MX2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of MX2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((S_ipd) AND ((NOT B_ipd))) OR (((NOT S_ipd)) AND (A_ipd)) OR ((A_ipd) AND ((NOT B_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S_ipd'last_event, tpd_S_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MX2B_VITAL of MX2B is for VITAL_ACT end for; end CFG_MX2B_VITAL; ----- CELL MX2C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MX2C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MX2C : entity is TRUE; end MX2C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of MX2C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalMUX (data => (B_ipd, A_ipd), dselect => (0 => S_ipd)); Y_zd := NOT Y_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S_ipd'last_event, tpd_S_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MX2C_VITAL of MX2C is for VITAL_ACT end for; end CFG_MX2C_VITAL; ----- CELL MX4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MX4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0 : in STD_ULOGIC; S1 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MX4 : entity is TRUE; end MX4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of MX4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S0_ipd : STD_ULOGIC := 'X'; SIGNAL S1_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S0_ipd, S0, tipd_S0); VitalWireDelay (S1_ipd, S1, tipd_S1); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, D3_ipd, S0_ipd, S1_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalMUX (data => (D3_ipd, D2_ipd, D1_ipd, D0_ipd), dselect => (S1_ipd, S0_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S1_ipd'last_event, tpd_S1_Y, TRUE), 1 => (S0_ipd'last_event, tpd_S0_Y, TRUE), 2 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 3 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 4 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 5 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MX4_VITAL of MX4 is for VITAL_ACT end for; end CFG_MX4_VITAL; ----- CELL NAND2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND2 : entity is TRUE; end NAND2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) AND (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND2_VITAL of NAND2 is for VITAL_ACT end for; end CFG_NAND2_VITAL; ----- CELL NAND2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND2A : entity is TRUE; end NAND2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) AND ((NOT A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND2A_VITAL of NAND2A is for VITAL_ACT end for; end CFG_NAND2A_VITAL; ----- CELL NAND2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND2B : entity is TRUE; end NAND2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND2B_VITAL of NAND2B is for VITAL_ACT end for; end CFG_NAND2B_VITAL; ----- CELL NAND3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND3 : entity is TRUE; end NAND3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) AND (A_ipd) AND (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND3_VITAL of NAND3 is for VITAL_ACT end for; end CFG_NAND3_VITAL; ----- CELL NAND3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND3A : entity is TRUE; end NAND3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) AND ((NOT A_ipd)) AND (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND3A_VITAL of NAND3A is for VITAL_ACT end for; end CFG_NAND3A_VITAL; ----- CELL NAND3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND3B : entity is TRUE; end NAND3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND3B_VITAL of NAND3B is for VITAL_ACT end for; end CFG_NAND3B_VITAL; ----- CELL NAND3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND3C : entity is TRUE; end NAND3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND3C_VITAL of NAND3C is for VITAL_ACT end for; end CFG_NAND3C_VITAL; ----- CELL NAND4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND4 : entity is TRUE; end NAND4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) AND (A_ipd) AND (C_ipd) AND (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND4_VITAL of NAND4 is for VITAL_ACT end for; end CFG_NAND4_VITAL; ----- CELL NAND4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND4A : entity is TRUE; end NAND4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) AND ((NOT A_ipd)) AND (C_ipd) AND (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND4A_VITAL of NAND4A is for VITAL_ACT end for; end CFG_NAND4A_VITAL; ----- CELL NAND4B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND4B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND4B : entity is TRUE; end NAND4B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND4B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd) AND (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND4B_VITAL of NAND4B is for VITAL_ACT end for; end CFG_NAND4B_VITAL; ----- CELL NAND4C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND4C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND4C : entity is TRUE; end NAND4C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND4C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)) AND (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND4C_VITAL of NAND4C is for VITAL_ACT end for; end CFG_NAND4C_VITAL; ----- CELL NAND4D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND4D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND4D : entity is TRUE; end NAND4D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND4D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)) AND ((NOT D_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND4D_VITAL of NAND4D is for VITAL_ACT end for; end CFG_NAND4D_VITAL; ----- CELL NAND5B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND5B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND5B : entity is TRUE; end NAND5B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND5B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd) AND (D_ipd) AND (E_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND5B_VITAL of NAND5B is for VITAL_ACT end for; end CFG_NAND5B_VITAL; ----- CELL NAND5C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND5C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND5C : entity is TRUE; end NAND5C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NAND5C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)) AND (D_ipd) AND (E_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND5C_VITAL of NAND5C is for VITAL_ACT end for; end CFG_NAND5C_VITAL; ----- CELL NOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR2 : entity is TRUE; end NOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) OR (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR2_VITAL of NOR2 is for VITAL_ACT end for; end CFG_NOR2_VITAL; ----- CELL NOR2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR2A : entity is TRUE; end NOR2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) OR ((NOT A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR2A_VITAL of NOR2A is for VITAL_ACT end for; end CFG_NOR2A_VITAL; ----- CELL NOR2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR2B : entity is TRUE; end NOR2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR2B_VITAL of NOR2B is for VITAL_ACT end for; end CFG_NOR2B_VITAL; ----- CELL NOR3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR3 : entity is TRUE; end NOR3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) OR (A_ipd) OR (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR3_VITAL of NOR3 is for VITAL_ACT end for; end CFG_NOR3_VITAL; ----- CELL NOR3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR3A : entity is TRUE; end NOR3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) OR ((NOT A_ipd)) OR (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR3A_VITAL of NOR3A is for VITAL_ACT end for; end CFG_NOR3A_VITAL; ----- CELL NOR3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR3B : entity is TRUE; end NOR3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)) OR (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR3B_VITAL of NOR3B is for VITAL_ACT end for; end CFG_NOR3B_VITAL; ----- CELL NOR3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR3C : entity is TRUE; end NOR3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)) OR ((NOT C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR3C_VITAL of NOR3C is for VITAL_ACT end for; end CFG_NOR3C_VITAL; ----- CELL NOR4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR4 : entity is TRUE; end NOR4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)) AND ((NOT D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR4_VITAL of NOR4 is for VITAL_ACT end for; end CFG_NOR4_VITAL; ----- CELL NOR4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR4A : entity is TRUE; end NOR4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) OR ((NOT A_ipd)) OR (C_ipd) OR (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR4A_VITAL of NOR4A is for VITAL_ACT end for; end CFG_NOR4A_VITAL; ----- CELL NOR4B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR4B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR4B : entity is TRUE; end NOR4B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR4B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)) OR (C_ipd) OR (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR4B_VITAL of NOR4B is for VITAL_ACT end for; end CFG_NOR4B_VITAL; ----- CELL NOR4C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR4C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR4C : entity is TRUE; end NOR4C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR4C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)) OR ((NOT C_ipd)) OR (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR4C_VITAL of NOR4C is for VITAL_ACT end for; end CFG_NOR4C_VITAL; ----- CELL NOR4D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR4D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR4D : entity is TRUE; end NOR4D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR4D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)) OR ((NOT C_ipd)) OR ((NOT D_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR4D_VITAL of NOR4D is for VITAL_ACT end for; end CFG_NOR4D_VITAL; ----- CELL NOR5B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR5B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR5B : entity is TRUE; end NOR5B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR5B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)) OR (C_ipd) OR (D_ipd) OR (E_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR5B_VITAL of NOR5B is for VITAL_ACT end for; end CFG_NOR5B_VITAL; ----- CELL NOR5C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR5C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR5C : entity is TRUE; end NOR5C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of NOR5C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)) OR ((NOT C_ipd)) OR (D_ipd) OR (E_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR5C_VITAL of NOR5C is for VITAL_ACT end for; end CFG_NOR5C_VITAL; ----- CELL OA1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA1 : entity is TRUE; end OA1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((B_ipd) OR (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA1_VITAL of OA1 is for VITAL_ACT end for; end CFG_OA1_VITAL; ----- CELL OA1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA1A : entity is TRUE; end OA1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((B_ipd) OR ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA1A_VITAL of OA1A is for VITAL_ACT end for; end CFG_OA1A_VITAL; ----- CELL OA1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA1B : entity is TRUE; end OA1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) AND ((B_ipd) OR (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA1B_VITAL of OA1B is for VITAL_ACT end for; end CFG_OA1B_VITAL; ----- CELL OA1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA1C : entity is TRUE; end OA1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) AND ((B_ipd) OR ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA1C_VITAL of OA1C is for VITAL_ACT end for; end CFG_OA1C_VITAL; ----- CELL OA2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA2 : entity is TRUE; end OA2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((D_ipd) OR (C_ipd)) AND ((B_ipd) OR (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA2_VITAL of OA2 is for VITAL_ACT end for; end CFG_OA2_VITAL; ----- CELL OA2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA2A : entity is TRUE; end OA2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((D_ipd) OR (C_ipd)) AND ((B_ipd) OR ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA2A_VITAL of OA2A is for VITAL_ACT end for; end CFG_OA2A_VITAL; ----- CELL OA3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA3 : entity is TRUE; end OA3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((B_ipd) OR (A_ipd)) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA3_VITAL of OA3 is for VITAL_ACT end for; end CFG_OA3_VITAL; ----- CELL OA3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA3A : entity is TRUE; end OA3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) AND ((B_ipd) OR (A_ipd)) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE), 3 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA3A_VITAL of OA3A is for VITAL_ACT end for; end CFG_OA3A_VITAL; ----- CELL OA3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA3B : entity is TRUE; end OA3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) AND ((B_ipd) OR ((NOT A_ipd))) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA3B_VITAL of OA3B is for VITAL_ACT end for; end CFG_OA3B_VITAL; ----- CELL OA4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA4 : entity is TRUE; end OA4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (D_ipd) AND ((B_ipd) OR (A_ipd) OR (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA4_VITAL of OA4 is for VITAL_ACT end for; end CFG_OA4_VITAL; ----- CELL OA4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA4A : entity is TRUE; end OA4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (D_ipd) AND ((B_ipd) OR (A_ipd) OR ((NOT C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE), 3 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA4A_VITAL of OA4A is for VITAL_ACT end for; end CFG_OA4A_VITAL; ----- CELL OA5 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA5 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA5 : entity is TRUE; end OA5; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OA5 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((D_ipd) OR (A_ipd)) AND ((B_ipd) OR (A_ipd) OR (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA5_VITAL of OA5 is for VITAL_ACT end for; end CFG_OA5_VITAL; ----- CELL OAI1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OAI1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OAI1 : entity is TRUE; end OAI1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OAI1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) AND ((B_ipd) OR (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OAI1_VITAL of OAI1 is for VITAL_ACT end for; end CFG_OAI1_VITAL; ----- CELL OAI2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OAI2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OAI2A : entity is TRUE; end OAI2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OAI2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT D_ipd)) AND ((B_ipd) OR (A_ipd) OR (C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OAI2A_VITAL of OAI2A is for VITAL_ACT end for; end CFG_OAI2A_VITAL; ----- CELL OAI3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OAI3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OAI3 : entity is TRUE; end OAI3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OAI3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) AND ((B_ipd) OR (A_ipd)) AND (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OAI3_VITAL of OAI3 is for VITAL_ACT end for; end CFG_OAI3_VITAL; ----- CELL OAI3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OAI3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OAI3A : entity is TRUE; end OAI3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OAI3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT C_ipd)) AND ((B_ipd) OR (A_ipd)) AND ((NOT D_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OAI3A_VITAL of OAI3A is for VITAL_ACT end for; end CFG_OAI3A_VITAL; ----- CELL OR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR2 : entity is TRUE; end OR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR2_VITAL of OR2 is for VITAL_ACT end for; end CFG_OR2_VITAL; ----- CELL OR2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR2A : entity is TRUE; end OR2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR ((NOT A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR2A_VITAL of OR2A is for VITAL_ACT end for; end CFG_OR2A_VITAL; ----- CELL OR2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR2B : entity is TRUE; end OR2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR2B_VITAL of OR2B is for VITAL_ACT end for; end CFG_OR2B_VITAL; ----- CELL OR3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR3 : entity is TRUE; end OR3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR (A_ipd) OR (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR3_VITAL of OR3 is for VITAL_ACT end for; end CFG_OR3_VITAL; ----- CELL OR3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR3A : entity is TRUE; end OR3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR ((NOT A_ipd)) OR (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR3A_VITAL of OR3A is for VITAL_ACT end for; end CFG_OR3A_VITAL; ----- CELL OR3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR3B : entity is TRUE; end OR3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)) OR (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR3B_VITAL of OR3B is for VITAL_ACT end for; end CFG_OR3B_VITAL; ----- CELL OR3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR3C : entity is TRUE; end OR3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)) OR ((NOT C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR3C_VITAL of OR3C is for VITAL_ACT end for; end CFG_OR3C_VITAL; ----- CELL OR4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR4 : entity is TRUE; end OR4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR (A_ipd) OR (C_ipd) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR4_VITAL of OR4 is for VITAL_ACT end for; end CFG_OR4_VITAL; ----- CELL OR4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR4A : entity is TRUE; end OR4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR ((NOT A_ipd)) OR (C_ipd) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR4A_VITAL of OR4A is for VITAL_ACT end for; end CFG_OR4A_VITAL; ----- CELL OR4B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR4B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR4B : entity is TRUE; end OR4B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR4B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)) OR (C_ipd) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR4B_VITAL of OR4B is for VITAL_ACT end for; end CFG_OR4B_VITAL; ----- CELL OR4C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR4C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR4C : entity is TRUE; end OR4C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR4C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)) OR ((NOT C_ipd)) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR4C_VITAL of OR4C is for VITAL_ACT end for; end CFG_OR4C_VITAL; ----- CELL OR4D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR4D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR4D : entity is TRUE; end OR4D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR4D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)) OR ((NOT C_ipd)) OR ((NOT D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR4D_VITAL of OR4D is for VITAL_ACT end for; end CFG_OR4D_VITAL; ----- CELL OR5A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR5A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR5A : entity is TRUE; end OR5A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR5A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR ((NOT A_ipd)) OR (C_ipd) OR (D_ipd) OR (E_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR5A_VITAL of OR5A is for VITAL_ACT end for; end CFG_OR5A_VITAL; ----- CELL OR5B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR5B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR5B : entity is TRUE; end OR5B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR5B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)) OR (C_ipd) OR (D_ipd) OR (E_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR5B_VITAL of OR5B is for VITAL_ACT end for; end CFG_OR5B_VITAL; ----- CELL OR5C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR5C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR5C : entity is TRUE; end OR5C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OR5C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)) OR ((NOT C_ipd)) OR (D_ipd) OR (E_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (E_ipd'last_event, tpd_E_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE), 4 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR5C_VITAL of OR5C is for VITAL_ACT end for; end CFG_OR5C_VITAL; ----- CELL OUTBUF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OUTBUF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; PAD : out STD_ULOGIC); attribute VITAL_LEVEL0 of OUTBUF : entity is TRUE; end OUTBUF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of OUTBUF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS PAD_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE PAD_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- PAD_zd := TO_X01(D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => PAD, GlitchData => PAD_GlitchData, OutSignalName => "PAD", OutTemp => PAD_zd, Paths => (0 => (D_ipd'last_event, tpd_D_PAD, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OUTBUF_VITAL of OUTBUF is for VITAL_ACT end for; end CFG_OUTBUF_VITAL; ----- CELL TF1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity TF1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_T_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_T_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_T : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( T : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of TF1A : entity is TRUE; end TF1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of TF1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL T_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (T_ipd, T, tipd_T); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (T_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_T_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_T_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE T_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_T_CLK_posedge, TimingData => Tmkr_T_CLK_posedge, TestSignal => T_ipd, TestSignalName => "T", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_T_CLK_noedge_posedge, SetupLow => tsetup_T_CLK_noedge_posedge, HoldHigh => thold_T_CLK_noedge_posedge, HoldLow => thold_T_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/TF1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/TF1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/TF1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/TF1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_T_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => TF1A_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, T_delayed, Q_zd, CLK_ipd)); Q_zd := Violation XOR Q_zd; T_delayed := T_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_TF1A_VITAL of TF1A is for VITAL_ACT end for; end CFG_TF1A_VITAL; ----- CELL TF1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity TF1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_T_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_T_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_T : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( T : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of TF1B : entity is TRUE; end TF1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of TF1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL T_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (T_ipd, T, tipd_T); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (T_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_T_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_T_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE T_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_T_CLK_negedge, TimingData => Tmkr_T_CLK_negedge, TestSignal => T_ipd, TestSignalName => "T", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_T_CLK_noedge_negedge, SetupLow => tsetup_T_CLK_noedge_negedge, HoldHigh => thold_T_CLK_noedge_negedge, HoldLow => thold_T_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/TF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/TF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/TF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/TF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_T_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => TF1A_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, T_delayed, Q_zd, CLK_delayed)); Q_zd := Violation XOR Q_zd; T_delayed := T_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_TF1B_VITAL of TF1B is for VITAL_ACT end for; end CFG_TF1B_VITAL; ----- CELL TRIBUFF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity TRIBUFF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_PAD : VitalDelayType01z := (0.000 ns, 0.000 ns, 1.000 ns, 1.000 ns, 1.000 ns, 1.000 ns); tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; PAD : out STD_ULOGIC); attribute VITAL_LEVEL0 of TRIBUFF : entity is TRUE; end TRIBUFF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of TRIBUFF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS PAD_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE PAD_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- PAD_zd := VitalBUFIF0 (data => D_ipd, enable => (NOT E_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01Z ( OutSignal => PAD, GlitchData => PAD_GlitchData, OutSignalName => "PAD", OutTemp => PAD_zd, Paths => (0 => (E_ipd'last_event, tpd_E_PAD, TRUE), 1 => (D_ipd'last_event, VitalExtendToFillDelay(tpd_D_PAD), TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING, OutputMap => "UX01ZWLH-"); end process; end VITAL_ACT; configuration CFG_TRIBUFF_VITAL of TRIBUFF is for VITAL_ACT end for; end CFG_TRIBUFF_VITAL; ----- CELL VCC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity VCC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True); port( Y : out STD_ULOGIC := '1'); attribute VITAL_LEVEL0 of VCC : entity is TRUE; end VCC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of VCC is attribute VITAL_LEVEL0 of VITAL_ACT : architecture is TRUE; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin -- empty end block; -------------------- -- BEHAVIOR SECTION -------------------- Y <= '1'; end VITAL_ACT; configuration CFG_VCC_VITAL of VCC is for VITAL_ACT end for; end CFG_VCC_VITAL; ----- CELL XA1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XA1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XA1 : entity is TRUE; end XA1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XA1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((B_ipd) XOR (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XA1_VITAL of XA1 is for VITAL_ACT end for; end CFG_XA1_VITAL; ----- CELL XA1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XA1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XA1A : entity is TRUE; end XA1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XA1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((NOT ((B_ipd) XOR (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XA1A_VITAL of XA1A is for VITAL_ACT end for; end CFG_XA1A_VITAL; ----- CELL XA1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XA1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XA1B : entity is TRUE; end XA1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XA1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) AND ((B_ipd) XOR (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XA1B_VITAL of XA1B is for VITAL_ACT end for; end CFG_XA1B_VITAL; ----- CELL XA1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XA1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XA1C : entity is TRUE; end XA1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XA1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) AND ((NOT ((B_ipd) XOR (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XA1C_VITAL of XA1C is for VITAL_ACT end for; end CFG_XA1C_VITAL; ----- CELL XAI1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XAI1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XAI1 : entity is TRUE; end XAI1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XAI1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) AND ((B_ipd) XOR (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XAI1_VITAL of XAI1 is for VITAL_ACT end for; end CFG_XAI1_VITAL; ----- CELL XAI1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XAI1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XAI1A : entity is TRUE; end XAI1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XAI1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) AND ((NOT ((B_ipd) XOR (A_ipd)))))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XAI1A_VITAL of XAI1A is for VITAL_ACT end for; end CFG_XAI1A_VITAL; ----- CELL XNOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XNOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XNOR2 : entity is TRUE; end XNOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XNOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) XOR (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XNOR2_VITAL of XNOR2 is for VITAL_ACT end for; end CFG_XNOR2_VITAL; ----- CELL XNOR3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XNOR3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XNOR3 : entity is TRUE; end XNOR3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XNOR3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) XOR (A_ipd) XOR (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XNOR3_VITAL of XNOR3 is for VITAL_ACT end for; end CFG_XNOR3_VITAL; ----- CELL XO1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XO1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XO1 : entity is TRUE; end XO1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XO1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((B_ipd) XOR (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XO1_VITAL of XO1 is for VITAL_ACT end for; end CFG_XO1_VITAL; ----- CELL XO1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XO1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XO1A : entity is TRUE; end XO1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XO1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((NOT ((B_ipd) XOR (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XO1A_VITAL of XO1A is for VITAL_ACT end for; end CFG_XO1A_VITAL; ----- CELL XOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XOR2 : entity is TRUE; end XOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) XOR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XOR2_VITAL of XOR2 is for VITAL_ACT end for; end CFG_XOR2_VITAL; ----- CELL XOR3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XOR3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XOR3 : entity is TRUE; end XOR3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of XOR3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) XOR (A_ipd) XOR (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XOR3_VITAL of XOR3 is for VITAL_ACT end for; end CFG_XOR3_VITAL; ----- CELL ZOR3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity ZOR3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of ZOR3 : entity is TRUE; end ZOR3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of ZOR3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd))) OR ((B_ipd) AND (A_ipd) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_ZOR3_VITAL of ZOR3 is for VITAL_ACT end for; end CFG_ZOR3_VITAL; ----- CELL ZOR3I ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity ZOR3I is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of ZOR3I : entity is TRUE; end ZOR3I; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a54sx; use a54sx.VTABLES.all; architecture VITAL_ACT of ZOR3I is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd))) OR ((B_ipd) AND (A_ipd) AND (C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_ZOR3I_VITAL of ZOR3I is for VITAL_ACT end for; end CFG_ZOR3I_VITAL; ---- end of library ----