-- "$Header: 40mx.vhd@@/main/4 $" -- Actel Vital 95 library library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; package COMPONENTS is constant DefaultTimingChecksOn : Boolean := True; constant DefaultXGenerationOn : Boolean := False; constant DefaultXon : Boolean := False; constant DefaultMsgOn : Boolean := True; component AND2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND4B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND4C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AND4D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AO5A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AOI4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AX1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AX1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AX1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component BIBUF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_PAD : VitalDelayType01z := (0.000 ns, 0.000 ns, 1.000 ns, 1.000 ns, 1.000 ns, 1.000 ns); tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; PAD : inout STD_ULOGIC; Y : out STD_ULOGIC); end component; component BUFA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component BUFD generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component BUFF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CLKBIBUF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_PAD : VitalDelayType01z := (0.000 ns, 0.000 ns, 1.000 ns, 1.000 ns, 1.000 ns, 1.000 ns); tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; PAD : inout STD_ULOGIC; Y : out STD_ULOGIC); end component; component CLKBUF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component CM8A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_SB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_SA_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_SA : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_SB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; SA : in STD_ULOGIC; B0 : in STD_ULOGIC; B1 : in STD_ULOGIC; SB : in STD_ULOGIC; S0 : in STD_ULOGIC; S1 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component DF1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DF1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DF1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DF1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFC1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFC1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFC1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFC1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFC1D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFC1E generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFC1F generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFC1G generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFE generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE2D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE3D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE4B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFE4C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFEA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFEB generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFEC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFED generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFM generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFM1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFM1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFM3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFM3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFM3E generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFM3F generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFM3G generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFM4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFM4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFM4B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFM4C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFM4D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFM4E generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFM5A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFM5B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFMA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFMB generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFME1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFP1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFP1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFP1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFP1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFP1D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFP1E generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFP1F generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFP1G generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DFPC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DFPCA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DL1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DL1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DL1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DL1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DL2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DL2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DL2C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DL2D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DLC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLC1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLC1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLC1F generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DLC1G generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DLCA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLE generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_E_posedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLE1D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DLE2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_E_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_E_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLE2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_E_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLE2C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_E_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLE3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_E_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_E_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLE3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_E_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLE3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_E_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLEA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLEB generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_E_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_negedge : VitalDelayType := 0.000 ns; thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLEC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLM generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_G_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLM2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLMA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_G_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLME1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_A_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_E_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLP1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLP1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLP1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLP1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component DLP1D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component DLP1E generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); end component; component FA1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); end component; component FA1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); end component; component FA1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); end component; component FA2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); end component; component GAND2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component GMX4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0 : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component GNAND2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component GND generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True); port( Y : out STD_ULOGIC := '0'); end component; component GNOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component GOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component GXOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component HA1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); end component; component HA1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); end component; component HA1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); end component; component HA1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); end component; component INBUF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component INV generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component INVA generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component INVD generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component JKF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF2C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF2D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF3D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKF4B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component JKFPC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); end component; component MAJ3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MX2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MX2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MX2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MX2C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MX4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0 : in STD_ULOGIC; S1 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MXC1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component MXT generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0A : in STD_ULOGIC; S0B : in STD_ULOGIC; S1 : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND4B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND4C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NAND4D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR4B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR4C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component NOR4D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA1B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA1C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OA5 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OAI1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OAI2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OAI3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OAI3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR2A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR2B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR3 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR3A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR3B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR3C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR4 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR4A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR4B generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR4C generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OR4D generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component OUTBUF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; PAD : out STD_ULOGIC); end component; component TRIBUFF generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_PAD : VitalDelayType01z := (0.000 ns, 0.000 ns, 1.000 ns, 1.000 ns, 1.000 ns, 1.000 ns); tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; PAD : out STD_ULOGIC); end component; component VCC generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True); port( Y : out STD_ULOGIC := '1'); end component; component XA1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XA1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XNOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XO1 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XO1A generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component XOR2 generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); end component; end COMPONENTS; ---------------------------------------------------------------- -- -- ---------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; use IEEE.VITAL_Primitives.all; package VTABLES is CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DF1_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( L, H, H, x, H ), ( H, x, x, x, S ), ( x, x, L, x, S )); CONSTANT DF1A_QN_tab : VitalStateTableType := ( ( L, L, H, x, H ), ( L, H, H, x, L ), ( H, x, x, x, S ), ( x, x, L, x, S )); CONSTANT DFC1_Q_tab : VitalStateTableType := ( ( L, L, H, x, x, L ), ( L, H, H, L, x, H ), ( H, x, x, L, x, S ), ( x, x, L, L, x, S ), ( x, x, x, H, x, L )); CONSTANT DFC1B_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, H, H, x, H ), ( H, H, x, x, x, S ), ( H, x, x, L, x, S ), ( x, L, L, H, x, L )); CONSTANT DFC1C_QN_tab : VitalStateTableType := ( ( L, L, H, H, x, L ), ( L, x, L, H, x, H ), ( H, L, x, x, x, S ), ( x, L, x, L, x, S ), ( x, H, x, x, x, H )); CONSTANT DFC1E_QN_tab : VitalStateTableType := ( ( L, H, H, H, x, L ), ( L, x, L, H, x, H ), ( H, H, x, x, x, S ), ( x, L, x, x, x, H ), ( x, H, x, L, x, S )); CONSTANT DFE_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, L ), ( L, L, x, L, H, x, L ), ( L, H, H, x, H, x, H ), ( L, H, x, L, H, x, H ), ( L, x, L, H, H, x, L ), ( L, x, H, H, H, x, H ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); CONSTANT DFE1B_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, L ), ( L, L, x, H, H, x, L ), ( L, H, H, x, H, x, H ), ( L, H, x, H, H, x, H ), ( L, x, L, L, H, x, L ), ( L, x, H, L, H, x, H ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); CONSTANT DFE2D_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, x, L ), ( H, L, x, H, H, x, H, x, H ), ( H, L, x, H, x, H, H, x, H ), ( H, L, x, x, H, L, H, x, H ), ( H, H, L, x, x, x, x, x, S ), ( H, x, L, x, x, x, L, x, S ), ( H, x, H, x, x, x, x, x, H ), ( x, L, L, L, L, x, H, x, L ), ( x, L, L, L, x, H, H, x, L ), ( x, L, L, x, L, L, H, x, L )); CONSTANT DFE3A_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, L, H, x, H ), ( H, L, x, H, H, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, L, H, x, L ), ( x, L, x, L, H, H, x, L )); CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L )); CONSTANT DFE4_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, H, x, L ), ( L, L, L, x, L, H, x, L ), ( L, L, x, L, H, H, x, L ), ( L, x, H, H, x, H, x, H ), ( L, x, H, x, L, H, x, H ), ( L, x, x, H, H, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H )); CONSTANT DFE4B_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, H, x, L ), ( L, L, L, x, H, H, x, L ), ( L, L, x, L, L, H, x, L ), ( L, x, H, H, x, H, x, H ), ( L, x, H, x, H, H, x, H ), ( L, x, x, H, L, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H )); CONSTANT DFEB_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, x, L ), ( H, L, x, H, H, x, H, x, H ), ( H, L, x, H, x, L, H, x, H ), ( H, L, x, x, H, H, H, x, H ), ( H, H, L, x, x, x, x, x, S ), ( H, x, L, x, x, x, L, x, S ), ( H, x, H, x, x, x, x, x, H ), ( x, L, L, L, L, x, H, x, L ), ( x, L, L, L, x, L, H, x, L ), ( x, L, L, x, L, H, H, x, L )); CONSTANT DFM1B_QN_tab : VitalStateTableType := ( ( L, L, x, L, H, x, H ), ( L, L, x, H, H, x, L ), ( L, H, L, x, H, x, H ), ( L, H, H, x, H, x, L ), ( L, x, L, L, H, x, H ), ( L, x, H, H, H, x, L ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); CONSTANT DFM3_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, x, L ), ( L, L, x, H, H, x, x, L ), ( L, H, H, x, H, L, x, H ), ( L, H, x, H, H, L, x, H ), ( L, x, L, L, H, x, x, L ), ( L, x, H, L, H, L, x, H ), ( H, x, x, x, x, L, x, S ), ( x, x, x, x, L, L, x, S ), ( x, x, x, x, x, H, x, L )); CONSTANT DFM3F_QN_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, H, H, x, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, x, L, x, L, H, x, H ), ( L, x, H, L, x, H, x, H ), ( L, x, x, L, L, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H )); CONSTANT DFM4A_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, H, H, x, x, H, x, H ), ( L, H, x, H, x, H, x, H ), ( L, x, L, L, H, H, x, L ), ( L, x, H, L, x, H, x, H ), ( H, x, x, x, H, x, x, S ), ( x, x, x, x, L, x, x, H ), ( x, x, x, x, H, L, x, S )); CONSTANT DFM4C_QN_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, L, x, L, H, x, H ), ( H, L, H, L, x, H, x, H ), ( H, L, x, L, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, x, H, H, x, L ), ( x, L, H, H, x, H, x, L ), ( x, L, x, H, H, H, x, L )); CONSTANT DFME1A_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, x, H, x, L ), ( L, L, L, x, H, x, H, x, L ), ( L, L, x, L, L, x, H, x, L ), ( L, L, x, x, x, H, H, x, L ), ( L, H, H, H, x, x, H, x, H ), ( L, H, H, x, H, x, H, x, H ), ( L, H, x, H, L, x, H, x, H ), ( L, H, x, x, x, H, H, x, H ), ( L, x, L, L, x, L, H, x, L ), ( L, x, L, x, H, L, H, x, L ), ( L, x, H, H, x, L, H, x, H ), ( L, x, H, x, H, L, H, x, H ), ( L, x, x, L, L, L, H, x, L ), ( L, x, x, H, L, L, H, x, H ), ( H, x, x, x, x, x, x, x, S ), ( x, x, x, x, x, x, L, x, S )); CONSTANT DFP1_Q_tab : VitalStateTableType := ( ( L, L, L, H, x, L ), ( L, H, x, H, x, H ), ( H, x, L, x, x, S ), ( x, x, L, L, x, S ), ( x, x, H, x, x, H )); CONSTANT DFP1B_Q_tab : VitalStateTableType := ( ( L, L, H, H, x, L ), ( L, H, x, H, x, H ), ( H, x, H, x, x, S ), ( x, x, L, x, x, H ), ( x, x, H, L, x, S )); CONSTANT DFP1C_QN_tab : VitalStateTableType := ( ( L, L, H, L, x, H ), ( L, H, H, x, x, L ), ( H, x, x, L, x, S ), ( x, x, L, L, x, S ), ( x, x, x, H, x, L )); CONSTANT DFP1E_QN_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, L, H, x, H ), ( H, H, x, x, x, S ), ( H, x, x, L, x, S ), ( x, L, H, H, x, L )); CONSTANT DFPC_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, L ), ( H, L, H, x, H, x, H ), ( H, H, x, L, x, x, S ), ( H, x, x, L, L, x, S ), ( H, x, x, H, x, x, H ), ( x, L, L, L, H, x, L )); CONSTANT DL1_Q_tab : VitalStateTableType := ( ( L, H, x, L ), ( H, H, x, H ), ( x, L, x, S )); CONSTANT DL1A_QN_tab : VitalStateTableType := ( ( L, H, x, H ), ( H, H, x, L ), ( x, L, x, S )); CONSTANT DL1B_Q_tab : VitalStateTableType := ( ( L, L, x, L ), ( L, H, x, H ), ( H, x, x, S )); CONSTANT DL1C_QN_tab : VitalStateTableType := ( ( L, L, x, H ), ( L, H, x, L ), ( H, x, x, S )); CONSTANT DL2A_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, H, x, H, x, H ), ( H, x, L, L, x, S ), ( H, x, H, x, x, H ), ( x, L, L, H, x, L )); CONSTANT DL2B_QN_tab : VitalStateTableType := ( ( L, L, x, x, x, L ), ( L, H, H, x, x, S ), ( L, x, L, H, x, L ), ( H, x, x, x, x, H ), ( x, H, L, L, x, H )); CONSTANT DL2C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, H, x, x, H ), ( H, H, x, L, x, S ), ( H, x, x, H, x, H ), ( x, L, L, L, x, L )); CONSTANT DL2D_QN_tab : VitalStateTableType := ( ( L, L, x, x, x, L ), ( L, H, x, L, x, S ), ( L, x, H, H, x, L ), ( H, x, x, x, x, H ), ( x, H, L, H, x, H )); CONSTANT DLC_Q_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, H, H, x, H ), ( H, x, L, x, S ), ( x, L, H, x, L )); CONSTANT DLC1_Q_tab : VitalStateTableType := ( ( L, H, x, x, L ), ( H, H, L, x, H ), ( x, L, L, x, S ), ( x, x, H, x, L )); CONSTANT DLC1A_Q_tab : VitalStateTableType := ( ( L, L, x, x, L ), ( L, H, L, x, H ), ( H, x, L, x, S ), ( x, x, H, x, L )); CONSTANT DLC1F_QN_tab : VitalStateTableType := ( ( L, H, H, x, L ), ( L, x, L, x, S ), ( H, x, x, x, H ), ( x, L, H, x, H )); CONSTANT DLC1G_QN_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( L, x, L, x, H ), ( H, L, x, x, S ), ( x, H, x, x, H )); CONSTANT DLCA_Q_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, L, H, x, H ), ( H, H, x, x, S ), ( x, L, L, x, L )); CONSTANT DLE_Q_tab : VitalStateTableType := ( ( L, H, H, x, L ), ( H, H, H, x, H ), ( x, L, x, x, S ), ( x, x, L, x, S )); CONSTANT DLE1D_QN_tab : VitalStateTableType := ( ( L, L, L, x, H ), ( L, L, H, x, L ), ( H, x, x, x, S ), ( x, H, x, x, S )); CONSTANT DLE2B_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, L, H, x, H ), ( H, H, x, x, x, S ), ( H, x, H, x, x, S ), ( x, L, L, L, x, L )); CONSTANT DLE2C_Q_tab : VitalStateTableType := ( ( L, L, L, x, x, L ), ( L, L, H, L, x, H ), ( H, x, x, L, x, S ), ( x, H, x, L, x, S ), ( x, x, x, H, x, L )); CONSTANT DLE3B_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, L ), ( L, L, H, x, x, H ), ( H, x, x, L, x, S ), ( x, H, x, L, x, S ), ( x, x, x, H, x, H )); CONSTANT DLE3C_Q_tab : VitalStateTableType := ( ( L, L, L, H, x, L ), ( L, L, H, x, x, H ), ( H, x, x, H, x, S ), ( x, H, x, H, x, S ), ( x, x, x, L, x, H )); CONSTANT DLEC_Q_tab : VitalStateTableType := ( ( L, L, L, x, L ), ( L, L, H, x, H ), ( H, x, x, x, S ), ( x, H, x, x, S )); CONSTANT DLM_Q_tab : VitalStateTableType := ( ( L, L, x, H, x, L ), ( L, x, H, H, x, L ), ( H, H, x, H, x, H ), ( H, x, H, H, x, H ), ( x, L, L, H, x, L ), ( x, H, L, H, x, H ), ( x, x, x, L, x, S )); CONSTANT DLM2A_Q_tab : VitalStateTableType := ( ( L, L, L, x, x, x, L ), ( L, L, x, H, x, x, L ), ( L, H, H, x, L, x, H ), ( L, H, x, H, L, x, H ), ( L, x, L, L, x, x, L ), ( L, x, H, L, L, x, H ), ( H, x, x, x, L, x, S ), ( x, x, x, x, H, x, L )); CONSTANT DLMA_Q_tab : VitalStateTableType := ( ( L, L, L, x, x, L ), ( L, L, x, H, x, L ), ( L, H, H, x, x, H ), ( L, H, x, H, x, H ), ( L, x, L, L, x, L ), ( L, x, H, L, x, H ), ( H, x, x, x, x, S )); CONSTANT DLME1A_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, x, L ), ( L, L, L, x, H, x, L ), ( L, L, H, H, x, x, H ), ( L, L, H, x, H, x, H ), ( L, L, x, L, L, x, L ), ( L, L, x, H, L, x, H ), ( H, x, x, x, x, x, S ), ( x, H, x, x, x, x, S )); CONSTANT DLP1_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( H, x, H, x, H ), ( x, L, L, x, S ), ( x, H, x, x, H )); CONSTANT DLP1A_Q_tab : VitalStateTableType := ( ( L, L, L, x, L ), ( L, H, x, x, H ), ( H, x, L, x, S ), ( x, x, H, x, H )); CONSTANT DLP1B_Q_tab : VitalStateTableType := ( ( L, H, H, x, L ), ( H, x, H, x, H ), ( x, L, x, x, H ), ( x, H, L, x, S )); CONSTANT DLP1C_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( L, H, x, x, H ), ( H, x, H, x, S ), ( x, x, L, x, H )); CONSTANT DLP1D_QN_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, L, H, x, H ), ( H, x, L, x, S ), ( x, H, H, x, L )); CONSTANT DLP1E_QN_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, L, L, x, H ), ( H, H, x, x, S ), ( x, L, H, x, L )); end VTABLES; ---- end of VITAL tables library ---- ----- CELL AND2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND2 : entity is TRUE; end AND2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND2_VITAL of AND2 is for VITAL_ACT end for; end CFG_AND2_VITAL; ----- CELL AND2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND2A : entity is TRUE; end AND2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND ((NOT A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND2A_VITAL of AND2A is for VITAL_ACT end for; end CFG_AND2A_VITAL; ----- CELL AND2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND2B : entity is TRUE; end AND2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND2B_VITAL of AND2B is for VITAL_ACT end for; end CFG_AND2B_VITAL; ----- CELL AND3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND3 : entity is TRUE; end AND3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND (A_ipd) AND (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND3_VITAL of AND3 is for VITAL_ACT end for; end CFG_AND3_VITAL; ----- CELL AND3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND3A : entity is TRUE; end AND3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND ((NOT A_ipd)) AND (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND3A_VITAL of AND3A is for VITAL_ACT end for; end CFG_AND3A_VITAL; ----- CELL AND3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND3B : entity is TRUE; end AND3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND3B_VITAL of AND3B is for VITAL_ACT end for; end CFG_AND3B_VITAL; ----- CELL AND3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND3C : entity is TRUE; end AND3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND3C_VITAL of AND3C is for VITAL_ACT end for; end CFG_AND3C_VITAL; ----- CELL AND4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND4 : entity is TRUE; end AND4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND (A_ipd) AND (C_ipd) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND4_VITAL of AND4 is for VITAL_ACT end for; end CFG_AND4_VITAL; ----- CELL AND4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND4A : entity is TRUE; end AND4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) AND ((NOT A_ipd)) AND (C_ipd) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND4A_VITAL of AND4A is for VITAL_ACT end for; end CFG_AND4A_VITAL; ----- CELL AND4B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND4B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND4B : entity is TRUE; end AND4B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND4B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (D_ipd'last_event, tpd_D_Y, TRUE), 3 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND4B_VITAL of AND4B is for VITAL_ACT end for; end CFG_AND4B_VITAL; ----- CELL AND4C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND4C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND4C : entity is TRUE; end AND4C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND4C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE), 3 => (D_ipd'last_event, tpd_D_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND4C_VITAL of AND4C is for VITAL_ACT end for; end CFG_AND4C_VITAL; ----- CELL AND4D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AND4D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AND4D : entity is TRUE; end AND4D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AND4D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)) AND ((NOT D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AND4D_VITAL of AND4D is for VITAL_ACT end for; end CFG_AND4D_VITAL; ----- CELL AO1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO1 : entity is TRUE; end AO1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AO1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((B_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO1_VITAL of AO1 is for VITAL_ACT end for; end CFG_AO1_VITAL; ----- CELL AO1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO1A : entity is TRUE; end AO1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AO1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((B_ipd) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO1A_VITAL of AO1A is for VITAL_ACT end for; end CFG_AO1A_VITAL; ----- CELL AO1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO1B : entity is TRUE; end AO1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AO1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR ((B_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO1B_VITAL of AO1B is for VITAL_ACT end for; end CFG_AO1B_VITAL; ----- CELL AO1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO1C : entity is TRUE; end AO1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AO1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR ((B_ipd) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO1C_VITAL of AO1C is for VITAL_ACT end for; end CFG_AO1C_VITAL; ----- CELL AO2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO2 : entity is TRUE; end AO2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AO2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((B_ipd) AND (A_ipd)) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO2_VITAL of AO2 is for VITAL_ACT end for; end CFG_AO2_VITAL; ----- CELL AO2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO2A : entity is TRUE; end AO2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AO2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((B_ipd) AND ((NOT A_ipd))) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO2A_VITAL of AO2A is for VITAL_ACT end for; end CFG_AO2A_VITAL; ----- CELL AO3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO3 : entity is TRUE; end AO3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AO3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (D_ipd) OR ((B_ipd) AND ((NOT A_ipd)) AND (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO3_VITAL of AO3 is for VITAL_ACT end for; end CFG_AO3_VITAL; ----- CELL AO4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO4A : entity is TRUE; end AO4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of AO4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((C_ipd) AND (A_ipd) AND (D_ipd)) OR ((B_ipd) AND ((NOT A_ipd)) AND (C_ipd)) OR ((C_ipd) AND (B_ipd) AND (D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO4A_VITAL of AO4A is for VITAL_ACT end for; end CFG_AO4A_VITAL; ----- CELL AO5A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AO5A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AO5A : entity is TRUE; end AO5A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of AO5A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((C_ipd) AND (A_ipd)) OR ((B_ipd) AND ((NOT A_ipd))) OR ((C_ipd) AND (B_ipd)) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AO5A_VITAL of AO5A is for VITAL_ACT end for; end CFG_AO5A_VITAL; ----- CELL AOI1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI1 : entity is TRUE; end AOI1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AOI1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) OR ((B_ipd) AND (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI1_VITAL of AOI1 is for VITAL_ACT end for; end CFG_AOI1_VITAL; ----- CELL AOI1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI1A : entity is TRUE; end AOI1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AOI1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) OR ((B_ipd) AND ((NOT A_ipd))))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI1A_VITAL of AOI1A is for VITAL_ACT end for; end CFG_AOI1A_VITAL; ----- CELL AOI1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI1B : entity is TRUE; end AOI1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AOI1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT C_ipd)) OR ((B_ipd) AND (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI1B_VITAL of AOI1B is for VITAL_ACT end for; end CFG_AOI1B_VITAL; ----- CELL AOI2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI2A : entity is TRUE; end AOI2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AOI2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) OR ((B_ipd) AND ((NOT A_ipd))) OR (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI2A_VITAL of AOI2A is for VITAL_ACT end for; end CFG_AOI2A_VITAL; ----- CELL AOI2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI2B : entity is TRUE; end AOI2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AOI2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT C_ipd)) OR ((B_ipd) AND ((NOT A_ipd))) OR (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI2B_VITAL of AOI2B is for VITAL_ACT end for; end CFG_AOI2B_VITAL; ----- CELL AOI3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI3A : entity is TRUE; end AOI3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AOI3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((D_ipd) OR (A_ipd)) AND ((B_ipd) OR (A_ipd) OR (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI3A_VITAL of AOI3A is for VITAL_ACT end for; end CFG_AOI3A_VITAL; ----- CELL AOI4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AOI4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AOI4 : entity is TRUE; end AOI4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AOI4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((D_ipd) AND (C_ipd)) OR ((B_ipd) AND (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AOI4_VITAL of AOI4 is for VITAL_ACT end for; end CFG_AOI4_VITAL; ----- CELL AX1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AX1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AX1 : entity is TRUE; end AX1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AX1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) XOR ((B_ipd) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AX1_VITAL of AX1 is for VITAL_ACT end for; end CFG_AX1_VITAL; ----- CELL AX1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AX1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AX1A : entity is TRUE; end AX1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AX1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) XOR ((B_ipd) AND ((NOT A_ipd))))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AX1A_VITAL of AX1A is for VITAL_ACT end for; end CFG_AX1A_VITAL; ----- CELL AX1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity AX1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of AX1B : entity is TRUE; end AX1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of AX1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) XOR (((NOT B_ipd)) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_AX1B_VITAL of AX1B is for VITAL_ACT end for; end CFG_AX1B_VITAL; ----- CELL BIBUF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity BIBUF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_PAD : VitalDelayType01z := (0.000 ns, 0.000 ns, 1.000 ns, 1.000 ns, 1.000 ns, 1.000 ns); tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; PAD : inout STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of BIBUF : entity is TRUE; end BIBUF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of BIBUF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL PAD_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (PAD_ipd, PAD, tipd_PAD); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, PAD_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS PAD_zd : STD_LOGIC is Results(1); ALIAS Y_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE PAD_GlitchData : VitalGlitchDataType; VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- PAD_zd := VitalBUFIF0 (data => D_ipd, enable => (NOT E_ipd)); Y_zd := TO_X01(PAD_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01Z ( OutSignal => PAD, GlitchData => PAD_GlitchData, OutSignalName => "PAD", OutTemp => PAD_zd, Paths => (0 => (E_ipd'last_event, tpd_E_PAD, TRUE), 1 => (D_ipd'last_event, VitalExtendToFillDelay(tpd_D_PAD), TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING, OutputMap => "UX01ZWLH-"); VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (PAD_ipd'last_event, tpd_PAD_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_BIBUF_VITAL of BIBUF is for VITAL_ACT end for; end CFG_BIBUF_VITAL; ----- CELL BUFA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity BUFA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of BUFA : entity is TRUE; end BUFA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of BUFA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_BUFA_VITAL of BUFA is for VITAL_ACT end for; end CFG_BUFA_VITAL; ----- CELL BUFD ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity BUFD is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of BUFD : entity is TRUE; end BUFD; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of BUFD is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_BUFD_VITAL of BUFD is for VITAL_ACT end for; end CFG_BUFD_VITAL; ----- CELL BUFF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity BUFF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of BUFF : entity is TRUE; end BUFF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of BUFF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_BUFF_VITAL of BUFF is for VITAL_ACT end for; end CFG_BUFF_VITAL; ----- CELL CLKBIBUF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CLKBIBUF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_PAD : VitalDelayType01z := (0.000 ns, 0.000 ns, 1.000 ns, 1.000 ns, 1.000 ns, 1.000 ns); tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; PAD : inout STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CLKBIBUF : entity is TRUE; end CLKBIBUF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of CLKBIBUF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL PAD_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (PAD_ipd, PAD, tipd_PAD); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, PAD_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS PAD_zd : STD_LOGIC is Results(1); ALIAS Y_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE PAD_GlitchData : VitalGlitchDataType; VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- PAD_zd := VitalBUFIF0 (data => D_ipd, enable => (NOT E_ipd)); Y_zd := TO_X01(PAD_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01Z ( OutSignal => PAD, GlitchData => PAD_GlitchData, OutSignalName => "PAD", OutTemp => PAD_zd, Paths => (0 => (E_ipd'last_event, tpd_E_PAD, TRUE), 1 => (D_ipd'last_event, VitalExtendToFillDelay(tpd_D_PAD), TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING, OutputMap => "UX01ZWLH-"); VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (PAD_ipd'last_event, tpd_PAD_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CLKBIBUF_VITAL of CLKBIBUF is for VITAL_ACT end for; end CFG_CLKBIBUF_VITAL; ----- CELL CLKBUF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CLKBUF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CLKBUF : entity is TRUE; end CLKBUF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of CLKBUF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL PAD_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (PAD_ipd, PAD, tipd_PAD); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (PAD_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(PAD_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (PAD_ipd'last_event, tpd_PAD_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CLKBUF_VITAL of CLKBUF is for VITAL_ACT end for; end CFG_CLKBUF_VITAL; ----- CELL CM8A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity CM8A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_SB_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_SA_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_SA : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_SB : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; SA : in STD_ULOGIC; B0 : in STD_ULOGIC; B1 : in STD_ULOGIC; SB : in STD_ULOGIC; S0 : in STD_ULOGIC; S1 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of CM8A : entity is TRUE; end CM8A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of CM8A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A0_ipd : STD_ULOGIC := 'X'; SIGNAL A1_ipd : STD_ULOGIC := 'X'; SIGNAL SA_ipd : STD_ULOGIC := 'X'; SIGNAL B0_ipd : STD_ULOGIC := 'X'; SIGNAL B1_ipd : STD_ULOGIC := 'X'; SIGNAL SB_ipd : STD_ULOGIC := 'X'; SIGNAL S0_ipd : STD_ULOGIC := 'X'; SIGNAL S1_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A0_ipd, A0, tipd_A0); VitalWireDelay (A1_ipd, A1, tipd_A1); VitalWireDelay (SA_ipd, SA, tipd_SA); VitalWireDelay (B0_ipd, B0, tipd_B0); VitalWireDelay (B1_ipd, B1, tipd_B1); VitalWireDelay (SB_ipd, SB, tipd_SB); VitalWireDelay (S0_ipd, S0, tipd_S0); VitalWireDelay (S1_ipd, S1, tipd_S1); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A0_ipd, A1_ipd, SA_ipd, B0_ipd, B1_ipd, SB_ipd, S0_ipd, S1_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE OR_Out, MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- (((S1_ipd) OR (S0_ipd)) AND (((SB_ipd) AND (B1_ipd)) OR (((NOT -- SB_ipd)) AND (B0_ipd)))) OR (((NOT ((S1_ipd) OR (S0_ipd)))) AND -- (((SA_ipd) AND (A1_ipd)) OR (((NOT SA_ipd)) AND (A0_ipd)))); OR_Out := VitalOR2(S0_ipd, S1_ipd); MUX1_Out := VitalMUX2(A1_ipd, A0_ipd, SA_ipd); MUX2_Out := VitalMUX2(B1_ipd, B0_ipd, SB_ipd); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, OR_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S1_ipd'last_event, tpd_S1_Y, TRUE), 1 => (S0_ipd'last_event, tpd_S0_Y, TRUE), 2 => (SB_ipd'last_event, tpd_SB_Y, TRUE), 3 => (SA_ipd'last_event, tpd_SA_Y, TRUE), 4 => (B1_ipd'last_event, tpd_B1_Y, TRUE), 5 => (B0_ipd'last_event, tpd_B0_Y, TRUE), 6 => (A1_ipd'last_event, tpd_A1_Y, TRUE), 7 => (A0_ipd'last_event, tpd_A0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_CM8A_VITAL of CM8A is for VITAL_ACT end for; end CFG_CM8A_VITAL; ----- CELL DF1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DF1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DF1 : entity is TRUE; end DF1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of DF1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DF1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DF1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DF1_Q_tab, DataIn => ( CLK_delayed, D_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DF1_VITAL of DF1 is for VITAL_ACT end for; end CFG_DF1_VITAL; ----- CELL DF1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DF1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DF1A : entity is TRUE; end DF1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of DF1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 2); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DF1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DF1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DF1A_QN_tab, DataIn => ( CLK_delayed, D_delayed, CLK_ipd)); QN_zd := Violation XOR QN_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DF1A_VITAL of DF1A is for VITAL_ACT end for; end CFG_DF1A_VITAL; ----- CELL DF1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DF1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DF1B : entity is TRUE; end DF1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of DF1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DF1_Q_tab, DataIn => ( CLK_ipd, D_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DF1B_VITAL of DF1B is for VITAL_ACT end for; end CFG_DF1B_VITAL; ----- CELL DF1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DF1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DF1C : entity is TRUE; end DF1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of DF1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 2); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DF1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DF1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DF1A_QN_tab, DataIn => ( CLK_ipd, D_delayed, CLK_delayed)); QN_zd := Violation XOR QN_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DF1C_VITAL of DF1C is for VITAL_ACT end for; end CFG_DF1C_VITAL; ----- CELL DFC1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFC1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFC1 : entity is TRUE; end DFC1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFC1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1_Q_tab : VitalStateTableType := ( ( L, L, H, x, x, L ), ( L, H, H, L, x, H ), ( H, x, x, L, x, S ), ( x, x, L, L, x, S ), ( x, x, x, H, x, L ), ( x, x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_negedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DFC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFC1_Q_tab, DataIn => ( CLK_delayed, D_delayed, CLK_ipd, CLR_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFC1_VITAL of DFC1 is for VITAL_ACT end for; end CFG_DFC1_VITAL; ----- CELL DFC1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFC1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFC1A : entity is TRUE; end DFC1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFC1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1_Q_tab : VitalStateTableType := ( ( L, L, H, x, x, L ), ( L, H, H, L, x, H ), ( H, x, x, L, x, S ), ( x, x, L, L, x, S ), ( x, x, x, H, x, L ), ( x, x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_negedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DFC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFC1_Q_tab, DataIn => ( CLK_ipd, D_delayed, CLK_delayed, CLR_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFC1A_VITAL of DFC1A is for VITAL_ACT end for; end CFG_DFC1A_VITAL; ----- CELL DFC1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFC1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFC1B : entity is TRUE; end DFC1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFC1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1B_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, H, H, x, H ), ( H, H, x, x, x, S ), ( H, x, x, L, x, S ), ( x, L, L, H, x, L ), ( U, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFC1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFC1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFC1B_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, D_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFC1B_VITAL of DFC1B is for VITAL_ACT end for; end CFG_DFC1B_VITAL; ----- CELL DFC1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFC1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFC1C : entity is TRUE; end DFC1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFC1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1C_QN_tab : VitalStateTableType := ( ( L, L, H, H, x, L ), ( L, x, L, H, x, H ), ( H, L, x, x, x, S ), ( x, L, x, L, x, S ), ( x, H, x, x, x, H ), ( x, U, x, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_negedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DFC1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFC1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFC1C_QN_tab, DataIn => ( CLK_delayed, CLR_ipd, D_delayed, CLK_ipd)); QN_zd := Violation XOR QN_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFC1C_VITAL of DFC1C is for VITAL_ACT end for; end CFG_DFC1C_VITAL; ----- CELL DFC1D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFC1D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFC1D : entity is TRUE; end DFC1D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFC1D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1B_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, H, H, x, H ), ( H, H, x, x, x, S ), ( H, x, x, L, x, S ), ( x, L, L, H, x, L ), ( U, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFC1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFC1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFC1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFC1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFC1B_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, D_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFC1D_VITAL of DFC1D is for VITAL_ACT end for; end CFG_DFC1D_VITAL; ----- CELL DFC1E ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFC1E is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFC1E : entity is TRUE; end DFC1E; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFC1E is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1E_QN_tab : VitalStateTableType := ( ( L, H, H, H, x, L ), ( L, x, L, H, x, H ), ( H, H, x, x, x, S ), ( x, L, x, x, x, H ), ( x, H, x, L, x, S ), ( x, U, x, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFC1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFC1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFC1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFC1E_QN_tab, DataIn => ( CLK_delayed, CLR_ipd, D_delayed, CLK_ipd)); QN_zd := Violation XOR QN_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFC1E_VITAL of DFC1E is for VITAL_ACT end for; end CFG_DFC1E_VITAL; ----- CELL DFC1F ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFC1F is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFC1F : entity is TRUE; end DFC1F; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFC1F is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1C_QN_tab : VitalStateTableType := ( ( L, L, H, H, x, L ), ( L, x, L, H, x, H ), ( H, L, x, x, x, S ), ( x, L, x, L, x, S ), ( x, H, x, x, x, H ), ( x, U, x, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFC1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_negedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFC1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DFC1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFC1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFC1C_QN_tab, DataIn => ( CLK_ipd, CLR_ipd, D_delayed, CLK_delayed)); QN_zd := Violation XOR QN_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFC1F_VITAL of DFC1F is for VITAL_ACT end for; end CFG_DFC1F_VITAL; ----- CELL DFC1G ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFC1G is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFC1G : entity is TRUE; end DFC1G; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFC1G is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1E_QN_tab : VitalStateTableType := ( ( L, H, H, H, x, L ), ( L, x, L, H, x, H ), ( H, H, x, x, x, S ), ( x, L, x, x, x, H ), ( x, H, x, L, x, S ), ( x, U, x, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFC1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFC1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFC1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFC1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFC1E_QN_tab, DataIn => ( CLK_ipd, CLR_ipd, D_delayed, CLK_delayed)); QN_zd := Violation XOR QN_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFC1G_VITAL of DFC1G is for VITAL_ACT end for; end CFG_DFC1G_VITAL; ----- CELL DFE ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE : entity is TRUE; end DFE; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, L ), ( L, L, x, L, H, x, L ), ( L, H, H, x, H, x, H ), ( L, H, x, L, H, x, H ), ( L, x, L, H, H, x, L ), ( L, x, H, H, H, x, H ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01( E_ipd ) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFE", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE_Q_tab, DataIn => ( CLK_delayed, Q_zd, D_delayed, E_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE_VITAL of DFE is for VITAL_ACT end for; end CFG_DFE_VITAL; ----- CELL DFE1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE1B : entity is TRUE; end DFE1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE1B_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, L ), ( L, L, x, H, H, x, L ), ( L, H, H, x, H, x, H ), ( L, H, x, H, H, x, H ), ( L, x, L, L, H, x, L ), ( L, x, H, L, H, x, H ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT E_ipd)) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFE1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE1B_Q_tab, DataIn => ( CLK_delayed, Q_zd, D_delayed, E_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE1B_VITAL of DFE1B is for VITAL_ACT end for; end CFG_DFE1B_VITAL; ----- CELL DFE1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE1C : entity is TRUE; end DFE1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE1B_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, L ), ( L, L, x, H, H, x, L ), ( L, H, H, x, H, x, H ), ( L, H, x, H, H, x, H ), ( L, x, L, L, H, x, L ), ( L, x, H, L, H, x, H ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT E_ipd)) /= '0' , RefTransition => 'F', HeaderMsg => InstancePath & "/DFE1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFE1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Tviol_E_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE1B_Q_tab, DataIn => ( CLK_ipd, Q_zd, D_delayed, E_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE1C_VITAL of DFE1C is for VITAL_ACT end for; end CFG_DFE1C_VITAL; ----- CELL DFE2D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE2D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE2D : entity is TRUE; end DFE2D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE2D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE2D_tab : VitalStateTableType := ( ( L, x, H, x, x, x, x, x, U ), ( L, x, L, x, x, x, x, x, L ), ( H, L, x, H, H, x, H, x, H ), ( H, L, x, H, x, H, H, x, H ), ( H, L, x, x, H, L, H, x, H ), ( H, H, L, x, x, x, x, x, S ), ( H, x, L, x, x, x, L, x, S ), ( H, x, H, x, x, x, x, x, H ), ( x, L, L, L, L, x, H, x, L ), ( x, L, L, L, x, H, H, x, L ), ( x, L, L, x, L, L, H, x, L ), ( U, x, L, L, x, x, x, x, L ), ( H, x, U, H, x, x, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) OR ( E_ipd )) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFE2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DFE2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFE2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_E_CLK_negedge or Tviol_PRE_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE2D_tab, DataIn => ( CLR_ipd, CLK_ipd, PRE_ipd, Q_zd, D_delayed, E_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE2D_VITAL of DFE2D is for VITAL_ACT end for; end CFG_DFE2D_VITAL; ----- CELL DFE3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE3A : entity is TRUE; end DFE3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3A_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, L, H, x, H ), ( H, L, x, H, H, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, L, H, x, L ), ( x, L, x, L, H, H, x, L ), ( U, x, L, x, x, x, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(( CLR_ipd ) AND ( E_ipd )) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3A_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, Q_zd, D_delayed, E_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE3A_VITAL of DFE3A is for VITAL_ACT end for; end CFG_DFE3A_VITAL; ----- CELL DFE3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE3B : entity is TRUE; end DFE3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3A_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, L, H, x, H ), ( H, L, x, H, H, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, L, H, x, L ), ( x, L, x, L, H, H, x, L ), ( U, x, L, x, x, x, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(( CLR_ipd ) AND ( E_ipd )) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Tviol_E_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3A_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, Q_zd, D_delayed, E_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE3B_VITAL of DFE3B is for VITAL_ACT end for; end CFG_DFE3B_VITAL; ----- CELL DFE3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE3C : entity is TRUE; end DFE3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L ), ( U, x, L, x, x, x, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((CLR_ipd) AND (NOT E_ipd)) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3C_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, Q_zd, D_delayed, E_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE3C_VITAL of DFE3C is for VITAL_ACT end for; end CFG_DFE3C_VITAL; ----- CELL DFE3D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE3D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE3D : entity is TRUE; end DFE3D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE3D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L ), ( U, x, L, x, x, x, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01((CLR_ipd) AND (NOT E_ipd)) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFE3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFE3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Tviol_E_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3C_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, Q_zd, D_delayed, E_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE3D_VITAL of DFE3D is for VITAL_ACT end for; end CFG_DFE3D_VITAL; ----- CELL DFE4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE4 : entity is TRUE; end DFE4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE4_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, H, x, L ), ( L, L, L, x, L, H, x, L ), ( L, L, x, L, H, H, x, L ), ( L, x, H, H, x, H, x, H ), ( L, x, H, x, L, H, x, H ), ( L, x, x, H, H, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H ), ( x, U, H, x, x, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd OR (NOT E_ipd)) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE4", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE4", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFE4", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFE4", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE4", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE4_Q_tab, DataIn => ( CLK_delayed, PRE_ipd, Q_zd, D_delayed, E_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE4_VITAL of DFE4 is for VITAL_ACT end for; end CFG_DFE4_VITAL; ----- CELL DFE4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE4A : entity is TRUE; end DFE4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE4_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, H, x, L ), ( L, L, L, x, L, H, x, L ), ( L, L, x, L, H, H, x, L ), ( L, x, H, H, x, H, x, H ), ( L, x, H, x, L, H, x, H ), ( L, x, x, H, H, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H ), ( x, U, H, x, x, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd OR (NOT E_ipd)) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE4A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE4A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFE4A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFE4A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE4A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_E_CLK_negedge or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE4_Q_tab, DataIn => ( CLK_ipd, PRE_ipd, Q_zd, D_delayed, E_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE4A_VITAL of DFE4A is for VITAL_ACT end for; end CFG_DFE4A_VITAL; ----- CELL DFE4B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE4B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE4B : entity is TRUE; end DFE4B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE4B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE4B_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, H, x, L ), ( L, L, L, x, H, H, x, L ), ( L, L, x, L, L, H, x, L ), ( L, x, H, H, x, H, x, H ), ( L, x, H, x, H, H, x, H ), ( L, x, x, H, L, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H ), ( x, U, H, x, x, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd OR E_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFE4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFE4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFE4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE4B_Q_tab, DataIn => ( CLK_delayed, PRE_ipd, Q_zd, D_delayed, E_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE4B_VITAL of DFE4B is for VITAL_ACT end for; end CFG_DFE4B_VITAL; ----- CELL DFE4C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFE4C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFE4C : entity is TRUE; end DFE4C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFE4C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE4B_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, H, x, L ), ( L, L, L, x, H, H, x, L ), ( L, L, x, L, L, H, x, L ), ( L, x, H, H, x, H, x, H ), ( L, x, H, x, H, H, x, H ), ( L, x, x, H, L, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H ), ( x, U, H, x, x, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd OR E_ipd) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE4C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFE4C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFE4C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFE4C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFE4C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_E_CLK_negedge or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE4B_Q_tab, DataIn => ( CLK_ipd, PRE_ipd, Q_zd, D_delayed, E_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFE4C_VITAL of DFE4C is for VITAL_ACT end for; end CFG_DFE4C_VITAL; ----- CELL DFEA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFEA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFEA : entity is TRUE; end DFEA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFEA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, L ), ( L, L, x, L, H, x, L ), ( L, H, H, x, H, x, H ), ( L, H, x, L, H, x, H ), ( L, x, L, H, H, x, L ), ( L, x, H, H, H, x, H ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01( E_ipd ) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DFEA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFEA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFEA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Tviol_E_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE_Q_tab, DataIn => ( CLK_ipd, Q_zd, D_delayed, E_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFEA_VITAL of DFEA is for VITAL_ACT end for; end CFG_DFEA_VITAL; ----- CELL DFEB ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFEB is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFEB : entity is TRUE; end DFEB; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFEB is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFEB_tab : VitalStateTableType := ( ( L, x, H, x, x, x, x, x, U ), ( L, x, L, x, x, x, x, x, L ), ( H, L, x, H, H, x, H, x, H ), ( H, L, x, H, x, L, H, x, H ), ( H, L, x, x, H, H, H, x, H ), ( H, H, L, x, x, x, x, x, S ), ( H, x, L, x, x, x, L, x, S ), ( H, x, H, x, x, x, x, x, H ), ( x, L, L, L, L, x, H, x, L ), ( x, L, L, L, x, L, H, x, L ), ( x, L, L, x, L, H, H, x, L ), ( U, x, L, L, x, x, x, x, L ), ( H, x, U, H, x, x, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) OR (NOT E_ipd)) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFEB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFEB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFEB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFEB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DFEB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFEB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFEB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Tviol_PRE_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_PRE or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFEB_tab, DataIn => ( CLR_ipd, CLK_delayed, PRE_ipd, Q_zd, D_delayed, E_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFEB_VITAL of DFEB is for VITAL_ACT end for; end CFG_DFEB_VITAL; ----- CELL DFEC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFEC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFEC : entity is TRUE; end DFEC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFEC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFEC_tab : VitalStateTableType := ( ( L, x, H, x, x, x, x, x, U ), ( L, x, L, x, x, x, x, x, L ), ( H, L, x, H, H, x, H, x, H ), ( H, L, x, H, x, L, H, x, H ), ( H, L, x, x, H, H, H, x, H ), ( H, H, L, x, x, x, x, x, S ), ( H, x, L, x, x, x, L, x, S ), ( H, x, H, x, x, x, x, x, H ), ( x, L, L, L, L, x, H, x, L ), ( x, L, L, L, x, L, H, x, L ), ( x, L, L, x, L, H, H, x, L ), ( U, x, L, L, x, x, x, x, L ), ( H, x, U, H, x, x, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) OR (NOT E_ipd)) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFEC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_negedge, TimingData => Tmkr_E_CLK_negedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_negedge, SetupLow => tsetup_E_CLK_noedge_negedge, HoldHigh => thold_E_CLK_noedge_negedge, HoldLow => thold_E_CLK_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFEC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFEC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFEC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DFEC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFEC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFEC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_E_CLK_negedge or Tviol_PRE_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFEC_tab, DataIn => ( CLR_ipd, CLK_ipd, PRE_ipd, Q_zd, D_delayed, E_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFEC_VITAL of DFEC is for VITAL_ACT end for; end CFG_DFEC_VITAL; ----- CELL DFED ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFED is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFED : entity is TRUE; end DFED; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFED is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFED_Q_tab : VitalStateTableType := ( ( L, x, H, x, x, x, x, x, U ), ( L, x, L, x, x, x, x, x, L ), ( H, L, x, H, H, x, H, x, H ), ( H, L, x, H, x, H, H, x, H ), ( H, L, x, x, H, L, H, x, H ), ( H, H, L, x, x, x, x, x, S ), ( H, x, L, x, x, x, L, x, S ), ( H, x, H, x, x, x, x, x, H ), ( x, L, L, L, L, x, H, x, L ), ( x, L, L, L, x, H, H, x, L ), ( x, L, L, x, L, L, H, x, L ), ( U, x, L, L, x, x, x, x, L ), ( H, x, U, H, x, x, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) OR ( E_ipd )) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFED", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFED", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFED", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFED", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DFED", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFED", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFED", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_E_CLK_posedge or Tviol_PRE_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_PRE or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFED_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, PRE_ipd, Q_zd, D_delayed, E_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFED_VITAL of DFED is for VITAL_ACT end for; end CFG_DFED_VITAL; ----- CELL DFM ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM : entity is TRUE; end DFM; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_A_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE1B_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, L ), ( L, L, x, H, H, x, L ), ( L, H, H, x, H, x, H ), ( L, H, x, H, H, x, H ), ( L, x, L, L, H, x, L ), ( L, x, H, L, H, x, H ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_posedge, TimingData => Tmkr_A_CLK_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_posedge, SetupLow => tsetup_A_CLK_noedge_posedge, HoldHigh => thold_A_CLK_noedge_posedge, HoldLow => thold_A_CLK_noedge_posedge, CheckEnabled => TO_X01( ( S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_posedge, TimingData => Tmkr_B_CLK_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_posedge, SetupLow => tsetup_B_CLK_noedge_posedge, HoldHigh => thold_B_CLK_noedge_posedge, HoldLow => thold_B_CLK_noedge_posedge, CheckEnabled => TO_X01( (NOT S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_posedge, TimingData => Tmkr_S_CLK_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_posedge, SetupLow => tsetup_S_CLK_noedge_posedge, HoldHigh => thold_S_CLK_noedge_posedge, HoldLow => thold_S_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_posedge or Tviol_S_CLK_posedge or Tviol_B_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE1B_Q_tab, DataIn => ( CLK_delayed, B_delayed, A_delayed, S_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM_VITAL of DFM is for VITAL_ACT end for; end CFG_DFM_VITAL; ----- CELL DFM1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM1B : entity is TRUE; end DFM1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_A_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 4); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM1B_QN_tab : VitalStateTableType := ( ( L, L, x, L, H, x, H ), ( L, L, x, H, H, x, L ), ( L, H, L, x, H, x, H ), ( L, H, H, x, H, x, L ), ( L, x, L, L, H, x, H ), ( L, x, H, H, H, x, L ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_posedge, TimingData => Tmkr_A_CLK_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_posedge, SetupLow => tsetup_A_CLK_noedge_posedge, HoldHigh => thold_A_CLK_noedge_posedge, HoldLow => thold_A_CLK_noedge_posedge, CheckEnabled => TO_X01( ( S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_posedge, TimingData => Tmkr_B_CLK_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_posedge, SetupLow => tsetup_B_CLK_noedge_posedge, HoldHigh => thold_B_CLK_noedge_posedge, HoldLow => thold_B_CLK_noedge_posedge, CheckEnabled => TO_X01( (NOT S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_posedge, TimingData => Tmkr_S_CLK_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_posedge, SetupLow => tsetup_S_CLK_noedge_posedge, HoldHigh => thold_S_CLK_noedge_posedge, HoldLow => thold_S_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFM1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_posedge or Tviol_S_CLK_posedge or Tviol_B_CLK_posedge or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFM1B_QN_tab, DataIn => ( CLK_delayed, S_delayed, B_delayed, A_delayed, CLK_ipd)); QN_zd := Violation XOR QN_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM1B_VITAL of DFM1B is for VITAL_ACT end for; end CFG_DFM1B_VITAL; ----- CELL DFM1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM1C : entity is TRUE; end DFM1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_A_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 4); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM1B_QN_tab : VitalStateTableType := ( ( L, L, x, L, H, x, H ), ( L, L, x, H, H, x, L ), ( L, H, L, x, H, x, H ), ( L, H, H, x, H, x, L ), ( L, x, L, L, H, x, H ), ( L, x, H, H, H, x, L ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_negedge, TimingData => Tmkr_A_CLK_negedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_negedge, SetupLow => tsetup_A_CLK_noedge_negedge, HoldHigh => thold_A_CLK_noedge_negedge, HoldLow => thold_A_CLK_noedge_negedge, CheckEnabled => TO_X01( ( S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_negedge, TimingData => Tmkr_B_CLK_negedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_negedge, SetupLow => tsetup_B_CLK_noedge_negedge, HoldHigh => thold_B_CLK_noedge_negedge, HoldLow => thold_B_CLK_noedge_negedge, CheckEnabled => TO_X01( (NOT S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_negedge, TimingData => Tmkr_S_CLK_negedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_negedge, SetupLow => tsetup_S_CLK_noedge_negedge, HoldHigh => thold_S_CLK_noedge_negedge, HoldLow => thold_S_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFM1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_negedge or Tviol_B_CLK_negedge or Tviol_S_CLK_negedge or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFM1B_QN_tab, DataIn => ( CLK_ipd, S_delayed, B_delayed, A_delayed, CLK_delayed)); QN_zd := Violation XOR QN_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM1C_VITAL of DFM1C is for VITAL_ACT end for; end CFG_DFM1C_VITAL; ----- CELL DFM3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM3 : entity is TRUE; end DFM3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_A_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM3_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, x, L ), ( L, L, x, H, H, x, x, L ), ( L, H, H, x, H, L, x, H ), ( L, H, x, H, H, L, x, H ), ( L, x, L, L, H, x, x, L ), ( L, x, H, L, H, L, x, H ), ( H, x, x, x, x, L, x, S ), ( x, x, x, x, L, L, x, S ), ( x, x, x, x, x, H, x, L ), ( x, x, x, x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_posedge, TimingData => Tmkr_A_CLK_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_posedge, SetupLow => tsetup_A_CLK_noedge_posedge, HoldHigh => thold_A_CLK_noedge_posedge, HoldLow => thold_A_CLK_noedge_posedge, CheckEnabled => TO_X01((CLR_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM3", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_posedge, TimingData => Tmkr_B_CLK_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_posedge, SetupLow => tsetup_B_CLK_noedge_posedge, HoldHigh => thold_B_CLK_noedge_posedge, HoldLow => thold_B_CLK_noedge_posedge, CheckEnabled => TO_X01((CLR_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM3", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_posedge, TimingData => Tmkr_S_CLK_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_posedge, SetupLow => tsetup_S_CLK_noedge_posedge, HoldHigh => thold_S_CLK_noedge_posedge, HoldLow => thold_S_CLK_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM3", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_negedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFM3", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DFM3", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM3", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_posedge or Tviol_S_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLR or Tviol_B_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM3_Q_tab, DataIn => ( CLK_delayed, B_delayed, A_delayed, S_delayed, CLK_ipd, CLR_ipd)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM3_VITAL of DFM3 is for VITAL_ACT end for; end CFG_DFM3_VITAL; ----- CELL DFM3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM3B : entity is TRUE; end DFM3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_A_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L ), ( U, x, x, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_negedge, TimingData => Tmkr_A_CLK_negedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_negedge, SetupLow => tsetup_A_CLK_noedge_negedge, HoldHigh => thold_A_CLK_noedge_negedge, HoldLow => thold_A_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_negedge, TimingData => Tmkr_B_CLK_negedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_negedge, SetupLow => tsetup_B_CLK_noedge_negedge, HoldHigh => thold_B_CLK_noedge_negedge, HoldLow => thold_B_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_negedge, TimingData => Tmkr_S_CLK_negedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_negedge, SetupLow => tsetup_S_CLK_noedge_negedge, HoldHigh => thold_S_CLK_noedge_negedge, HoldLow => thold_S_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFM3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_negedge or Tviol_B_CLK_negedge or Tviol_S_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3C_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, B_delayed, A_delayed, S_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM3B_VITAL of DFM3B is for VITAL_ACT end for; end CFG_DFM3B_VITAL; ----- CELL DFM3E ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM3E is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM3E : entity is TRUE; end DFM3E; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM3E is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_A_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM3_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, x, L ), ( L, L, x, H, H, x, x, L ), ( L, H, H, x, H, L, x, H ), ( L, H, x, H, H, L, x, H ), ( L, x, L, L, H, x, x, L ), ( L, x, H, L, H, L, x, H ), ( H, x, x, x, x, L, x, S ), ( x, x, x, x, L, L, x, S ), ( x, x, x, x, x, H, x, L ), ( x, x, x, x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_negedge, TimingData => Tmkr_A_CLK_negedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_negedge, SetupLow => tsetup_A_CLK_noedge_negedge, HoldHigh => thold_A_CLK_noedge_negedge, HoldLow => thold_A_CLK_noedge_negedge, CheckEnabled => TO_X01((CLR_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_negedge, TimingData => Tmkr_B_CLK_negedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_negedge, SetupLow => tsetup_B_CLK_noedge_negedge, HoldHigh => thold_B_CLK_noedge_negedge, HoldLow => thold_B_CLK_noedge_negedge, CheckEnabled => TO_X01((CLR_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_negedge, TimingData => Tmkr_S_CLK_negedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_negedge, SetupLow => tsetup_S_CLK_noedge_negedge, HoldHigh => thold_S_CLK_noedge_negedge, HoldLow => thold_S_CLK_noedge_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_negedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DFM3E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM3E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_negedge or Tviol_B_CLK_negedge or Tviol_S_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM3_Q_tab, DataIn => ( CLK_ipd, B_delayed, A_delayed, S_delayed, CLK_delayed, CLR_ipd)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM3E_VITAL of DFM3E is for VITAL_ACT end for; end CFG_DFM3E_VITAL; ----- CELL DFM3F ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM3F is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM3F : entity is TRUE; end DFM3F; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM3F is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_A_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM3F_QN_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, H, H, x, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, x, L, x, L, H, x, H ), ( L, x, H, L, x, H, x, H ), ( L, x, x, L, L, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H ), ( x, U, x, x, x, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_posedge, TimingData => Tmkr_A_CLK_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_posedge, SetupLow => tsetup_A_CLK_noedge_posedge, HoldHigh => thold_A_CLK_noedge_posedge, HoldLow => thold_A_CLK_noedge_posedge, CheckEnabled => TO_X01((CLR_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM3F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_posedge, TimingData => Tmkr_B_CLK_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_posedge, SetupLow => tsetup_B_CLK_noedge_posedge, HoldHigh => thold_B_CLK_noedge_posedge, HoldLow => thold_B_CLK_noedge_posedge, CheckEnabled => TO_X01((CLR_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM3F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_posedge, TimingData => Tmkr_S_CLK_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_posedge, SetupLow => tsetup_S_CLK_noedge_posedge, HoldHigh => thold_S_CLK_noedge_posedge, HoldLow => thold_S_CLK_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM3F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_negedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFM3F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DFM3F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM3F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_posedge or Tviol_S_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLR or Tviol_B_CLK_posedge or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFM3F_QN_tab, DataIn => ( CLK_delayed, CLR_ipd, S_delayed, B_delayed, A_delayed, CLK_ipd)); QN_zd := Violation XOR QN_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM3F_VITAL of DFM3F is for VITAL_ACT end for; end CFG_DFM3F_VITAL; ----- CELL DFM3G ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM3G is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM3G : entity is TRUE; end DFM3G; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM3G is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_A_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM3F_QN_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, H, H, x, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, x, L, x, L, H, x, H ), ( L, x, H, L, x, H, x, H ), ( L, x, x, L, L, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H ), ( x, U, x, x, x, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_negedge, TimingData => Tmkr_A_CLK_negedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_negedge, SetupLow => tsetup_A_CLK_noedge_negedge, HoldHigh => thold_A_CLK_noedge_negedge, HoldLow => thold_A_CLK_noedge_negedge, CheckEnabled => TO_X01((CLR_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_negedge, TimingData => Tmkr_B_CLK_negedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_negedge, SetupLow => tsetup_B_CLK_noedge_negedge, HoldHigh => thold_B_CLK_noedge_negedge, HoldLow => thold_B_CLK_noedge_negedge, CheckEnabled => TO_X01((CLR_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_negedge, TimingData => Tmkr_S_CLK_negedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_negedge, SetupLow => tsetup_S_CLK_noedge_negedge, HoldHigh => thold_S_CLK_noedge_negedge, HoldLow => thold_S_CLK_noedge_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_negedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFM3G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DFM3G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM3G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_negedge or Tviol_B_CLK_negedge or Tviol_S_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFM3F_QN_tab, DataIn => ( CLK_ipd, CLR_ipd, S_delayed, B_delayed, A_delayed, CLK_delayed)); QN_zd := Violation XOR QN_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM3G_VITAL of DFM3G is for VITAL_ACT end for; end CFG_DFM3G_VITAL; ----- CELL DFM4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM4 : entity is TRUE; end DFM4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_A_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE4B_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, H, x, L ), ( L, L, L, x, H, H, x, L ), ( L, L, x, L, L, H, x, L ), ( L, x, H, H, x, H, x, H ), ( L, x, H, x, H, H, x, H ), ( L, x, x, H, L, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H ), ( x, U, x, x, x, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_posedge, TimingData => Tmkr_A_CLK_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_posedge, SetupLow => tsetup_A_CLK_noedge_posedge, HoldHigh => thold_A_CLK_noedge_posedge, HoldLow => thold_A_CLK_noedge_posedge, CheckEnabled => TO_X01((PRE_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_posedge, TimingData => Tmkr_B_CLK_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_posedge, SetupLow => tsetup_B_CLK_noedge_posedge, HoldHigh => thold_B_CLK_noedge_posedge, HoldLow => thold_B_CLK_noedge_posedge, CheckEnabled => TO_X01((PRE_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_posedge, TimingData => Tmkr_S_CLK_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_posedge, SetupLow => tsetup_S_CLK_noedge_posedge, HoldHigh => thold_S_CLK_noedge_posedge, HoldLow => thold_S_CLK_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFM4", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM4", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_posedge or Tviol_S_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Tviol_B_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE4B_Q_tab, DataIn => ( CLK_delayed, PRE_ipd, B_delayed, A_delayed, S_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM4_VITAL of DFM4 is for VITAL_ACT end for; end CFG_DFM4_VITAL; ----- CELL DFM4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM4A : entity is TRUE; end DFM4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_A_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM4A_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, H, H, x, x, H, x, H ), ( L, H, x, H, x, H, x, H ), ( L, x, L, L, H, H, x, L ), ( L, x, H, L, x, H, x, H ), ( H, x, x, x, H, x, x, S ), ( x, x, x, x, L, x, x, H ), ( x, x, x, x, H, L, x, S ), ( x, x, x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_posedge, TimingData => Tmkr_A_CLK_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_posedge, SetupLow => tsetup_A_CLK_noedge_posedge, HoldHigh => thold_A_CLK_noedge_posedge, HoldLow => thold_A_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_posedge, TimingData => Tmkr_B_CLK_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_posedge, SetupLow => tsetup_B_CLK_noedge_posedge, HoldHigh => thold_B_CLK_noedge_posedge, HoldLow => thold_B_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_posedge, TimingData => Tmkr_S_CLK_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_posedge, SetupLow => tsetup_S_CLK_noedge_posedge, HoldHigh => thold_S_CLK_noedge_posedge, HoldLow => thold_S_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFM4A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM4A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_posedge or Tviol_S_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Tviol_B_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM4A_Q_tab, DataIn => ( CLK_delayed, B_delayed, A_delayed, S_delayed, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM4A_VITAL of DFM4A is for VITAL_ACT end for; end CFG_DFM4A_VITAL; ----- CELL DFM4B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM4B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM4B : entity is TRUE; end DFM4B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM4B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_A_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM4A_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, H, H, x, x, H, x, H ), ( L, H, x, H, x, H, x, H ), ( L, x, L, L, H, H, x, L ), ( L, x, H, L, x, H, x, H ), ( H, x, x, x, H, x, x, S ), ( x, x, x, x, L, x, x, H ), ( x, x, x, x, H, L, x, S ), ( x, x, x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_negedge, TimingData => Tmkr_A_CLK_negedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_negedge, SetupLow => tsetup_A_CLK_noedge_negedge, HoldHigh => thold_A_CLK_noedge_negedge, HoldLow => thold_A_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_negedge, TimingData => Tmkr_B_CLK_negedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_negedge, SetupLow => tsetup_B_CLK_noedge_negedge, HoldHigh => thold_B_CLK_noedge_negedge, HoldLow => thold_B_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_negedge, TimingData => Tmkr_S_CLK_negedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_negedge, SetupLow => tsetup_S_CLK_noedge_negedge, HoldHigh => thold_S_CLK_noedge_negedge, HoldLow => thold_S_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFM4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_negedge or Pviol_PRE or Tviol_B_CLK_negedge or Tviol_S_CLK_negedge or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM4A_Q_tab, DataIn => ( CLK_ipd, B_delayed, A_delayed, S_delayed, PRE_ipd, CLK_delayed)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM4B_VITAL of DFM4B is for VITAL_ACT end for; end CFG_DFM4B_VITAL; ----- CELL DFM4C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM4C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM4C : entity is TRUE; end DFM4C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM4C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_A_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM4C_QN_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, L, x, L, H, x, H ), ( H, L, H, L, x, H, x, H ), ( H, L, x, L, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, x, H, H, x, L ), ( x, L, H, H, x, H, x, L ), ( x, L, x, H, H, H, x, L ), ( U, x, x, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_posedge, TimingData => Tmkr_A_CLK_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_posedge, SetupLow => tsetup_A_CLK_noedge_posedge, HoldHigh => thold_A_CLK_noedge_posedge, HoldLow => thold_A_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_posedge, TimingData => Tmkr_B_CLK_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_posedge, SetupLow => tsetup_B_CLK_noedge_posedge, HoldHigh => thold_B_CLK_noedge_posedge, HoldLow => thold_B_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_posedge, TimingData => Tmkr_S_CLK_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_posedge, SetupLow => tsetup_S_CLK_noedge_posedge, HoldHigh => thold_S_CLK_noedge_posedge, HoldLow => thold_S_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFM4C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFM4C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM4C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_posedge or Tviol_S_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Tviol_B_CLK_posedge or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFM4C_QN_tab, DataIn => ( PRE_ipd, CLK_delayed, S_delayed, B_delayed, A_delayed, CLK_ipd)); QN_zd := Violation XOR QN_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM4C_VITAL of DFM4C is for VITAL_ACT end for; end CFG_DFM4C_VITAL; ----- CELL DFM4D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM4D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM4D : entity is TRUE; end DFM4D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM4D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_A_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM4C_QN_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, L, x, L, H, x, H ), ( H, L, H, L, x, H, x, H ), ( H, L, x, L, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, x, H, H, x, L ), ( x, L, H, H, x, H, x, L ), ( x, L, x, H, H, H, x, L ), ( U, x, x, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_negedge, TimingData => Tmkr_A_CLK_negedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_negedge, SetupLow => tsetup_A_CLK_noedge_negedge, HoldHigh => thold_A_CLK_noedge_negedge, HoldLow => thold_A_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_negedge, TimingData => Tmkr_B_CLK_negedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_negedge, SetupLow => tsetup_B_CLK_noedge_negedge, HoldHigh => thold_B_CLK_noedge_negedge, HoldLow => thold_B_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_negedge, TimingData => Tmkr_S_CLK_negedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_negedge, SetupLow => tsetup_S_CLK_noedge_negedge, HoldHigh => thold_S_CLK_noedge_negedge, HoldLow => thold_S_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFM4D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM4D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_negedge or Pviol_PRE or Tviol_B_CLK_negedge or Tviol_S_CLK_negedge or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFM4C_QN_tab, DataIn => ( PRE_ipd, CLK_ipd, S_delayed, B_delayed, A_delayed, CLK_delayed)); QN_zd := Violation XOR QN_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM4D_VITAL of DFM4D is for VITAL_ACT end for; end CFG_DFM4D_VITAL; ----- CELL DFM4E ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM4E is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM4E : entity is TRUE; end DFM4E; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM4E is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_A_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE4B_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, H, x, L ), ( L, L, L, x, H, H, x, L ), ( L, L, x, L, L, H, x, L ), ( L, x, H, H, x, H, x, H ), ( L, x, H, x, H, H, x, H ), ( L, x, x, H, L, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H ), ( x, U, x, x, x, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_negedge, TimingData => Tmkr_A_CLK_negedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_negedge, SetupLow => tsetup_A_CLK_noedge_negedge, HoldHigh => thold_A_CLK_noedge_negedge, HoldLow => thold_A_CLK_noedge_negedge, CheckEnabled => TO_X01((PRE_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_negedge, TimingData => Tmkr_B_CLK_negedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_negedge, SetupLow => tsetup_B_CLK_noedge_negedge, HoldHigh => thold_B_CLK_noedge_negedge, HoldLow => thold_B_CLK_noedge_negedge, CheckEnabled => TO_X01((PRE_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_negedge, TimingData => Tmkr_S_CLK_negedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_negedge, SetupLow => tsetup_S_CLK_noedge_negedge, HoldHigh => thold_S_CLK_noedge_negedge, HoldLow => thold_S_CLK_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFM4E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFM4E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM4E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_negedge or Pviol_PRE or Tviol_B_CLK_negedge or Tviol_S_CLK_negedge or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE4B_Q_tab, DataIn => ( CLK_ipd, PRE_ipd, B_delayed, A_delayed, S_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM4E_VITAL of DFM4E is for VITAL_ACT end for; end CFG_DFM4E_VITAL; ----- CELL DFM5A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM5A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM5A : entity is TRUE; end DFM5A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM5A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_A_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM5A_Q_tab : VitalStateTableType := ( ( L, x, H, x, x, x, x, x, U ), ( L, x, L, x, x, x, x, x, L ), ( H, L, x, H, H, x, H, x, H ), ( H, L, x, H, x, H, H, x, H ), ( H, L, x, x, H, L, H, x, H ), ( H, H, L, x, x, x, x, x, S ), ( H, x, L, x, x, x, L, x, S ), ( H, x, H, x, x, x, x, x, H ), ( x, L, L, L, L, x, H, x, L ), ( x, L, L, L, x, H, H, x, L ), ( x, L, L, x, L, L, H, x, L ), ( U, x, L, x, x, x, x, L, L ), ( H, x, U, x, x, x, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_posedge, TimingData => Tmkr_A_CLK_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_posedge, SetupLow => tsetup_A_CLK_noedge_posedge, HoldHigh => thold_A_CLK_noedge_posedge, HoldLow => thold_A_CLK_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR (NOT CLR_ipd) OR ( S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM5A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_posedge, TimingData => Tmkr_B_CLK_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_posedge, SetupLow => tsetup_B_CLK_noedge_posedge, HoldHigh => thold_B_CLK_noedge_posedge, HoldLow => thold_B_CLK_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR (NOT CLR_ipd) OR (NOT S_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM5A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_posedge, TimingData => Tmkr_S_CLK_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_posedge, SetupLow => tsetup_S_CLK_noedge_posedge, HoldHigh => thold_S_CLK_noedge_posedge, HoldLow => thold_S_CLK_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM5A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFM5A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFM5A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DFM5A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFM5A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM5A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_posedge or Tviol_S_CLK_posedge or Tviol_PRE_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_PRE or Pviol_CLR or Tviol_B_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM5A_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, PRE_ipd, B_delayed, A_delayed, S_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM5A_VITAL of DFM5A is for VITAL_ACT end for; end CFG_DFM5A_VITAL; ----- CELL DFM5B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFM5B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFM5B : entity is TRUE; end DFM5B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFM5B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_A_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM5B_Q_tab : VitalStateTableType := ( ( L, x, H, x, x, x, x, x, U ), ( L, x, L, x, x, x, x, x, L ), ( H, L, x, H, H, x, H, x, H ), ( H, L, x, H, x, H, H, x, H ), ( H, L, x, x, H, L, H, x, H ), ( H, H, L, x, x, x, x, x, S ), ( H, x, L, x, x, x, L, x, S ), ( H, x, H, x, x, x, x, x, H ), ( x, L, L, L, L, x, H, x, L ), ( x, L, L, L, x, H, H, x, L ), ( x, L, L, x, L, L, H, x, L ), ( U, x, L, x, x, x, x, L, L ), ( H, x, U, x, x, x, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_negedge, TimingData => Tmkr_A_CLK_negedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_negedge, SetupLow => tsetup_A_CLK_noedge_negedge, HoldHigh => thold_A_CLK_noedge_negedge, HoldLow => thold_A_CLK_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR (NOT CLR_ipd) OR ( S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM5B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_negedge, TimingData => Tmkr_B_CLK_negedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_negedge, SetupLow => tsetup_B_CLK_noedge_negedge, HoldHigh => thold_B_CLK_noedge_negedge, HoldLow => thold_B_CLK_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR (NOT CLR_ipd) OR (NOT S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM5B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_negedge, TimingData => Tmkr_S_CLK_negedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_negedge, SetupLow => tsetup_S_CLK_noedge_negedge, HoldHigh => thold_S_CLK_noedge_negedge, HoldLow => thold_S_CLK_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM5B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFM5B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFM5B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DFM5B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFM5B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFM5B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_negedge or Pviol_PRE or Tviol_B_CLK_negedge or Tviol_S_CLK_negedge or Tviol_PRE_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM5B_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, PRE_ipd, B_delayed, A_delayed, S_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFM5B_VITAL of DFM5B is for VITAL_ACT end for; end CFG_DFM5B_VITAL; ----- CELL DFMA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFMA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFMA : entity is TRUE; end DFMA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFMA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_A_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE1B_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, L ), ( L, L, x, H, H, x, L ), ( L, H, H, x, H, x, H ), ( L, H, x, H, H, x, H ), ( L, x, L, L, H, x, L ), ( L, x, H, L, H, x, H ), ( H, x, x, x, x, x, S ), ( x, x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_negedge, TimingData => Tmkr_A_CLK_negedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_negedge, SetupLow => tsetup_A_CLK_noedge_negedge, HoldHigh => thold_A_CLK_noedge_negedge, HoldLow => thold_A_CLK_noedge_negedge, CheckEnabled => TO_X01( ( S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFMA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_negedge, TimingData => Tmkr_B_CLK_negedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_negedge, SetupLow => tsetup_B_CLK_noedge_negedge, HoldHigh => thold_B_CLK_noedge_negedge, HoldLow => thold_B_CLK_noedge_negedge, CheckEnabled => TO_X01( (NOT S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFMA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_negedge, TimingData => Tmkr_S_CLK_negedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_negedge, SetupLow => tsetup_S_CLK_noedge_negedge, HoldHigh => thold_S_CLK_noedge_negedge, HoldLow => thold_S_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFMA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFMA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_negedge or Tviol_B_CLK_negedge or Tviol_S_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE1B_Q_tab, DataIn => ( CLK_ipd, B_delayed, A_delayed, S_delayed, CLK_delayed)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFMA_VITAL of DFMA is for VITAL_ACT end for; end CFG_DFMA_VITAL; ----- CELL DFMB ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFMB is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFMB : entity is TRUE; end DFMB; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFMB is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_A_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L ), ( U, x, x, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_posedge, TimingData => Tmkr_A_CLK_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_posedge, SetupLow => tsetup_A_CLK_noedge_posedge, HoldHigh => thold_A_CLK_noedge_posedge, HoldLow => thold_A_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd ) OR ( S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFMB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_posedge, TimingData => Tmkr_B_CLK_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_posedge, SetupLow => tsetup_B_CLK_noedge_posedge, HoldHigh => thold_B_CLK_noedge_posedge, HoldLow => thold_B_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd ) OR (NOT S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFMB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_posedge, TimingData => Tmkr_S_CLK_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_posedge, SetupLow => tsetup_S_CLK_noedge_posedge, HoldHigh => thold_S_CLK_noedge_posedge, HoldLow => thold_S_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFMB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFMB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFMB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFMB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_posedge or Tviol_S_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_CLR or Tviol_B_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3C_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, B_delayed, A_delayed, S_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFMB_VITAL of DFMB is for VITAL_ACT end for; end CFG_DFMB_VITAL; ----- CELL DFME1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFME1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_E_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; E : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFME1A : entity is TRUE; end DFME1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFME1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, E_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_A_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_E_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_E_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); VARIABLE A_delayed : STD_ULOGIC := 'X'; VARIABLE B_delayed : STD_ULOGIC := 'X'; VARIABLE S_delayed : STD_ULOGIC := 'X'; VARIABLE E_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFME1A_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, x, H, x, L ), ( L, L, L, x, H, x, H, x, L ), ( L, L, x, L, L, x, H, x, L ), ( L, L, x, x, x, H, H, x, L ), ( L, H, H, H, x, x, H, x, H ), ( L, H, H, x, H, x, H, x, H ), ( L, H, x, H, L, x, H, x, H ), ( L, H, x, x, x, H, H, x, H ), ( L, x, L, L, x, L, H, x, L ), ( L, x, L, x, H, L, H, x, L ), ( L, x, H, H, x, L, H, x, H ), ( L, x, H, x, H, L, H, x, H ), ( L, x, x, L, L, L, H, x, L ), ( L, x, x, H, L, L, H, x, H ), ( H, x, x, x, x, x, x, x, S ), ( x, x, x, x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_CLK_posedge, TimingData => Tmkr_A_CLK_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_A_CLK_noedge_posedge, SetupLow => tsetup_A_CLK_noedge_posedge, HoldHigh => thold_A_CLK_noedge_posedge, HoldLow => thold_A_CLK_noedge_posedge, CheckEnabled => TO_X01(E_ipd OR S_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_CLK_posedge, TimingData => Tmkr_B_CLK_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_B_CLK_noedge_posedge, SetupLow => tsetup_B_CLK_noedge_posedge, HoldHigh => thold_B_CLK_noedge_posedge, HoldLow => thold_B_CLK_noedge_posedge, CheckEnabled => TO_X01(E_ipd OR (NOT S_ipd)) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_CLK_posedge, TimingData => Tmkr_S_CLK_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_S_CLK_noedge_posedge, SetupLow => tsetup_S_CLK_noedge_posedge, HoldHigh => thold_S_CLK_noedge_posedge, HoldLow => thold_S_CLK_noedge_posedge, CheckEnabled => TO_X01(E_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_E_CLK_posedge, TimingData => Tmkr_E_CLK_posedge, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_E_CLK_noedge_posedge, SetupLow => tsetup_E_CLK_noedge_posedge, HoldHigh => thold_E_CLK_noedge_posedge, HoldLow => thold_E_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_CLK_posedge or Tviol_S_CLK_posedge or Tviol_E_CLK_posedge or Tviol_B_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFME1A_Q_tab, DataIn => ( CLK_delayed, Q_zd, B_delayed, A_delayed, S_delayed, E_delayed, CLK_ipd)); Q_zd := Violation XOR Q_zd; A_delayed := A_ipd; B_delayed := B_ipd; S_delayed := S_ipd; E_delayed := E_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFME1A_VITAL of DFME1A is for VITAL_ACT end for; end CFG_DFME1A_VITAL; ----- CELL DFP1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1 : entity is TRUE; end DFP1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1_Q_tab : VitalStateTableType := ( ( L, L, L, H, x, L ), ( L, H, x, H, x, H ), ( H, x, L, x, x, S ), ( x, x, L, L, x, S ), ( x, x, H, x, x, H ), ( x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFP1_Q_tab, DataIn => ( CLK_delayed, D_delayed, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1_VITAL of DFP1 is for VITAL_ACT end for; end CFG_DFP1_VITAL; ----- CELL DFP1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1A : entity is TRUE; end DFP1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1_Q_tab : VitalStateTableType := ( ( L, L, L, H, x, L ), ( L, H, x, H, x, H ), ( H, x, L, x, x, S ), ( x, x, L, L, x, S ), ( x, x, H, x, x, H ), ( x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFP1_Q_tab, DataIn => ( CLK_ipd, D_delayed, PRE_ipd, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1A_VITAL of DFP1A is for VITAL_ACT end for; end CFG_DFP1A_VITAL; ----- CELL DFP1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1B : entity is TRUE; end DFP1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1B_Q_tab : VitalStateTableType := ( ( L, L, H, H, x, L ), ( L, H, x, H, x, H ), ( H, x, H, x, x, S ), ( x, x, L, x, x, H ), ( x, x, H, L, x, S ), ( x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFP1B_Q_tab, DataIn => ( CLK_delayed, D_delayed, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1B_VITAL of DFP1B is for VITAL_ACT end for; end CFG_DFP1B_VITAL; ----- CELL DFP1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1C : entity is TRUE; end DFP1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1C_QN_tab : VitalStateTableType := ( ( L, L, H, L, x, H ), ( L, H, H, x, x, L ), ( H, x, x, L, x, S ), ( x, x, L, L, x, S ), ( x, x, x, H, x, L ), ( x, x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFP1C_QN_tab, DataIn => ( CLK_delayed, D_delayed, CLK_ipd, PRE_ipd)); QN_zd := Violation XOR QN_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1C_VITAL of DFP1C is for VITAL_ACT end for; end CFG_DFP1C_VITAL; ----- CELL DFP1D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1D : entity is TRUE; end DFP1D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1B_Q_tab : VitalStateTableType := ( ( L, L, H, H, x, L ), ( L, H, x, H, x, H ), ( H, x, H, x, x, S ), ( x, x, L, x, x, H ), ( x, x, H, L, x, S ), ( x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFP1B_Q_tab, DataIn => ( CLK_ipd, D_delayed, PRE_ipd, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1D_VITAL of DFP1D is for VITAL_ACT end for; end CFG_DFP1D_VITAL; ----- CELL DFP1E ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1E is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1E : entity is TRUE; end DFP1E; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1E is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1E_QN_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, L, H, x, H ), ( H, H, x, x, x, S ), ( H, x, x, L, x, S ), ( x, L, H, H, x, L ), ( U, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFP1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFP1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_PRE or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFP1E_QN_tab, DataIn => ( PRE_ipd, CLK_delayed, D_delayed, CLK_ipd)); QN_zd := Violation XOR QN_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1E_VITAL of DFP1E is for VITAL_ACT end for; end CFG_DFP1E_VITAL; ----- CELL DFP1F ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1F is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1F : entity is TRUE; end DFP1F; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1F is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1C_QN_tab : VitalStateTableType := ( ( L, L, H, L, x, H ), ( L, H, H, x, x, L ), ( H, x, x, L, x, S ), ( x, x, L, L, x, S ), ( x, x, x, H, x, L ), ( x, x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DFP1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFP1C_QN_tab, DataIn => ( CLK_ipd, D_delayed, CLK_delayed, PRE_ipd)); QN_zd := Violation XOR QN_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1F_VITAL of DFP1F is for VITAL_ACT end for; end CFG_DFP1F_VITAL; ----- CELL DFP1G ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFP1G is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFP1G : entity is TRUE; end DFP1G; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFP1G is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 3); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1E_QN_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, L, H, x, H ), ( H, H, x, x, x, S ), ( H, x, x, L, x, S ), ( x, L, H, H, x, L ), ( U, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFP1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFP1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFP1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DFP1E_QN_tab, DataIn => ( PRE_ipd, CLK_ipd, D_delayed, CLK_delayed)); QN_zd := Violation XOR QN_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_QN, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFP1G_VITAL of DFP1G is for VITAL_ACT end for; end CFG_DFP1G_VITAL; ----- CELL DFPC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFPC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFPC : entity is TRUE; end DFPC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFPC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFPC_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, L ), ( H, L, H, x, H, x, H ), ( H, H, x, L, x, x, S ), ( H, x, x, L, L, x, S ), ( H, x, x, H, x, x, H ), ( x, L, L, L, H, x, L ), ( U, x, x, x, x, L, L ), ( H, x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_posedge, TimingData => Tmkr_D_CLK_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_posedge, SetupLow => tsetup_D_CLK_noedge_posedge, HoldHigh => thold_D_CLK_noedge_posedge, HoldLow => thold_D_CLK_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_posedge or Tviol_PRE_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_PRE or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFPC_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, D_delayed, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFPC_VITAL of DFPC is for VITAL_ACT end for; end CFG_DFPC_VITAL; ----- CELL DFPCA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DFPCA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DFPCA : entity is TRUE; end DFPCA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DFPCA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE D_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFPCA_tab : VitalStateTableType := ( ( L, x, x, H, x, x, U ), ( L, x, x, L, x, x, L ), ( H, L, H, x, H, x, H ), ( H, H, x, L, x, x, S ), ( H, x, x, L, L, x, S ), ( H, x, x, H, x, x, H ), ( x, L, L, L, H, x, L ), ( U, x, x, L, x, L, L ), ( H, x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_CLK_negedge, TimingData => Tmkr_D_CLK_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_D_CLK_noedge_negedge, SetupLow => tsetup_D_CLK_noedge_negedge, HoldHigh => thold_D_CLK_noedge_negedge, HoldLow => thold_D_CLK_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFPCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DFPCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DFPCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DFPCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DFPCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DFPCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_CLK_negedge or Pviol_PRE or Tviol_PRE_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFPCA_tab, DataIn => ( CLR_ipd, CLK_ipd, D_delayed, PRE_ipd, CLK_delayed)); Q_zd := Violation XOR Q_zd; D_delayed := D_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DFPCA_VITAL of DFPCA is for VITAL_ACT end for; end CFG_DFPCA_VITAL; ----- CELL DL1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL1 : entity is TRUE; end DL1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of DL1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 1); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DL1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DL1_Q_tab, DataIn => ( D_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL1_VITAL of DL1 is for VITAL_ACT end for; end CFG_DL1_VITAL; ----- CELL DL1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL1A : entity is TRUE; end DL1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of DL1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 1); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DL1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Pviol_G; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DL1A_QN_tab, DataIn => ( D_ipd, G_ipd)); QN_zd := Violation XOR QN_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (D_ipd'last_event, tpd_D_QN, TRUE), 1 => (G_ipd'last_event, tpd_G_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL1A_VITAL of DL1A is for VITAL_ACT end for; end CFG_DL1A_VITAL; ----- CELL DL1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL1B : entity is TRUE; end DL1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of DL1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 1); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DL1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DL1B_Q_tab, DataIn => ( G_ipd, D_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL1B_VITAL of DL1B is for VITAL_ACT end for; end CFG_DL1B_VITAL; ----- CELL DL1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL1C : entity is TRUE; end DL1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of DL1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 1); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DL1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Pviol_G; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DL1C_QN_tab, DataIn => ( G_ipd, D_ipd)); QN_zd := Violation XOR QN_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (D_ipd'last_event, tpd_D_QN, TRUE), 1 => (G_ipd'last_event, tpd_G_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL1C_VITAL of DL1C is for VITAL_ACT end for; end CFG_DL1C_VITAL; ----- CELL DL2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL2A : entity is TRUE; end DL2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DL2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DL2A_tab : VitalStateTableType := ( ( L, x, H, x, x, U ), ( L, x, L, x, x, L ), ( H, H, x, H, x, H ), ( H, x, L, L, x, S ), ( H, x, H, x, x, H ), ( x, L, L, H, x, L ), ( U, x, L, x, L, L ), ( H, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_negedge, TimingData => Tmkr_PRE_G_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_negedge_negedge, Removal => thold_PRE_G_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_negedge, TimingData => Tmkr_CLR_G_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_posedge_negedge, Removal => thold_CLR_G_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_PRE_G_negedge or Pviol_PRE or Tviol_CLR_G_negedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DL2A_tab, DataIn => ( CLR_ipd, D_ipd, PRE_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 3 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL2A_VITAL of DL2A is for VITAL_ACT end for; end CFG_DL2A_VITAL; ----- CELL DL2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL2B : entity is TRUE; end DL2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DL2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DL2B_tab : VitalStateTableType := ( ( H, L, x, x, x, U ), ( L, L, x, x, x, L ), ( L, H, H, x, x, S ), ( L, x, L, H, x, L ), ( H, H, x, x, x, H ), ( x, H, L, L, x, H ), ( U, H, x, x, H, H ), ( L, U, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(( (NOT PRE_ipd) ) OR ( CLR_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DL2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_posedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TO_X01( ( CLR_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DL2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DL2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(( (NOT PRE_ipd) ) OR ( CLR_ipd ) ) /= '1', HeaderMsg => InstancePath &"/DL2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TO_X01( ( CLR_ipd ) ) /= '1', HeaderMsg => InstancePath &"/DL2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Tviol_CLR_G_posedge or Pviol_PRE or Pviol_G or Pviol_CLR; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DL2B_tab, DataIn => ( CLR_ipd, PRE_ipd, G_ipd, D_ipd)); QN_zd := Violation XOR QN_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (D_ipd'last_event, tpd_D_QN, TRUE), 1 => (G_ipd'last_event, tpd_G_QN, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_QN, TRUE), 3 => (CLR_ipd'last_event, tpd_CLR_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL2B_VITAL of DL2B is for VITAL_ACT end for; end CFG_DL2B_VITAL; ----- CELL DL2C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL2C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL2C : entity is TRUE; end DL2C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DL2C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DL2C_tab : VitalStateTableType := ( ( L, x, x, H, x, U ), ( L, x, x, L, x, L ), ( H, L, H, x, x, H ), ( H, H, x, L, x, S ), ( H, x, x, H, x, H ), ( x, L, L, L, x, L ), ( U, x, x, L, L, L ), ( H, x, x, U, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_negedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_posedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Tviol_CLR_G_posedge or Pviol_PRE or Pviol_G or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DL2C_tab, DataIn => ( CLR_ipd, G_ipd, D_ipd, PRE_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 3 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL2C_VITAL of DL2C is for VITAL_ACT end for; end CFG_DL2C_VITAL; ----- CELL DL2D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DL2D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DL2D : entity is TRUE; end DL2D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DL2D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DL2D_tab : VitalStateTableType := ( ( H, L, x, x, x, U ), ( L, L, x, x, x, L ), ( L, H, x, L, x, S ), ( L, x, H, H, x, L ), ( H, H, x, x, x, H ), ( x, H, L, H, x, H ), ( U, H, x, x, H, H ), ( L, U, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01(( (NOT PRE_ipd) ) OR ( CLR_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DL2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_negedge, TimingData => Tmkr_PRE_G_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_posedge_negedge, Removal => thold_PRE_G_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TO_X01( ( CLR_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DL2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_negedge, TimingData => Tmkr_CLR_G_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_negedge, Removal => thold_CLR_G_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DL2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(( (NOT PRE_ipd) ) OR ( CLR_ipd ) ) /= '1', HeaderMsg => InstancePath &"/DL2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TO_X01( ( CLR_ipd ) ) /= '1', HeaderMsg => InstancePath &"/DL2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DL2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_PRE_G_negedge or Pviol_PRE or Tviol_CLR_G_negedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DL2D_tab, DataIn => ( CLR_ipd, PRE_ipd, D_ipd, G_ipd)); QN_zd := Violation XOR QN_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (D_ipd'last_event, tpd_D_QN, TRUE), 1 => (G_ipd'last_event, tpd_G_QN, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_QN, TRUE), 3 => (CLR_ipd'last_event, tpd_CLR_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DL2D_VITAL of DL2D is for VITAL_ACT end for; end CFG_DL2D_VITAL; ----- CELL DLC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLC : entity is TRUE; end DLC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLC_Q_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, H, H, x, H ), ( H, x, L, x, S ), ( x, L, H, x, L ), ( U, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_negedge, TimingData => Tmkr_CLR_G_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_posedge_negedge, Removal => thold_CLR_G_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DLC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_CLR_G_negedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLC_Q_tab, DataIn => ( CLR_ipd, D_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLC_VITAL of DLC is for VITAL_ACT end for; end CFG_DLC_VITAL; ----- CELL DLC1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLC1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLC1 : entity is TRUE; end DLC1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLC1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLC1_Q_tab : VitalStateTableType := ( ( L, H, x, x, L ), ( H, H, L, x, H ), ( x, L, L, x, S ), ( x, x, H, x, L ), ( x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_negedge, TimingData => Tmkr_CLR_G_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_negedge, Removal => thold_CLR_G_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DLC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLC1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_CLR_G_negedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLC1_Q_tab, DataIn => ( D_ipd, G_ipd, CLR_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLC1_VITAL of DLC1 is for VITAL_ACT end for; end CFG_DLC1_VITAL; ----- CELL DLC1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLC1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLC1A : entity is TRUE; end DLC1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLC1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLC1A_Q_tab : VitalStateTableType := ( ( L, L, x, x, L ), ( L, H, L, x, H ), ( H, x, L, x, S ), ( x, x, H, x, L ), ( x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DLC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLC1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_CLR_G_posedge or Pviol_G or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLC1A_Q_tab, DataIn => ( G_ipd, D_ipd, CLR_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLC1A_VITAL of DLC1A is for VITAL_ACT end for; end CFG_DLC1A_VITAL; ----- CELL DLC1F ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLC1F is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLC1F : entity is TRUE; end DLC1F; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLC1F is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLC1F_QN_tab : VitalStateTableType := ( ( L, H, H, x, L ), ( L, x, L, x, S ), ( H, x, x, x, H ), ( x, L, H, x, H ), ( U, x, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLC1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_negedge, TimingData => Tmkr_CLR_G_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_negedge, Removal => thold_CLR_G_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLC1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DLC1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLC1F", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_CLR_G_negedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DLC1F_QN_tab, DataIn => ( CLR_ipd, D_ipd, G_ipd)); QN_zd := Violation XOR QN_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (D_ipd'last_event, tpd_D_QN, TRUE), 1 => (G_ipd'last_event, tpd_G_QN, TRUE), 2 => (CLR_ipd'last_event, tpd_CLR_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLC1F_VITAL of DLC1F is for VITAL_ACT end for; end CFG_DLC1F_VITAL; ----- CELL DLC1G ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLC1G is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLC1G : entity is TRUE; end DLC1G; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLC1G is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLC1G_QN_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( L, x, L, x, H ), ( H, L, x, x, S ), ( x, H, x, x, H ), ( x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLC1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLC1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DLC1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLC1G", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_CLR_G_posedge or Pviol_G or Pviol_CLR; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DLC1G_QN_tab, DataIn => ( G_ipd, CLR_ipd, D_ipd)); QN_zd := Violation XOR QN_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (D_ipd'last_event, tpd_D_QN, TRUE), 1 => (G_ipd'last_event, tpd_G_QN, TRUE), 2 => (CLR_ipd'last_event, tpd_CLR_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLC1G_VITAL of DLC1G is for VITAL_ACT end for; end CFG_DLC1G_VITAL; ----- CELL DLCA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLCA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLCA : entity is TRUE; end DLCA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLCA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLCA_Q_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, L, H, x, H ), ( H, H, x, x, S ), ( x, L, L, x, L ), ( U, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_posedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/DLCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLCA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_CLR_G_posedge or Pviol_G or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLCA_Q_tab, DataIn => ( CLR_ipd, G_ipd, D_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLCA_VITAL of DLCA is for VITAL_ACT end for; end CFG_DLCA_VITAL; ----- CELL DLE ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLE is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_E_posedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLE : entity is TRUE; end DLE; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLE is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLE_Q_tab : VitalStateTableType := ( ( L, H, H, x, L ), ( H, H, H, x, H ), ( x, L, x, x, S ), ( x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01(E_ipd) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DLE", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_negedge, TimingData => Tmkr_D_E_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_negedge, SetupLow => tsetup_D_E_noedge_negedge, HoldHigh => thold_D_E_noedge_negedge, HoldLow => thold_D_E_noedge_negedge, CheckEnabled => TO_X01(G_ipd) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DLE", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_E_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(G_ipd) /= '0', HeaderMsg => InstancePath &"/DLE", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(E_ipd) /= '0', HeaderMsg => InstancePath &"/DLE", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_D_E_negedge or Pviol_E or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLE_Q_tab, DataIn => ( D_ipd, G_ipd, E_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLE_VITAL of DLE is for VITAL_ACT end for; end CFG_DLE_VITAL; ----- CELL DLE1D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLE1D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLE1D : entity is TRUE; end DLE1D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLE1D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLE1D_QN_tab : VitalStateTableType := ( ( L, L, L, x, H ), ( L, L, H, x, L ), ( H, x, x, x, S ), ( x, H, x, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(NOT E_ipd) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_posedge, TimingData => Tmkr_D_E_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_posedge, SetupLow => tsetup_D_E_noedge_posedge, HoldHigh => thold_D_E_noedge_posedge, HoldLow => thold_D_E_noedge_posedge, CheckEnabled => TO_X01(NOT G_ipd) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_E_negedge, CheckEnabled => TO_X01(NOT G_ipd) /= '0', HeaderMsg => InstancePath &"/DLE1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(NOT E_ipd) /= '0', HeaderMsg => InstancePath &"/DLE1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Pviol_E or Tviol_D_E_posedge or Pviol_G; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DLE1D_QN_tab, DataIn => ( G_ipd, E_ipd, D_ipd)); QN_zd := Violation XOR QN_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (D_ipd'last_event, tpd_D_QN, TRUE), 1 => (E_ipd'last_event, tpd_E_QN, TRUE), 2 => (G_ipd'last_event, tpd_G_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLE1D_VITAL of DLE1D is for VITAL_ACT end for; end CFG_DLE1D_VITAL; ----- CELL DLE2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLE2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_E_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_E_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLE2A : entity is TRUE; end DLE2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLE2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_E_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_E_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFC1_Q_tab : VitalStateTableType := ( ( L, L, H, x, x, L ), ( L, H, H, L, x, H ), ( H, x, x, L, x, S ), ( x, x, L, L, x, S ), ( x, x, x, H, x, L ), ( x, x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd OR (NOT E_ipd)) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_negedge, TimingData => Tmkr_D_E_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_negedge, SetupLow => tsetup_D_E_noedge_negedge, HoldHigh => thold_D_E_noedge_negedge, HoldLow => thold_D_E_noedge_negedge, CheckEnabled => TO_X01(CLR_ipd OR (G_ipd)) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLE2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_E_negedge, TimingData => Tmkr_CLR_E_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, Recovery => trecovery_CLR_E_negedge_negedge, Removal => thold_CLR_E_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLE2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_E_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(CLR_ipd OR (G_ipd)) /= '1', HeaderMsg => InstancePath &"/DLE2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(CLR_ipd OR (NOT E_ipd)) /= '1', HeaderMsg => InstancePath &"/DLE2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLE2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_D_E_negedge or Pviol_E or Tviol_CLR_G_posedge or Tviol_CLR_E_negedge or Pviol_G or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFC1_Q_tab, DataIn => ( G_ipd, D_ipd, E_ipd, CLR_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE), 3 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLE2A_VITAL of DLE2A is for VITAL_ACT end for; end CFG_DLE2A_VITAL; ----- CELL DLE2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLE2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_posedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_E_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLE2B : entity is TRUE; end DLE2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLE2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLE2B_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, L ), ( H, L, L, H, x, H ), ( H, H, x, x, x, S ), ( H, x, H, x, x, S ), ( x, L, L, L, x, L ), ( U, x, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01((CLR_ipd) AND (NOT E_ipd)) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_posedge, TimingData => Tmkr_D_E_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_posedge, SetupLow => tsetup_D_E_noedge_posedge, HoldHigh => thold_D_E_noedge_posedge, HoldLow => thold_D_E_noedge_posedge, CheckEnabled => TO_X01((CLR_ipd) AND (NOT G_ipd)) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_posedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_E_posedge, TimingData => Tmkr_CLR_E_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, Recovery => trecovery_CLR_E_posedge_posedge, Removal => thold_CLR_E_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_E_negedge, CheckEnabled => TO_X01((CLR_ipd) AND (NOT G_ipd)) /= '0', HeaderMsg => InstancePath &"/DLE2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01((CLR_ipd) AND (NOT E_ipd)) /= '0', HeaderMsg => InstancePath &"/DLE2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLE2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_CLR_G_posedge or Pviol_E or Tviol_D_E_posedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLE2B_Q_tab, DataIn => ( CLR_ipd, G_ipd, E_ipd, D_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE), 3 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLE2B_VITAL of DLE2B is for VITAL_ACT end for; end CFG_DLE2B_VITAL; ----- CELL DLE2C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLE2C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_E_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLE2C : entity is TRUE; end DLE2C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLE2C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLE2C_Q_tab : VitalStateTableType := ( ( L, L, L, x, x, L ), ( L, L, H, L, x, H ), ( H, x, x, L, x, S ), ( x, H, x, L, x, S ), ( x, x, x, H, x, L ), ( x, x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd OR E_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_posedge, TimingData => Tmkr_D_E_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_posedge, SetupLow => tsetup_D_E_noedge_posedge, HoldHigh => thold_D_E_noedge_posedge, HoldLow => thold_D_E_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd OR G_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_E_posedge, TimingData => Tmkr_CLR_E_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, Recovery => trecovery_CLR_E_negedge_posedge, Removal => thold_CLR_E_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_E_negedge, CheckEnabled => TO_X01(CLR_ipd OR G_ipd) /= '1', HeaderMsg => InstancePath &"/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(CLR_ipd OR E_ipd) /= '1', HeaderMsg => InstancePath &"/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLE2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_CLR_G_posedge or Pviol_E or Tviol_D_E_posedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLE2C_Q_tab, DataIn => ( G_ipd, E_ipd, D_ipd, CLR_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE), 3 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLE2C_VITAL of DLE2C is for VITAL_ACT end for; end CFG_DLE2C_VITAL; ----- CELL DLE3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLE3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_E_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_E_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLE3A : entity is TRUE; end DLE3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLE3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_E_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_E_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFP1_Q_tab : VitalStateTableType := ( ( L, L, L, H, x, L ), ( L, H, x, H, x, H ), ( H, x, L, x, x, S ), ( x, x, L, L, x, S ), ( x, x, H, x, x, H ), ( x, x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd OR (NOT E_ipd)) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_negedge, TimingData => Tmkr_D_E_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_negedge, SetupLow => tsetup_D_E_noedge_negedge, HoldHigh => thold_D_E_noedge_negedge, HoldLow => thold_D_E_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd OR (G_ipd)) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_negedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_E_negedge, TimingData => Tmkr_PRE_E_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, Recovery => trecovery_PRE_E_negedge_negedge, Removal => thold_PRE_E_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_E_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(PRE_ipd OR (G_ipd)) /= '1', HeaderMsg => InstancePath &"/DLE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(PRE_ipd OR (NOT E_ipd)) /= '1', HeaderMsg => InstancePath &"/DLE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLE3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_D_E_negedge or Tviol_PRE_G_posedge or Pviol_E or Pviol_PRE or Tviol_PRE_E_negedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFP1_Q_tab, DataIn => ( G_ipd, D_ipd, PRE_ipd, E_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE), 3 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLE3A_VITAL of DLE3A is for VITAL_ACT end for; end CFG_DLE3A_VITAL; ----- CELL DLE3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLE3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_E_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLE3B : entity is TRUE; end DLE3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLE3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLE3B_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, L ), ( L, L, H, x, x, H ), ( H, x, x, L, x, S ), ( x, H, x, L, x, S ), ( x, x, x, H, x, H ), ( x, x, x, U, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd OR E_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_posedge, TimingData => Tmkr_D_E_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_posedge, SetupLow => tsetup_D_E_noedge_posedge, HoldHigh => thold_D_E_noedge_posedge, HoldLow => thold_D_E_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd OR G_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_negedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_E_posedge, TimingData => Tmkr_PRE_E_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, Recovery => trecovery_PRE_E_negedge_posedge, Removal => thold_PRE_E_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_E_negedge, CheckEnabled => TO_X01(PRE_ipd OR G_ipd) /= '1', HeaderMsg => InstancePath &"/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(PRE_ipd OR E_ipd) /= '1', HeaderMsg => InstancePath &"/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLE3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Pviol_E or Pviol_PRE or Tviol_D_E_posedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLE3B_Q_tab, DataIn => ( G_ipd, E_ipd, D_ipd, PRE_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE), 3 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLE3B_VITAL of DLE3B is for VITAL_ACT end for; end CFG_DLE3B_VITAL; ----- CELL DLE3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLE3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_E_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_E_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLE3C : entity is TRUE; end DLE3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLE3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLE3C_Q_tab : VitalStateTableType := ( ( L, L, L, H, x, L ), ( L, L, H, x, x, H ), ( H, x, x, H, x, S ), ( x, H, x, H, x, S ), ( x, x, x, L, x, H ), ( x, x, x, U, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) OR E_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_posedge, TimingData => Tmkr_D_E_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_posedge, SetupLow => tsetup_D_E_noedge_posedge, HoldHigh => thold_D_E_noedge_posedge, HoldLow => thold_D_E_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) OR G_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_posedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_E_posedge, TimingData => Tmkr_PRE_E_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, Recovery => trecovery_PRE_E_posedge_posedge, Removal => thold_PRE_E_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_E_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) OR G_ipd ) /= '1', HeaderMsg => InstancePath &"/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) OR E_ipd ) /= '1', HeaderMsg => InstancePath &"/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLE3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Pviol_E or Pviol_PRE or Tviol_D_E_posedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLE3C_Q_tab, DataIn => ( G_ipd, E_ipd, D_ipd, PRE_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE), 3 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLE3C_VITAL of DLE3C is for VITAL_ACT end for; end CFG_DLE3C_VITAL; ----- CELL DLEA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLEA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLEA : entity is TRUE; end DLEA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLEA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd) -- timing check results VARIABLE Tviol_D_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DF1_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( L, H, H, x, H ), ( H, x, x, x, S ), ( x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_E_posedge, TimingData => Tmkr_D_E_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_posedge, SetupLow => tsetup_D_E_noedge_posedge, HoldHigh => thold_D_E_noedge_posedge, HoldLow => thold_D_E_noedge_posedge, CheckEnabled => TO_X01(G_ipd) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DLEA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01(NOT E_ipd) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DLEA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_E_negedge, CheckEnabled => TO_X01(G_ipd) /= '0', HeaderMsg => InstancePath &"/DLEA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(NOT E_ipd) /= '0', HeaderMsg => InstancePath &"/DLEA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_E_posedge or Tviol_D_G_negedge or Pviol_E or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DF1_Q_tab, DataIn => ( E_ipd, D_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLEA_VITAL of DLEA is for VITAL_ACT end for; end CFG_DLEA_VITAL; ----- CELL DLEB ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLEB is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_E_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_negedge : VitalDelayType := 0.000 ns; thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLEB : entity is TRUE; end DLEB; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLEB is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd) -- timing check results VARIABLE Tviol_D_E_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DF1_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( L, H, H, x, H ), ( H, x, x, x, S ), ( x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_E_negedge, TimingData => Tmkr_D_E_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_negedge, SetupLow => tsetup_D_E_noedge_negedge, HoldHigh => thold_D_E_noedge_negedge, HoldLow => thold_D_E_noedge_negedge, CheckEnabled => TO_X01(NOT G_ipd) /= '0', RefTransition => 'F', HeaderMsg => InstancePath & "/DLEB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(E_ipd) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DLEB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_E_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(NOT G_ipd) /= '0', HeaderMsg => InstancePath &"/DLEB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(E_ipd) /= '0', HeaderMsg => InstancePath &"/DLEB", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_E_negedge or Pviol_E or Tviol_D_G_posedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DF1_Q_tab, DataIn => ( G_ipd, D_ipd, E_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLEB_VITAL of DLEB is for VITAL_ACT end for; end CFG_DLEB_VITAL; ----- CELL DLEC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLEC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_E_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLEC : entity is TRUE; end DLEC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLEC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd, G_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_D_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLEC_Q_tab : VitalStateTableType := ( ( L, L, L, x, L ), ( L, L, H, x, H ), ( H, x, x, x, S ), ( x, H, x, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(NOT E_ipd) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DLEC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_D_E_posedge, TimingData => Tmkr_D_E_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_D_E_noedge_posedge, SetupLow => tsetup_D_E_noedge_posedge, HoldHigh => thold_D_E_noedge_posedge, HoldLow => thold_D_E_noedge_posedge, CheckEnabled => TO_X01(NOT G_ipd) /= '0', RefTransition => 'R', HeaderMsg => InstancePath & "/DLEC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_E_negedge, CheckEnabled => TO_X01(NOT G_ipd) /= '0', HeaderMsg => InstancePath &"/DLEC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(NOT E_ipd) /= '0', HeaderMsg => InstancePath &"/DLEC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Pviol_E or Tviol_D_E_posedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLEC_Q_tab, DataIn => ( G_ipd, E_ipd, D_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (E_ipd'last_event, tpd_E_Q, TRUE), 2 => (G_ipd'last_event, tpd_G_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLEC_VITAL of DLEC is for VITAL_ACT end for; end CFG_DLEC_VITAL; ----- CELL DLM ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLM is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_A_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_B_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_B_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_S_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_S_G_noedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLM : entity is TRUE; end DLM; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLM is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, G_ipd) -- timing check results VARIABLE Tviol_A_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLM_Q_tab : VitalStateTableType := ( ( L, L, x, H, x, L ), ( L, x, H, H, x, L ), ( H, H, x, H, x, H ), ( H, x, H, H, x, H ), ( x, L, L, H, x, L ), ( x, H, L, H, x, H ), ( x, x, x, L, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_G_negedge, TimingData => Tmkr_A_G_negedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_A_G_noedge_negedge, SetupLow => tsetup_A_G_noedge_negedge, HoldHigh => thold_A_G_noedge_negedge, HoldLow => thold_A_G_noedge_negedge, CheckEnabled => TO_X01( ( S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_G_negedge, TimingData => Tmkr_B_G_negedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_B_G_noedge_negedge, SetupLow => tsetup_B_G_noedge_negedge, HoldHigh => thold_B_G_noedge_negedge, HoldLow => thold_B_G_noedge_negedge, CheckEnabled => TO_X01( (NOT S_ipd ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_G_negedge, TimingData => Tmkr_S_G_negedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_S_G_noedge_negedge, SetupLow => tsetup_S_G_noedge_negedge, HoldHigh => thold_S_G_noedge_negedge, HoldLow => thold_S_G_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLM", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_G_negedge or Tviol_B_G_negedge or Tviol_S_G_negedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLM_Q_tab, DataIn => ( B_ipd, A_ipd, S_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Q, TRUE), 1 => (B_ipd'last_event, tpd_B_Q, TRUE), 2 => (S_ipd'last_event, tpd_S_Q, TRUE), 3 => (G_ipd'last_event, tpd_G_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLM_VITAL of DLM is for VITAL_ACT end for; end CFG_DLM_VITAL; ----- CELL DLM2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLM2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; G : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLM2A : entity is TRUE; end DLM2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLM2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, G_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_A_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLM2A_Q_tab : VitalStateTableType := ( ( L, L, L, x, x, x, L ), ( L, L, x, H, x, x, L ), ( L, H, H, x, L, x, H ), ( L, H, x, H, L, x, H ), ( L, x, L, L, x, x, L ), ( L, x, H, L, L, x, H ), ( H, x, x, x, L, x, S ), ( x, x, x, x, H, x, L ), ( x, x, x, x, U, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_G_posedge, TimingData => Tmkr_A_G_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_A_G_noedge_posedge, SetupLow => tsetup_A_G_noedge_posedge, HoldHigh => thold_A_G_noedge_posedge, HoldLow => thold_A_G_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd OR S_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLM2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_G_posedge, TimingData => Tmkr_B_G_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_B_G_noedge_posedge, SetupLow => tsetup_B_G_noedge_posedge, HoldHigh => thold_B_G_noedge_posedge, HoldLow => thold_B_G_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd OR (NOT S_ipd)) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLM2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_G_posedge, TimingData => Tmkr_S_G_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_S_G_noedge_posedge, SetupLow => tsetup_S_G_noedge_posedge, HoldHigh => thold_S_G_noedge_posedge, HoldLow => thold_S_G_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLM2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_G_posedge, TimingData => Tmkr_CLR_G_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_CLR_G_negedge_posedge, Removal => thold_CLR_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLM2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/DLM2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLM2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_G_posedge or Tviol_B_G_posedge or Tviol_CLR_G_posedge or Tviol_S_G_posedge or Pviol_CLR or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLM2A_Q_tab, DataIn => ( G_ipd, B_ipd, A_ipd, S_ipd, CLR_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Q, TRUE), 1 => (B_ipd'last_event, tpd_B_Q, TRUE), 2 => (S_ipd'last_event, tpd_S_Q, TRUE), 3 => (G_ipd'last_event, tpd_G_Q, TRUE), 4 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLM2A_VITAL of DLM2A is for VITAL_ACT end for; end CFG_DLM2A_VITAL; ----- CELL DLMA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLMA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_G_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLMA : entity is TRUE; end DLMA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLMA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, G_ipd) -- timing check results VARIABLE Tviol_A_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLMA_Q_tab : VitalStateTableType := ( ( L, L, L, x, x, L ), ( L, L, x, H, x, L ), ( L, H, H, x, x, H ), ( L, H, x, H, x, H ), ( L, x, L, L, x, L ), ( L, x, H, L, x, H ), ( H, x, x, x, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_G_posedge, TimingData => Tmkr_A_G_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_A_G_noedge_posedge, SetupLow => tsetup_A_G_noedge_posedge, HoldHigh => thold_A_G_noedge_posedge, HoldLow => thold_A_G_noedge_posedge, CheckEnabled => TO_X01( ( S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLMA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_G_posedge, TimingData => Tmkr_B_G_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_B_G_noedge_posedge, SetupLow => tsetup_B_G_noedge_posedge, HoldHigh => thold_B_G_noedge_posedge, HoldLow => thold_B_G_noedge_posedge, CheckEnabled => TO_X01( (NOT S_ipd ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLMA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_G_posedge, TimingData => Tmkr_S_G_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_S_G_noedge_posedge, SetupLow => tsetup_S_G_noedge_posedge, HoldHigh => thold_S_G_noedge_posedge, HoldLow => thold_S_G_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLMA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLMA", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_G_posedge or Tviol_B_G_posedge or Tviol_S_G_posedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLMA_Q_tab, DataIn => ( G_ipd, B_ipd, A_ipd, S_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Q, TRUE), 1 => (B_ipd'last_event, tpd_B_Q, TRUE), 2 => (S_ipd'last_event, tpd_S_Q, TRUE), 3 => (G_ipd'last_event, tpd_G_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLMA_VITAL of DLMA is for VITAL_ACT end for; end CFG_DLMA_VITAL; ----- CELL DLME1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLME1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_E_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_A_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_A_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_A_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_B_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_B_E_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_S_E_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_S_E_noedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_E_negedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; E : in STD_ULOGIC; G : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLME1A : entity is TRUE; end DLME1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLME1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); VitalWireDelay (E_ipd, E, tipd_E); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd, E_ipd, G_ipd) -- timing check results VARIABLE Tviol_A_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_A_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_A_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_B_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_B_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_S_E_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_S_E_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_E : STD_ULOGIC := '0'; VARIABLE PInfo_E : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLME1A_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, x, L ), ( L, L, L, x, H, x, L ), ( L, L, H, H, x, x, H ), ( L, L, H, x, H, x, H ), ( L, L, x, L, L, x, L ), ( L, L, x, H, L, x, H ), ( H, x, x, x, x, x, S ), ( x, H, x, x, x, x, S )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_A_G_posedge, TimingData => Tmkr_A_G_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_A_G_noedge_posedge, SetupLow => tsetup_A_G_noedge_posedge, HoldHigh => thold_A_G_noedge_posedge, HoldLow => thold_A_G_noedge_posedge, CheckEnabled => TO_X01(E_ipd OR S_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_A_E_posedge, TimingData => Tmkr_A_E_posedge, TestSignal => A_ipd, TestSignalName => "A", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_A_E_noedge_posedge, SetupLow => tsetup_A_E_noedge_posedge, HoldHigh => thold_A_E_noedge_posedge, HoldLow => thold_A_E_noedge_posedge, CheckEnabled => TO_X01(S_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_G_posedge, TimingData => Tmkr_B_G_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_B_G_noedge_posedge, SetupLow => tsetup_B_G_noedge_posedge, HoldHigh => thold_B_G_noedge_posedge, HoldLow => thold_B_G_noedge_posedge, CheckEnabled => TO_X01(E_ipd OR (NOT S_ipd)) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_B_E_posedge, TimingData => Tmkr_B_E_posedge, TestSignal => B_ipd, TestSignalName => "B", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_B_E_noedge_posedge, SetupLow => tsetup_B_E_noedge_posedge, HoldHigh => thold_B_E_noedge_posedge, HoldLow => thold_B_E_noedge_posedge, CheckEnabled => TO_X01(NOT S_ipd) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_G_posedge, TimingData => Tmkr_S_G_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_S_G_noedge_posedge, SetupLow => tsetup_S_G_noedge_posedge, HoldHigh => thold_S_G_noedge_posedge, HoldLow => thold_S_G_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_S_E_posedge, TimingData => Tmkr_S_E_posedge, TestSignal => S_ipd, TestSignalName => "S", TestDelay => 0 ns, RefSignal => E_ipd, RefSignalName => "E", RefDelay => 0 ns, SetupHigh => tsetup_S_E_noedge_posedge, SetupLow => tsetup_S_E_noedge_posedge, HoldHigh => thold_S_E_noedge_posedge, HoldLow => thold_S_E_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_E, PeriodData => PInfo_E, TestSignal => E_ipd, TestSignalName => "E", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_E_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLME1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_A_G_posedge or Pviol_E or Tviol_A_E_posedge or Tviol_B_G_posedge or Tviol_B_E_posedge or Tviol_S_G_posedge or Tviol_S_E_posedge or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLME1A_Q_tab, DataIn => ( G_ipd, E_ipd, B_ipd, A_ipd, S_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Q, TRUE), 1 => (B_ipd'last_event, tpd_B_Q, TRUE), 2 => (S_ipd'last_event, tpd_S_Q, TRUE), 3 => (E_ipd'last_event, tpd_E_Q, TRUE), 4 => (G_ipd'last_event, tpd_G_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLME1A_VITAL of DLME1A is for VITAL_ACT end for; end CFG_DLME1A_VITAL; ----- CELL DLP1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLP1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLP1 : entity is TRUE; end DLP1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLP1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLP1_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( H, x, H, x, H ), ( x, L, L, x, S ), ( x, H, x, x, H ), ( x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_negedge, TimingData => Tmkr_PRE_G_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_negedge_negedge, Removal => thold_PRE_G_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DLP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLP1", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_PRE_G_negedge or Pviol_PRE or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLP1_Q_tab, DataIn => ( D_ipd, PRE_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLP1_VITAL of DLP1 is for VITAL_ACT end for; end CFG_DLP1_VITAL; ----- CELL DLP1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLP1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLP1A : entity is TRUE; end DLP1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLP1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLP1A_Q_tab : VitalStateTableType := ( ( L, L, L, x, L ), ( L, H, x, x, H ), ( H, x, L, x, S ), ( x, x, H, x, H ), ( x, x, U, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_negedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/DLP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLP1A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Pviol_PRE or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLP1A_Q_tab, DataIn => ( G_ipd, D_ipd, PRE_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLP1A_VITAL of DLP1A is for VITAL_ACT end for; end CFG_DLP1A_VITAL; ----- CELL DLP1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLP1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLP1B : entity is TRUE; end DLP1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLP1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLP1B_Q_tab : VitalStateTableType := ( ( L, H, H, x, L ), ( H, x, H, x, H ), ( x, L, x, x, H ), ( x, H, L, x, S ), ( x, U, x, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_negedge, TimingData => Tmkr_PRE_G_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_posedge_negedge, Removal => thold_PRE_G_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DLP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLP1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_PRE_G_negedge or Pviol_PRE or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLP1B_Q_tab, DataIn => ( D_ipd, PRE_ipd, G_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLP1B_VITAL of DLP1B is for VITAL_ACT end for; end CFG_DLP1B_VITAL; ----- CELL DLP1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLP1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLP1C : entity is TRUE; end DLP1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLP1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLP1C_Q_tab : VitalStateTableType := ( ( L, L, H, x, L ), ( L, H, x, x, H ), ( H, x, H, x, S ), ( x, x, L, x, H ), ( x, x, U, H, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_posedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DLP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLP1C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Pviol_PRE or Pviol_G; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DLP1C_Q_tab, DataIn => ( G_ipd, D_ipd, PRE_ipd)); Q_zd := Violation XOR Q_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Q, TRUE), 1 => (G_ipd'last_event, tpd_G_Q, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLP1C_VITAL of DLP1C is for VITAL_ACT end for; end CFG_DLP1C_VITAL; ----- CELL DLP1D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLP1D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_G_negedge : VitalDelayType := 0.000 ns; tpw_G_posedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLP1D : entity is TRUE; end DLP1D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLP1D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLP1D_QN_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, L, H, x, H ), ( H, x, L, x, S ), ( x, H, H, x, L ), ( U, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_negedge, TimingData => Tmkr_D_G_negedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_negedge, SetupLow => tsetup_D_G_noedge_negedge, HoldHigh => thold_D_G_noedge_negedge, HoldLow => thold_D_G_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/DLP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_negedge, TimingData => Tmkr_PRE_G_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_posedge_negedge, Removal => thold_PRE_G_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/DLP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_negedge, PulseWidthHigh => tpw_G_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DLP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLP1D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_negedge or Tviol_PRE_G_negedge or Pviol_PRE or Pviol_G; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DLP1D_QN_tab, DataIn => ( PRE_ipd, D_ipd, G_ipd)); QN_zd := Violation XOR QN_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (D_ipd'last_event, tpd_D_QN, TRUE), 1 => (G_ipd'last_event, tpd_G_QN, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLP1D_VITAL of DLP1D is for VITAL_ACT end for; end CFG_DLP1D_VITAL; ----- CELL DLP1E ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity DLP1E is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_G_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_QN : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_D_G_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_D_G_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_G_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_G_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_G_posedge : VitalDelayType := 0.000 ns; tpw_G_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; G : in STD_ULOGIC; PRE : in STD_ULOGIC; QN : out STD_ULOGIC); attribute VITAL_LEVEL0 of DLP1E : entity is TRUE; end DLP1E; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of DLP1E is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (G_ipd, G, tipd_G); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, G_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_D_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_D_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_G_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_G_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_G : STD_ULOGIC := '0'; VARIABLE PInfo_G : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_QN : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS QN_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE QN_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DLP1E_QN_tab : VitalStateTableType := ( ( L, x, x, x, L ), ( H, L, L, x, H ), ( H, H, x, x, S ), ( x, L, H, x, L ), ( U, x, x, L, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_D_G_posedge, TimingData => Tmkr_D_G_posedge, TestSignal => D_ipd, TestSignalName => "D", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, SetupHigh => tsetup_D_G_noedge_posedge, SetupLow => tsetup_D_G_noedge_posedge, HoldHigh => thold_D_G_noedge_posedge, HoldLow => thold_D_G_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/DLP1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_G_posedge, TimingData => Tmkr_PRE_G_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => G_ipd, RefSignalName => "G", RefDelay => 0 ns, Recovery => trecovery_PRE_G_posedge_posedge, Removal => thold_PRE_G_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/DLP1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_G, PeriodData => PInfo_G, TestSignal => G_ipd, TestSignalName => "G", TestDelay => 0 ns, Period => tperiod_G_posedge, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_G_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/DLP1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/DLP1E", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_D_G_posedge or Tviol_PRE_G_posedge or Pviol_PRE or Pviol_G; VitalStateTable( Result => QN_zd, PreviousDataIn => PrevData_QN, StateTable => DLP1E_QN_tab, DataIn => ( PRE_ipd, G_ipd, D_ipd)); QN_zd := Violation XOR QN_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => QN, GlitchData => QN_GlitchData, OutSignalName => "QN", OutTemp => QN_zd, Paths => (0 => (D_ipd'last_event, tpd_D_QN, TRUE), 1 => (G_ipd'last_event, tpd_G_QN, TRUE), 2 => (PRE_ipd'last_event, tpd_PRE_QN, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_DLP1E_VITAL of DLP1E is for VITAL_ACT end for; end CFG_DLP1E_VITAL; ----- CELL FA1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity FA1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); attribute VITAL_LEVEL0 of FA1 : entity is TRUE; end FA1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of FA1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL CI_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (CI_ipd, CI, tipd_CI); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, CI_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS CO_zd : STD_LOGIC is Results(1); ALIAS S_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE CO_GlitchData : VitalGlitchDataType; VARIABLE S_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- CO_zd := ((B_ipd) AND (A_ipd)) OR ((A_ipd) AND (CI_ipd)) OR ((B_ipd) AND (CI_ipd)); S_zd := (A_ipd) XOR (CI_ipd) XOR (B_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (A_ipd'last_event, tpd_A_CO, TRUE), 1 => (B_ipd'last_event, tpd_B_CO, TRUE), 2 => (CI_ipd'last_event, tpd_CI_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (A_ipd'last_event, tpd_A_S, TRUE), 1 => (B_ipd'last_event, tpd_B_S, TRUE), 2 => (CI_ipd'last_event, tpd_CI_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_FA1_VITAL of FA1 is for VITAL_ACT end for; end CFG_FA1_VITAL; ----- CELL FA1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity FA1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); attribute VITAL_LEVEL0 of FA1A : entity is TRUE; end FA1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of FA1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL CI_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (CI_ipd, CI, tipd_CI); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, CI_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS S_zd : STD_LOGIC is Results(1); ALIAS CO_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE S_GlitchData : VitalGlitchDataType; VARIABLE CO_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- S_zd := (((NOT A_ipd)) AND ((((NOT B_ipd)) AND (A_ipd)) OR (((NOT B_ipd)) AND (CI_ipd) AND ((NOT A_ipd))) OR ((CI_ipd) AND (B_ipd) AND (A_ipd))) AND (CI_ipd)) OR (((NOT A_ipd)) AND (B_ipd) AND ((NOT CI_ipd))) OR ((A_ipd) AND ((((NOT B_ipd)) AND (A_ipd)) OR (((NOT B_ipd)) AND (CI_ipd) AND ((NOT A_ipd))) OR ((CI_ipd) AND (B_ipd) AND (A_ipd))) AND ((NOT CI_ipd))) OR ((A_ipd) AND (B_ipd) AND (CI_ipd)); CO_zd := (((NOT B_ipd)) AND (A_ipd)) OR (((NOT B_ipd)) AND (CI_ipd)) OR ((CI_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_S, TRUE), 1 => (B_ipd'last_event, tpd_B_S, TRUE), 2 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_CO, TRUE), 1 => (B_ipd'last_event, tpd_B_CO, TRUE), 2 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_FA1A_VITAL of FA1A is for VITAL_ACT end for; end CFG_FA1A_VITAL; ----- CELL FA1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity FA1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); attribute VITAL_LEVEL0 of FA1B : entity is TRUE; end FA1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of FA1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL CI_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (CI_ipd, CI, tipd_CI); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, CI_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS S_zd : STD_LOGIC is Results(1); ALIAS CO_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE S_GlitchData : VitalGlitchDataType; VARIABLE CO_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- S_zd := ((((((CI_ipd) AND ((NOT B_ipd)) AND (A_ipd)) OR ((((CI_ipd) AND (B_ipd)) OR ((NOT B_ipd))) AND ((NOT A_ipd)))) AND (CI_ipd)) OR ((B_ipd) AND ((NOT CI_ipd)))) AND (A_ipd)) OR ((((B_ipd) AND (CI_ipd)) OR ((((CI_ipd) AND ((NOT B_ipd)) AND (A_ipd)) OR ((((CI_ipd) AND (B_ipd)) OR ((NOT B_ipd))) AND ((NOT A_ipd)))) AND ((NOT CI_ipd)))) AND ((NOT A_ipd))); CO_zd := ((CI_ipd) AND ((NOT B_ipd))) OR ((CI_ipd) AND ((NOT A_ipd))) OR (((NOT B_ipd)) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_S, TRUE), 1 => (B_ipd'last_event, tpd_B_S, TRUE), 2 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_CO, TRUE), 1 => (B_ipd'last_event, tpd_B_CO, TRUE), 2 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_FA1B_VITAL of FA1B is for VITAL_ACT end for; end CFG_FA1B_VITAL; ----- CELL FA2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity FA2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CI_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CI_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A1_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A0_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_A1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CI : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; B : in STD_ULOGIC; CI : in STD_ULOGIC; S : out STD_ULOGIC; CO : out STD_ULOGIC); attribute VITAL_LEVEL0 of FA2A : entity is TRUE; end FA2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of FA2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A0_ipd : STD_ULOGIC := 'X'; SIGNAL A1_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL CI_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A0_ipd, A0, tipd_A0); VitalWireDelay (A1_ipd, A1, tipd_A1); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (CI_ipd, CI, tipd_CI); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A0_ipd, A1_ipd, B_ipd, CI_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS S_zd : STD_LOGIC is Results(1); ALIAS CO_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE S_GlitchData : VitalGlitchDataType; VARIABLE CO_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- S_zd := (((NOT ((A1_ipd) OR (A0_ipd)))) AND ((((A1_ipd) OR (A0_ipd)) AND ((NOT B_ipd))) OR (((NOT B_ipd)) AND (CI_ipd) AND ((NOT ((A1_ipd) OR (A0_ipd))))) OR ((CI_ipd) AND (B_ipd) AND ((A1_ipd) OR (A0_ipd)))) AND (CI_ipd)) OR (((NOT ((A1_ipd) OR (A0_ipd)))) AND (B_ipd) AND ((NOT CI_ipd))) OR (((A1_ipd) OR (A0_ipd)) AND ((((A1_ipd) OR (A0_ipd)) AND ((NOT B_ipd))) OR (((NOT B_ipd)) AND (CI_ipd) AND ((NOT ((A1_ipd) OR (A0_ipd))))) OR ((CI_ipd) AND (B_ipd) AND ((A1_ipd) OR (A0_ipd)))) AND ((NOT CI_ipd))) OR (((A1_ipd) OR (A0_ipd)) AND (B_ipd) AND (CI_ipd)); --CO_zd := -- (((A1_ipd) OR (A0_ipd)) AND ((NOT B_ipd))) OR (((NOT B_ipd)) AND -- (CI_ipd) AND ((NOT ((A1_ipd) OR (A0_ipd))))) OR ((CI_ipd) AND -- (B_ipd) AND ((A1_ipd) OR (A0_ipd))); CO_zd := (((A1_ipd) AND (NOT B_ipd)) OR ((A0_ipd) AND (NOT B_ipd)) OR ((A0_ipd) AND (CI_ipd)) OR ((A1_ipd) AND (CI_ipd)) OR ((NOT B_ipd) AND (CI_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_S, TRUE), 1 => (B_ipd'last_event, tpd_B_S, TRUE), 2 => (A1_ipd'last_event, tpd_A1_S, TRUE), 3 => (A0_ipd'last_event, tpd_A0_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (CI_ipd'last_event, tpd_CI_CO, TRUE), 1 => (B_ipd'last_event, tpd_B_CO, TRUE), 2 => (A1_ipd'last_event, tpd_A1_CO, TRUE), 3 => (A0_ipd'last_event, tpd_A0_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_FA2A_VITAL of FA2A is for VITAL_ACT end for; end CFG_FA2A_VITAL; ----- CELL GAND2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GAND2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GAND2 : entity is TRUE; end GAND2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of GAND2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (G_ipd) AND (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GAND2_VITAL of GAND2 is for VITAL_ACT end for; end CFG_GAND2_VITAL; ----- CELL GMX4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GMX4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0 : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GMX4 : entity is TRUE; end GMX4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of GMX4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S0_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S0_ipd, S0, tipd_S0); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, D3_ipd, S0_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalMUX (data => (D3_ipd, D1_ipd, D2_ipd, D0_ipd), dselect => (S0_ipd, G_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (S0_ipd'last_event, tpd_S0_Y, TRUE), 2 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 3 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 4 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 5 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GMX4_VITAL of GMX4 is for VITAL_ACT end for; end CFG_GMX4_VITAL; ----- CELL GNAND2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GNAND2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GNAND2 : entity is TRUE; end GNAND2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of GNAND2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((G_ipd) AND (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GNAND2_VITAL of GNAND2 is for VITAL_ACT end for; end CFG_GNAND2_VITAL; ----- CELL GND ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GND is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True); port( Y : out STD_ULOGIC := '0'); attribute VITAL_LEVEL0 of GND : entity is TRUE; end GND; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of GND is attribute VITAL_LEVEL0 of VITAL_ACT : architecture is TRUE; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin -- empty end block; -------------------- -- BEHAVIOR SECTION -------------------- Y <= '0'; end VITAL_ACT; configuration CFG_GND_VITAL of GND is for VITAL_ACT end for; end CFG_GND_VITAL; ----- CELL GNOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GNOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GNOR2 : entity is TRUE; end GNOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of GNOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((G_ipd) OR (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GNOR2_VITAL of GNOR2 is for VITAL_ACT end for; end CFG_GNOR2_VITAL; ----- CELL GOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GOR2 : entity is TRUE; end GOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of GOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (G_ipd) OR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GOR2_VITAL of GOR2 is for VITAL_ACT end for; end CFG_GOR2_VITAL; ----- CELL GXOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity GXOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_G_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_G : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; G : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of GXOR2 : entity is TRUE; end GXOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of GXOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL G_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (G_ipd, G, tipd_G); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, G_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (G_ipd) XOR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (G_ipd'last_event, tpd_G_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_GXOR2_VITAL of GXOR2 is for VITAL_ACT end for; end CFG_GXOR2_VITAL; ----- CELL HA1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity HA1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); attribute VITAL_LEVEL0 of HA1 : entity is TRUE; end HA1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of HA1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS CO_zd : STD_LOGIC is Results(1); ALIAS S_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE CO_GlitchData : VitalGlitchDataType; VARIABLE S_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- CO_zd := (B_ipd) AND (A_ipd); S_zd := (B_ipd) XOR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (B_ipd'last_event, tpd_B_CO, TRUE), 1 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (B_ipd'last_event, tpd_B_S, TRUE), 1 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_HA1_VITAL of HA1 is for VITAL_ACT end for; end CFG_HA1_VITAL; ----- CELL HA1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity HA1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); attribute VITAL_LEVEL0 of HA1A : entity is TRUE; end HA1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of HA1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS CO_zd : STD_LOGIC is Results(1); ALIAS S_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE CO_GlitchData : VitalGlitchDataType; VARIABLE S_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- CO_zd := (B_ipd) AND ((NOT A_ipd)); S_zd := (NOT ((B_ipd) XOR (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (B_ipd'last_event, tpd_B_CO, TRUE), 1 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (B_ipd'last_event, tpd_B_S, TRUE), 1 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_HA1A_VITAL of HA1A is for VITAL_ACT end for; end CFG_HA1A_VITAL; ----- CELL HA1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity HA1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); attribute VITAL_LEVEL0 of HA1B : entity is TRUE; end HA1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of HA1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS CO_zd : STD_LOGIC is Results(1); ALIAS S_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE CO_GlitchData : VitalGlitchDataType; VARIABLE S_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- CO_zd := (NOT ((B_ipd) AND (A_ipd))); S_zd := (NOT ((B_ipd) XOR (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (B_ipd'last_event, tpd_B_CO, TRUE), 1 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (B_ipd'last_event, tpd_B_S, TRUE), 1 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_HA1B_VITAL of HA1B is for VITAL_ACT end for; end CFG_HA1B_VITAL; ----- CELL HA1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity HA1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_CO : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_S : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; CO : out STD_ULOGIC; S : out STD_ULOGIC); attribute VITAL_LEVEL0 of HA1C : entity is TRUE; end HA1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of HA1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X'); ALIAS CO_zd : STD_LOGIC is Results(1); ALIAS S_zd : STD_LOGIC is Results(2); -- output glitch detection variables VARIABLE CO_GlitchData : VitalGlitchDataType; VARIABLE S_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- CO_zd := (NOT ((B_ipd) AND (A_ipd))); S_zd := (B_ipd) XOR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => CO, GlitchData => CO_GlitchData, OutSignalName => "CO", OutTemp => CO_zd, Paths => (0 => (B_ipd'last_event, tpd_B_CO, TRUE), 1 => (A_ipd'last_event, tpd_A_CO, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => S, GlitchData => S_GlitchData, OutSignalName => "S", OutTemp => S_zd, Paths => (0 => (B_ipd'last_event, tpd_B_S, TRUE), 1 => (A_ipd'last_event, tpd_A_S, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_HA1C_VITAL of HA1C is for VITAL_ACT end for; end CFG_HA1C_VITAL; ----- CELL INBUF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity INBUF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PAD_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_PAD : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of INBUF : entity is TRUE; end INBUF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of INBUF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL PAD_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (PAD_ipd, PAD, tipd_PAD); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (PAD_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := TO_X01(PAD_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (PAD_ipd'last_event, tpd_PAD_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_INBUF_VITAL of INBUF is for VITAL_ACT end for; end CFG_INBUF_VITAL; ----- CELL INV ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity INV is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of INV : entity is TRUE; end INV; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of INV is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_INV_VITAL of INV is for VITAL_ACT end for; end CFG_INV_VITAL; ----- CELL INVA ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity INVA is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of INVA : entity is TRUE; end INVA; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of INVA is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_INVA_VITAL of INVA is for VITAL_ACT end for; end CFG_INVA_VITAL; ----- CELL INVD ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity INVD is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of INVD : entity is TRUE; end INVD; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of INVD is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_INVD_VITAL of INVD is for VITAL_ACT end for; end CFG_INVD_VITAL; ----- CELL JKF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF : entity is TRUE; end JKF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of JKF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_J_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_posedge, TimingData => Tmkr_J_CLK_posedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_posedge, SetupLow => tsetup_J_CLK_noedge_posedge, HoldHigh => thold_J_CLK_noedge_posedge, HoldLow => thold_J_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/JKF", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_posedge, TimingData => Tmkr_K_CLK_posedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_posedge, SetupLow => tsetup_K_CLK_noedge_posedge, HoldHigh => thold_K_CLK_noedge_posedge, HoldLow => thold_K_CLK_noedge_posedge, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/JKF", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_posedge or Tviol_K_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE1B_Q_tab, DataIn => ( CLK_delayed, K_delayed, J_delayed, Q_zd, CLK_ipd)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF_VITAL of JKF is for VITAL_ACT end for; end CFG_JKF_VITAL; ----- CELL JKF1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF1B : entity is TRUE; end JKF1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of JKF1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd) -- timing check results VARIABLE Tviol_J_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_negedge, TimingData => Tmkr_J_CLK_negedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_negedge, SetupLow => tsetup_J_CLK_noedge_negedge, HoldHigh => thold_J_CLK_noedge_negedge, HoldLow => thold_J_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/JKF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_negedge, TimingData => Tmkr_K_CLK_negedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_negedge, SetupLow => tsetup_K_CLK_noedge_negedge, HoldHigh => thold_K_CLK_noedge_negedge, HoldLow => thold_K_CLK_noedge_negedge, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/JKF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF1B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_negedge or Tviol_K_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE1B_Q_tab, DataIn => ( CLK_ipd, K_delayed, J_delayed, Q_zd, CLK_delayed)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF1B_VITAL of JKF1B is for VITAL_ACT end for; end CFG_JKF1B_VITAL; ----- CELL JKF2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF2A : entity is TRUE; end JKF2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_J_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L ), ( U, x, x, x, L, x, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_posedge, TimingData => Tmkr_J_CLK_posedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_posedge, SetupLow => tsetup_J_CLK_noedge_posedge, HoldHigh => thold_J_CLK_noedge_posedge, HoldLow => thold_J_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_posedge, TimingData => Tmkr_K_CLK_posedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_posedge, SetupLow => tsetup_K_CLK_noedge_posedge, HoldHigh => thold_K_CLK_noedge_posedge, HoldLow => thold_K_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/JKF2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/JKF2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF2A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_posedge or Tviol_CLR_CLK_posedge or Tviol_K_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3C_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, K_delayed, J_delayed, Q_zd, CLK_ipd)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF2A_VITAL of JKF2A is for VITAL_ACT end for; end CFG_JKF2A_VITAL; ----- CELL JKF2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF2B : entity is TRUE; end JKF2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_J_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE3C_Q_tab : VitalStateTableType := ( ( L, x, x, x, x, x, x, L ), ( H, L, H, H, x, H, x, H ), ( H, L, H, x, H, H, x, H ), ( H, L, x, H, L, H, x, H ), ( H, H, x, x, x, x, x, S ), ( H, x, x, x, x, L, x, S ), ( x, L, L, L, x, H, x, L ), ( x, L, L, x, H, H, x, L ), ( x, L, x, L, L, H, x, L ), ( U, x, x, x, L, x, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_negedge, TimingData => Tmkr_J_CLK_negedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_negedge, SetupLow => tsetup_J_CLK_noedge_negedge, HoldHigh => thold_J_CLK_noedge_negedge, HoldLow => thold_J_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_negedge, TimingData => Tmkr_K_CLK_negedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_negedge, SetupLow => tsetup_K_CLK_noedge_negedge, HoldHigh => thold_K_CLK_noedge_negedge, HoldLow => thold_K_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/JKF2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/JKF2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF2B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_negedge or Tviol_K_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE3C_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, K_delayed, J_delayed, Q_zd, CLK_delayed)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF2B_VITAL of JKF2B is for VITAL_ACT end for; end CFG_JKF2B_VITAL; ----- CELL JKF2C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF2C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF2C : entity is TRUE; end JKF2C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF2C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_J_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM3_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, x, L ), ( L, L, x, H, H, x, x, L ), ( L, H, H, x, H, L, x, H ), ( L, H, x, H, H, L, x, H ), ( L, x, L, L, H, x, x, L ), ( L, x, H, L, H, L, x, H ), ( H, x, x, x, x, L, x, S ), ( x, x, x, x, L, L, x, S ), ( x, x, x, x, x, H, x, L ), ( x, x, x, L, x, U, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_posedge, TimingData => Tmkr_J_CLK_posedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_posedge, SetupLow => tsetup_J_CLK_noedge_posedge, HoldHigh => thold_J_CLK_noedge_posedge, HoldLow => thold_J_CLK_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_posedge, TimingData => Tmkr_K_CLK_posedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_posedge, SetupLow => tsetup_K_CLK_noedge_posedge, HoldHigh => thold_K_CLK_noedge_posedge, HoldLow => thold_K_CLK_noedge_posedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_negedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/JKF2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/JKF2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF2C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_posedge or Tviol_CLR_CLK_posedge or Tviol_K_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM3_Q_tab, DataIn => ( CLK_delayed, K_delayed, J_delayed, Q_zd, CLK_ipd, CLR_ipd)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF2C_VITAL of JKF2C is for VITAL_ACT end for; end CFG_JKF2C_VITAL; ----- CELL JKF2D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF2D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLR_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF2D : entity is TRUE; end JKF2D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF2D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_J_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM3_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, x, x, L ), ( L, L, x, H, H, x, x, L ), ( L, H, H, x, H, L, x, H ), ( L, H, x, H, H, L, x, H ), ( L, x, L, L, H, x, x, L ), ( L, x, H, L, H, L, x, H ), ( H, x, x, x, x, L, x, S ), ( x, x, x, x, L, L, x, S ), ( x, x, x, x, x, H, x, L ), ( x, x, x, L, x, U, x, L )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_negedge, TimingData => Tmkr_J_CLK_negedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_negedge, SetupLow => tsetup_J_CLK_noedge_negedge, HoldHigh => thold_J_CLK_noedge_negedge, HoldLow => thold_J_CLK_noedge_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_negedge, TimingData => Tmkr_K_CLK_negedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_negedge, SetupLow => tsetup_K_CLK_noedge_negedge, HoldHigh => thold_K_CLK_noedge_negedge, HoldLow => thold_K_CLK_noedge_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_negedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/JKF2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(CLR_ipd ) /= '1', HeaderMsg => InstancePath &"/JKF2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_CLR_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF2D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_negedge or Tviol_K_CLK_negedge or Tviol_CLR_CLK_negedge or Pviol_CLR or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM3_Q_tab, DataIn => ( CLK_ipd, K_delayed, J_delayed, Q_zd, CLK_delayed, CLR_ipd)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF2D_VITAL of JKF2D is for VITAL_ACT end for; end CFG_JKF2D_VITAL; ----- CELL JKF3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF3A : entity is TRUE; end JKF3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_J_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM4A_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, H, H, x, x, H, x, H ), ( L, H, x, H, x, H, x, H ), ( L, x, L, L, H, H, x, L ), ( L, x, H, L, x, H, x, H ), ( H, x, x, x, H, x, x, S ), ( x, x, x, x, L, x, x, H ), ( x, x, x, x, H, L, x, S ), ( x, x, x, H, U, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_posedge, TimingData => Tmkr_J_CLK_posedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_posedge, SetupLow => tsetup_J_CLK_noedge_posedge, HoldHigh => thold_J_CLK_noedge_posedge, HoldLow => thold_J_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_posedge, TimingData => Tmkr_K_CLK_posedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_posedge, SetupLow => tsetup_K_CLK_noedge_posedge, HoldHigh => thold_K_CLK_noedge_posedge, HoldLow => thold_K_CLK_noedge_posedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/JKF3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/JKF3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF3A", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_posedge or Pviol_PRE or Tviol_K_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM4A_Q_tab, DataIn => ( CLK_delayed, K_delayed, J_delayed, Q_zd, PRE_ipd, CLK_ipd)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF3A_VITAL of JKF3A is for VITAL_ACT end for; end CFG_JKF3A_VITAL; ----- CELL JKF3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_PRE_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF3B : entity is TRUE; end JKF3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_J_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFM4A_Q_tab : VitalStateTableType := ( ( L, L, L, x, H, H, x, L ), ( L, L, x, H, H, H, x, L ), ( L, H, H, x, x, H, x, H ), ( L, H, x, H, x, H, x, H ), ( L, x, L, L, H, H, x, L ), ( L, x, H, L, x, H, x, H ), ( H, x, x, x, H, x, x, S ), ( x, x, x, x, L, x, x, H ), ( x, x, x, x, H, L, x, S ), ( x, x, x, H, U, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_negedge, TimingData => Tmkr_J_CLK_negedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_negedge, SetupLow => tsetup_J_CLK_noedge_negedge, HoldHigh => thold_J_CLK_noedge_negedge, HoldLow => thold_J_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_negedge, TimingData => Tmkr_K_CLK_negedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_negedge, SetupLow => tsetup_K_CLK_noedge_negedge, HoldHigh => thold_K_CLK_noedge_negedge, HoldLow => thold_K_CLK_noedge_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_posedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/JKF3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01((NOT PRE_ipd) ) /= '1', HeaderMsg => InstancePath &"/JKF3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_PRE_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF3B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_negedge or Tviol_K_CLK_negedge or Pviol_PRE or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFM4A_Q_tab, DataIn => ( CLK_ipd, K_delayed, J_delayed, Q_zd, PRE_ipd, CLK_delayed)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF3B_VITAL of JKF3B is for VITAL_ACT end for; end CFG_JKF3B_VITAL; ----- CELL JKF3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF3C : entity is TRUE; end JKF3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_J_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE4B_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, H, x, L ), ( L, L, L, x, H, H, x, L ), ( L, L, x, L, L, H, x, L ), ( L, x, H, H, x, H, x, H ), ( L, x, H, x, H, H, x, H ), ( L, x, x, H, L, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H ), ( x, U, x, x, H, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_posedge, TimingData => Tmkr_J_CLK_posedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_posedge, SetupLow => tsetup_J_CLK_noedge_posedge, HoldHigh => thold_J_CLK_noedge_posedge, HoldLow => thold_J_CLK_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_posedge, TimingData => Tmkr_K_CLK_posedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_posedge, SetupLow => tsetup_K_CLK_noedge_posedge, HoldHigh => thold_K_CLK_noedge_posedge, HoldLow => thold_K_CLK_noedge_posedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKF3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/JKF3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/JKF3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF3C", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_posedge or Pviol_PRE or Tviol_K_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE4B_Q_tab, DataIn => ( CLK_delayed, PRE_ipd, K_delayed, J_delayed, Q_zd, CLK_ipd)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF3C_VITAL of JKF3C is for VITAL_ACT end for; end CFG_JKF3C_VITAL; ----- CELL JKF3D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF3D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF3D : entity is TRUE; end JKF3D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF3D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, PRE_ipd) -- timing check results VARIABLE Tviol_J_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 5); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT DFE4B_Q_tab : VitalStateTableType := ( ( L, L, L, L, x, H, x, L ), ( L, L, L, x, H, H, x, L ), ( L, L, x, L, L, H, x, L ), ( L, x, H, H, x, H, x, H ), ( L, x, H, x, H, H, x, H ), ( L, x, x, H, L, H, x, H ), ( H, L, x, x, x, x, x, S ), ( x, L, x, x, x, L, x, S ), ( x, H, x, x, x, x, x, H ), ( x, U, x, x, H, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_negedge, TimingData => Tmkr_J_CLK_negedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_negedge, SetupLow => tsetup_J_CLK_noedge_negedge, HoldHigh => thold_J_CLK_noedge_negedge, HoldLow => thold_J_CLK_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_negedge, TimingData => Tmkr_K_CLK_negedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_negedge, SetupLow => tsetup_K_CLK_noedge_negedge, HoldHigh => thold_K_CLK_noedge_negedge, HoldLow => thold_K_CLK_noedge_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/JKF3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(PRE_ipd ) /= '1', HeaderMsg => InstancePath &"/JKF3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF3D", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_negedge or Tviol_K_CLK_negedge or Pviol_PRE or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => DFE4B_Q_tab, DataIn => ( CLK_ipd, PRE_ipd, K_delayed, J_delayed, Q_zd, CLK_delayed)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 1 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF3D_VITAL of JKF3D is for VITAL_ACT end for; end CFG_JKF3D_VITAL; ----- CELL JKF4B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKF4B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_negedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_negedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_negedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_negedge : VitalDelayType := 0.000 ns; tperiod_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKF4B : entity is TRUE; end JKF4B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKF4B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_J_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_negedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_negedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT JKF4B_Q_tab : VitalStateTableType := ( ( L, x, H, x, x, x, x, x, U ), ( L, x, L, x, x, x, x, x, L ), ( H, L, x, H, H, x, H, x, H ), ( H, L, x, H, x, H, H, x, H ), ( H, L, x, x, H, L, H, x, H ), ( H, H, L, x, x, x, x, x, S ), ( H, x, L, x, x, x, L, x, S ), ( H, x, H, x, x, x, x, x, H ), ( x, L, L, L, L, x, H, x, L ), ( x, L, L, L, x, H, H, x, L ), ( x, L, L, x, L, L, H, x, L ), ( U, x, L, x, x, L, x, x, L ), ( H, x, U, x, x, H, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_negedge, TimingData => Tmkr_J_CLK_negedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_negedge, SetupLow => tsetup_J_CLK_noedge_negedge, HoldHigh => thold_J_CLK_noedge_negedge, HoldLow => thold_J_CLK_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_negedge, TimingData => Tmkr_K_CLK_negedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_negedge, SetupLow => tsetup_K_CLK_noedge_negedge, HoldHigh => thold_K_CLK_noedge_negedge, HoldLow => thold_K_CLK_noedge_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_negedge, TimingData => Tmkr_PRE_CLK_negedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_negedge, Removal => thold_PRE_CLK_noedge_negedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'F', HeaderMsg => InstancePath & "/JKF4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_negedge, TimingData => Tmkr_CLR_CLK_negedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_negedge, Removal => thold_CLR_CLK_noedge_negedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'F', HeaderMsg => InstancePath & "/JKF4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/JKF4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/JKF4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKF4B", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_negedge or Tviol_K_CLK_negedge or Pviol_PRE or Tviol_CLR_CLK_negedge or Pviol_CLR or Tviol_PRE_CLK_negedge or Pviol_CLK; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => JKF4B_Q_tab, DataIn => ( CLR_ipd, CLK_ipd, PRE_ipd, K_delayed, J_delayed, Q_zd, CLK_delayed)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKF4B_VITAL of JKF4B is for VITAL_ACT end for; end CFG_JKF4B_VITAL; ----- CELL JKFPC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity JKFPC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_CLR_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_PRE_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_CLK_Q : VitalDelayType01 := (1.000 ns, 1.000 ns); thold_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_J_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; tsetup_K_CLK_noedge_posedge : VitalDelayType := 0.000 ns; thold_PRE_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_PRE_CLK_negedge_posedge : VitalDelayType := 0.000 ns; thold_CLR_CLK_noedge_posedge : VitalDelayType := 0.000 ns; trecovery_CLR_CLK_posedge_posedge : VitalDelayType := 0.000 ns; tperiod_CLK_posedge : VitalDelayType := 0.000 ns; tpw_CLK_posedge : VitalDelayType := 0.000 ns; tpw_PRE_posedge : VitalDelayType := 0.000 ns; tpw_CLK_negedge : VitalDelayType := 0.000 ns; tpw_CLR_negedge : VitalDelayType := 0.000 ns; tipd_J : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_K : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLK : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_PRE : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_CLR : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( J : in STD_ULOGIC; K : in STD_ULOGIC; CLK : in STD_ULOGIC; PRE : in STD_ULOGIC; CLR : in STD_ULOGIC; Q : out STD_ULOGIC); attribute VITAL_LEVEL0 of JKFPC : entity is TRUE; end JKFPC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of JKFPC is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL J_ipd : STD_ULOGIC := 'X'; SIGNAL K_ipd : STD_ULOGIC := 'X'; SIGNAL CLK_ipd : STD_ULOGIC := 'X'; SIGNAL PRE_ipd : STD_ULOGIC := 'X'; SIGNAL CLR_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (J_ipd, J, tipd_J); VitalWireDelay (K_ipd, K, tipd_K); VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (PRE_ipd, PRE, tipd_PRE); VitalWireDelay (CLR_ipd, CLR, tipd_CLR); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (J_ipd, K_ipd, CLK_ipd, PRE_ipd, CLR_ipd) -- timing check results VARIABLE Tviol_J_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_J_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_K_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_K_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_PRE_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_PRE_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_CLR_CLK_posedge : STD_ULOGIC := '0'; VARIABLE Tmkr_CLR_CLK_posedge : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_CLK : STD_ULOGIC := '0'; VARIABLE PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRE : STD_ULOGIC := '0'; VARIABLE PInfo_PRE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLR : STD_ULOGIC := '0'; VARIABLE PInfo_CLR : VitalPeriodDataType := VitalPeriodDataInit; -- functionality results VARIABLE Violation : STD_ULOGIC := '0'; VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 6); VARIABLE J_delayed : STD_ULOGIC := 'X'; VARIABLE K_delayed : STD_ULOGIC := 'X'; VARIABLE CLK_delayed : STD_ULOGIC := 'X'; VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Q_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Q_GlitchData : VitalGlitchDataType; CONSTANT L : VitalTableSymbolType := '0'; CONSTANT H : VitalTableSymbolType := '1'; CONSTANT x : VitalTableSymbolType := '-'; CONSTANT S : VitalTableSymbolType := 'S'; CONSTANT R : VitalTableSymbolType := '/'; CONSTANT U : VitalTableSymbolType := 'X'; CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) CONSTANT JKFPC_Q_tab : VitalStateTableType := ( ( L, x, H, x, x, x, x, x, U ), ( L, x, L, x, x, x, x, x, L ), ( H, L, x, H, H, x, H, x, H ), ( H, L, x, H, x, H, H, x, H ), ( H, L, x, x, H, L, H, x, H ), ( H, H, L, x, x, x, x, x, S ), ( H, x, L, x, x, x, L, x, S ), ( H, x, H, x, x, x, x, x, H ), ( x, L, L, L, L, x, H, x, L ), ( x, L, L, L, x, H, H, x, L ), ( x, L, L, x, L, L, H, x, L ), ( U, x, L, x, x, L, x, x, L ), ( H, x, U, x, x, H, x, x, H )); begin ------------------------ -- Timing Check Section ------------------------ if (TimingChecksOn) then VitalSetupHoldCheck ( Violation => Tviol_J_CLK_posedge, TimingData => Tmkr_J_CLK_posedge, TestSignal => J_ipd, TestSignalName => "J", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_J_CLK_noedge_posedge, SetupLow => tsetup_J_CLK_noedge_posedge, HoldHigh => thold_J_CLK_noedge_posedge, HoldLow => thold_J_CLK_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalSetupHoldCheck ( Violation => Tviol_K_CLK_posedge, TimingData => Tmkr_K_CLK_posedge, TestSignal => K_ipd, TestSignalName => "K", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, SetupHigh => tsetup_K_CLK_noedge_posedge, SetupLow => tsetup_K_CLK_noedge_posedge, HoldHigh => thold_K_CLK_noedge_posedge, HoldLow => thold_K_CLK_noedge_posedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_PRE_CLK_posedge, TimingData => Tmkr_PRE_CLK_posedge, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_PRE_CLK_negedge_posedge, Removal => thold_PRE_CLK_noedge_posedge, ActiveLow => FALSE, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', RefTransition => 'R', HeaderMsg => InstancePath & "/JKFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalRecoveryRemovalCheck ( Violation => Tviol_CLR_CLK_posedge, TimingData => Tmkr_CLR_CLK_posedge, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, RefSignal => CLK_ipd, RefSignalName => "CLK", RefDelay => 0 ns, Recovery => trecovery_CLR_CLK_posedge_posedge, Removal => thold_CLR_CLK_noedge_posedge, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => 'R', HeaderMsg => InstancePath & "/JKFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLK, PeriodData => PInfo_CLK, TestSignal => CLK_ipd, TestSignalName => "CLK", TestDelay => 0 ns, Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TO_X01(( PRE_ipd ) OR ( (NOT CLR_ipd) ) ) /= '1', HeaderMsg => InstancePath &"/JKFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_PRE, PeriodData => PInfo_PRE, TestSignal => PRE_ipd, TestSignalName => "PRE", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => tpw_PRE_posedge, PulseWidthLow => 0 ns, CheckEnabled => TO_X01( (NOT CLR_ipd) ) /= '1', HeaderMsg => InstancePath &"/JKFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); VitalPeriodPulseCheck ( Violation => Pviol_CLR, PeriodData => PInfo_CLR, TestSignal => CLR_ipd, TestSignalName => "CLR", TestDelay => 0 ns, Period => 0 ns, PulseWidthHigh => 0 ns, PulseWidthLow => tpw_CLR_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath &"/JKFPC", Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end if; ------------------------- -- Functionality Section ------------------------- Violation := Tviol_J_CLK_posedge or Tviol_CLR_CLK_posedge or Pviol_PRE or Tviol_K_CLK_posedge or Tviol_PRE_CLK_posedge or Pviol_CLK or Pviol_CLR; VitalStateTable( Result => Q_zd, PreviousDataIn => PrevData_Q, StateTable => JKFPC_Q_tab, DataIn => ( CLR_ipd, CLK_delayed, PRE_ipd, K_delayed, J_delayed, Q_zd, CLK_ipd)); Q_zd := Violation XOR Q_zd; J_delayed := J_ipd; K_delayed := K_ipd; CLK_delayed := CLK_ipd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Q, GlitchData => Q_GlitchData, OutSignalName => "Q", OutTemp => Q_zd, Paths => (0 => (CLR_ipd'last_event, tpd_CLR_Q, TRUE), 1 => (PRE_ipd'last_event, tpd_PRE_Q, TRUE), 2 => (CLK_ipd'last_event, tpd_CLK_Q, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_JKFPC_VITAL of JKFPC is for VITAL_ACT end for; end CFG_JKFPC_VITAL; ----- CELL MAJ3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MAJ3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MAJ3 : entity is TRUE; end MAJ3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of MAJ3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((C_ipd) AND (B_ipd)) OR ((B_ipd) AND (A_ipd)) OR ((C_ipd) AND (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MAJ3_VITAL of MAJ3 is for VITAL_ACT end for; end CFG_MAJ3_VITAL; ----- CELL MX2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MX2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MX2 : entity is TRUE; end MX2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of MX2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalMUX (data => (B_ipd, A_ipd), dselect => (0 => S_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S_ipd'last_event, tpd_S_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MX2_VITAL of MX2 is for VITAL_ACT end for; end CFG_MX2_VITAL; ----- CELL MX2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MX2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MX2A : entity is TRUE; end MX2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of MX2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((S_ipd) AND (B_ipd)) OR (((NOT S_ipd)) AND ((NOT A_ipd))) OR ((B_ipd) AND ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S_ipd'last_event, tpd_S_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MX2A_VITAL of MX2A is for VITAL_ACT end for; end CFG_MX2A_VITAL; ----- CELL MX2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MX2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MX2B : entity is TRUE; end MX2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of MX2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((S_ipd) AND ((NOT B_ipd))) OR (((NOT S_ipd)) AND (A_ipd)) OR ((A_ipd) AND ((NOT B_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S_ipd'last_event, tpd_S_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MX2B_VITAL of MX2B is for VITAL_ACT end for; end CFG_MX2B_VITAL; ----- CELL MX2C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MX2C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MX2C : entity is TRUE; end MX2C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of MX2C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, S_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalMUX (data => (B_ipd, A_ipd), dselect => (0 => S_ipd)); Y_zd := NOT Y_zd; ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S_ipd'last_event, tpd_S_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MX2C_VITAL of MX2C is for VITAL_ACT end for; end CFG_MX2C_VITAL; ----- CELL MX4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MX4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0 : in STD_ULOGIC; S1 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MX4 : entity is TRUE; end MX4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of MX4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S0_ipd : STD_ULOGIC := 'X'; SIGNAL S1_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S0_ipd, S0, tipd_S0); VitalWireDelay (S1_ipd, S1, tipd_S1); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, D3_ipd, S0_ipd, S1_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := VitalMUX (data => (D3_ipd, D2_ipd, D1_ipd, D0_ipd), dselect => (S1_ipd, S0_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S1_ipd'last_event, tpd_S1_Y, TRUE), 1 => (S0_ipd'last_event, tpd_S0_Y, TRUE), 2 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 3 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 4 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 5 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MX4_VITAL of MX4 is for VITAL_ACT end for; end CFG_MX4_VITAL; ----- CELL MXC1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MXC1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MXC1 : entity is TRUE; end MXC1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of MXC1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL S_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (S_ipd, S, tipd_S); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd, S_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE MUX_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- ((D_ipd) AND (((B_ipd) AND (S_ipd)) OR ((A_ipd) AND ((NOT S_ipd))))) -- OR ((C_ipd) AND ((NOT (((B_ipd) AND (S_ipd)) OR ((A_ipd) AND ((NOT -- S_ipd))))))); MUX_Out := VitalMUX2(B_ipd, A_ipd, S_ipd); Y_zd := VitalMUX2(D_ipd, C_ipd, MUX_Out); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S_ipd'last_event, tpd_S_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE), 3 => (D_ipd'last_event, tpd_D_Y, TRUE), 4 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MXC1_VITAL of MXC1 is for VITAL_ACT end for; end CFG_MXC1_VITAL; ----- CELL MXT ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity MXT is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_S1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_S0A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D3_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D2_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D1_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D0_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D0 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D1 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D2 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D3 : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S0B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_S1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; D2 : in STD_ULOGIC; D3 : in STD_ULOGIC; S0A : in STD_ULOGIC; S0B : in STD_ULOGIC; S1 : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of MXT : entity is TRUE; end MXT; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of MXT is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D0_ipd : STD_ULOGIC := 'X'; SIGNAL D1_ipd : STD_ULOGIC := 'X'; SIGNAL D2_ipd : STD_ULOGIC := 'X'; SIGNAL D3_ipd : STD_ULOGIC := 'X'; SIGNAL S0A_ipd : STD_ULOGIC := 'X'; SIGNAL S0B_ipd : STD_ULOGIC := 'X'; SIGNAL S1_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D0_ipd, D0, tipd_D0); VitalWireDelay (D1_ipd, D1, tipd_D1); VitalWireDelay (D2_ipd, D2, tipd_D2); VitalWireDelay (D3_ipd, D3, tipd_D3); VitalWireDelay (S0A_ipd, S0A, tipd_S0A); VitalWireDelay (S0B_ipd, S0B, tipd_S0B); VitalWireDelay (S1_ipd, S1, tipd_S1); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D0_ipd, D1_ipd, D2_ipd, D3_ipd, S0A_ipd, S0B_ipd, S1_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); VARIABLE MUX1_Out, MUX2_Out : std_ulogic; -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- --Y_zd := -- ((S0A_ipd) AND ((NOT S1_ipd)) AND (D1_ipd)) OR (((NOT S0A_ipd)) AND -- ((NOT S1_ipd)) AND (D0_ipd)) OR (((NOT S0B_ipd)) AND (S1_ipd) AND -- (D2_ipd)) OR ((S0B_ipd) AND (S1_ipd) AND (D3_ipd)); MUX1_Out := VitalMUX2(D1_ipd, D0_ipd, S0A_ipd); MUX2_Out := VitalMUX2(D3_ipd, D2_ipd, S0B_ipd); Y_zd := VitalMUX2(MUX2_Out, MUX1_Out, S1_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (S1_ipd'last_event, tpd_S1_Y, TRUE), 1 => (S0B_ipd'last_event, tpd_S0B_Y, TRUE), 2 => (S0A_ipd'last_event, tpd_S0A_Y, TRUE), 3 => (D3_ipd'last_event, tpd_D3_Y, TRUE), 4 => (D2_ipd'last_event, tpd_D2_Y, TRUE), 5 => (D1_ipd'last_event, tpd_D1_Y, TRUE), 6 => (D0_ipd'last_event, tpd_D0_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_MXT_VITAL of MXT is for VITAL_ACT end for; end CFG_MXT_VITAL; ----- CELL NAND2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND2 : entity is TRUE; end NAND2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) AND (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND2_VITAL of NAND2 is for VITAL_ACT end for; end CFG_NAND2_VITAL; ----- CELL NAND2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND2A : entity is TRUE; end NAND2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) AND ((NOT A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND2A_VITAL of NAND2A is for VITAL_ACT end for; end CFG_NAND2A_VITAL; ----- CELL NAND2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND2B : entity is TRUE; end NAND2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND2B_VITAL of NAND2B is for VITAL_ACT end for; end CFG_NAND2B_VITAL; ----- CELL NAND3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND3 : entity is TRUE; end NAND3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) AND (A_ipd) AND (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND3_VITAL of NAND3 is for VITAL_ACT end for; end CFG_NAND3_VITAL; ----- CELL NAND3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND3A : entity is TRUE; end NAND3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) AND ((NOT A_ipd)) AND (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND3A_VITAL of NAND3A is for VITAL_ACT end for; end CFG_NAND3A_VITAL; ----- CELL NAND3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND3B : entity is TRUE; end NAND3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)) AND (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND3B_VITAL of NAND3B is for VITAL_ACT end for; end CFG_NAND3B_VITAL; ----- CELL NAND3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND3C : entity is TRUE; end NAND3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND3C_VITAL of NAND3C is for VITAL_ACT end for; end CFG_NAND3C_VITAL; ----- CELL NAND4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND4 : entity is TRUE; end NAND4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR ((NOT ((B_ipd) AND (A_ipd)))) OR ((NOT D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND4_VITAL of NAND4 is for VITAL_ACT end for; end CFG_NAND4_VITAL; ----- CELL NAND4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND4A : entity is TRUE; end NAND4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR ((NOT ((B_ipd) AND ((NOT A_ipd))))) OR ((NOT D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND4A_VITAL of NAND4A is for VITAL_ACT end for; end CFG_NAND4A_VITAL; ----- CELL NAND4B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND4B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND4B : entity is TRUE; end NAND4B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND4B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR ((NOT (((NOT B_ipd)) AND ((NOT A_ipd))))) OR ((NOT D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND4B_VITAL of NAND4B is for VITAL_ACT end for; end CFG_NAND4B_VITAL; ----- CELL NAND4C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND4C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND4C : entity is TRUE; end NAND4C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND4C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)) AND (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND4C_VITAL of NAND4C is for VITAL_ACT end for; end CFG_NAND4C_VITAL; ----- CELL NAND4D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NAND4D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NAND4D : entity is TRUE; end NAND4D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NAND4D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) AND ((NOT A_ipd)) AND ((NOT C_ipd)) AND ((NOT D_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NAND4D_VITAL of NAND4D is for VITAL_ACT end for; end CFG_NAND4D_VITAL; ----- CELL NOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR2 : entity is TRUE; end NOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) OR (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR2_VITAL of NOR2 is for VITAL_ACT end for; end CFG_NOR2_VITAL; ----- CELL NOR2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR2A : entity is TRUE; end NOR2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) OR ((NOT A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR2A_VITAL of NOR2A is for VITAL_ACT end for; end CFG_NOR2A_VITAL; ----- CELL NOR2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR2B : entity is TRUE; end NOR2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR2B_VITAL of NOR2B is for VITAL_ACT end for; end CFG_NOR2B_VITAL; ----- CELL NOR3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR3 : entity is TRUE; end NOR3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) OR (A_ipd) OR (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR3_VITAL of NOR3 is for VITAL_ACT end for; end CFG_NOR3_VITAL; ----- CELL NOR3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR3A : entity is TRUE; end NOR3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) OR ((NOT A_ipd)) OR (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR3A_VITAL of NOR3A is for VITAL_ACT end for; end CFG_NOR3A_VITAL; ----- CELL NOR3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR3B : entity is TRUE; end NOR3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)) OR (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR3B_VITAL of NOR3B is for VITAL_ACT end for; end CFG_NOR3B_VITAL; ----- CELL NOR3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR3C : entity is TRUE; end NOR3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)) OR ((NOT C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR3C_VITAL of NOR3C is for VITAL_ACT end for; end CFG_NOR3C_VITAL; ----- CELL NOR4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR4 : entity is TRUE; end NOR4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) AND ((NOT ((B_ipd) OR (A_ipd)))) AND ((NOT D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR4_VITAL of NOR4 is for VITAL_ACT end for; end CFG_NOR4_VITAL; ----- CELL NOR4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR4A : entity is TRUE; end NOR4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) OR ((NOT A_ipd)) OR (C_ipd) OR (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR4A_VITAL of NOR4A is for VITAL_ACT end for; end CFG_NOR4A_VITAL; ----- CELL NOR4B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR4B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR4B : entity is TRUE; end NOR4B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR4B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT B_ipd)) OR ((NOT A_ipd)) OR (C_ipd) OR (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR4B_VITAL of NOR4B is for VITAL_ACT end for; end CFG_NOR4B_VITAL; ----- CELL NOR4C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR4C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR4C : entity is TRUE; end NOR4C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR4C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((NOT (((NOT B_ipd)) OR ((NOT A_ipd))))) AND ((NOT D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR4C_VITAL of NOR4C is for VITAL_ACT end for; end CFG_NOR4C_VITAL; ----- CELL NOR4D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity NOR4D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of NOR4D : entity is TRUE; end NOR4D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of NOR4D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((NOT (((NOT B_ipd)) OR ((NOT A_ipd))))) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_NOR4D_VITAL of NOR4D is for VITAL_ACT end for; end CFG_NOR4D_VITAL; ----- CELL OA1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA1 : entity is TRUE; end OA1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OA1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((B_ipd) OR (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA1_VITAL of OA1 is for VITAL_ACT end for; end CFG_OA1_VITAL; ----- CELL OA1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA1A : entity is TRUE; end OA1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OA1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((B_ipd) OR ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA1A_VITAL of OA1A is for VITAL_ACT end for; end CFG_OA1A_VITAL; ----- CELL OA1B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA1B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA1B : entity is TRUE; end OA1B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OA1B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) AND ((B_ipd) OR (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA1B_VITAL of OA1B is for VITAL_ACT end for; end CFG_OA1B_VITAL; ----- CELL OA1C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA1C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA1C : entity is TRUE; end OA1C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OA1C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) AND ((B_ipd) OR ((NOT A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA1C_VITAL of OA1C is for VITAL_ACT end for; end CFG_OA1C_VITAL; ----- CELL OA2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA2 : entity is TRUE; end OA2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OA2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((B_ipd) OR (A_ipd)) AND ((D_ipd) OR (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA2_VITAL of OA2 is for VITAL_ACT end for; end CFG_OA2_VITAL; ----- CELL OA2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA2A : entity is TRUE; end OA2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OA2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((B_ipd) OR ((NOT A_ipd))) AND ((D_ipd) OR (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA2A_VITAL of OA2A is for VITAL_ACT end for; end CFG_OA2A_VITAL; ----- CELL OA3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA3 : entity is TRUE; end OA3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OA3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((B_ipd) OR (A_ipd)) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA3_VITAL of OA3 is for VITAL_ACT end for; end CFG_OA3_VITAL; ----- CELL OA3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA3A : entity is TRUE; end OA3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OA3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) AND ((B_ipd) OR (A_ipd)) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA3A_VITAL of OA3A is for VITAL_ACT end for; end CFG_OA3A_VITAL; ----- CELL OA3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA3B : entity is TRUE; end OA3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OA3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) AND ((B_ipd) OR ((NOT A_ipd))) AND (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (D_ipd'last_event, tpd_D_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA3B_VITAL of OA3B is for VITAL_ACT end for; end CFG_OA3B_VITAL; ----- CELL OA4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA4A : entity is TRUE; end OA4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OA4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (D_ipd) AND ((B_ipd) OR (A_ipd) OR ((NOT C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA4A_VITAL of OA4A is for VITAL_ACT end for; end CFG_OA4A_VITAL; ----- CELL OA5 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OA5 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OA5 : entity is TRUE; end OA5; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OA5 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((D_ipd) OR (A_ipd)) AND ((B_ipd) OR (A_ipd) OR (C_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OA5_VITAL of OA5 is for VITAL_ACT end for; end CFG_OA5_VITAL; ----- CELL OAI1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OAI1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OAI1 : entity is TRUE; end OAI1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OAI1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) AND ((B_ipd) OR (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OAI1_VITAL of OAI1 is for VITAL_ACT end for; end CFG_OAI1_VITAL; ----- CELL OAI2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OAI2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OAI2A : entity is TRUE; end OAI2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OAI2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT D_ipd)) AND ((B_ipd) OR (A_ipd) OR (C_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE), 3 => (D_ipd'last_event, tpd_D_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OAI2A_VITAL of OAI2A is for VITAL_ACT end for; end CFG_OAI2A_VITAL; ----- CELL OAI3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OAI3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OAI3 : entity is TRUE; end OAI3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OAI3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((C_ipd) AND ((B_ipd) OR (A_ipd)) AND (D_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OAI3_VITAL of OAI3 is for VITAL_ACT end for; end CFG_OAI3_VITAL; ----- CELL OAI3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OAI3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OAI3A : entity is TRUE; end OAI3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OAI3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT (((NOT C_ipd)) AND ((B_ipd) OR (A_ipd)) AND ((NOT D_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (D_ipd'last_event, tpd_D_Y, TRUE), 3 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OAI3A_VITAL of OAI3A is for VITAL_ACT end for; end CFG_OAI3A_VITAL; ----- CELL OR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR2 : entity is TRUE; end OR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR2_VITAL of OR2 is for VITAL_ACT end for; end CFG_OR2_VITAL; ----- CELL OR2A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR2A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR2A : entity is TRUE; end OR2A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR2A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR ((NOT A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR2A_VITAL of OR2A is for VITAL_ACT end for; end CFG_OR2A_VITAL; ----- CELL OR2B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR2B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR2B : entity is TRUE; end OR2B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR2B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR2B_VITAL of OR2B is for VITAL_ACT end for; end CFG_OR2B_VITAL; ----- CELL OR3 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR3 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR3 : entity is TRUE; end OR3; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR3 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR (A_ipd) OR (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR3_VITAL of OR3 is for VITAL_ACT end for; end CFG_OR3_VITAL; ----- CELL OR3A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR3A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR3A : entity is TRUE; end OR3A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR3A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR ((NOT A_ipd)) OR (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR3A_VITAL of OR3A is for VITAL_ACT end for; end CFG_OR3A_VITAL; ----- CELL OR3B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR3B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR3B : entity is TRUE; end OR3B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR3B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)) OR (C_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR3B_VITAL of OR3B is for VITAL_ACT end for; end CFG_OR3B_VITAL; ----- CELL OR3C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR3C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR3C : entity is TRUE; end OR3C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR3C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) AND (A_ipd) AND (C_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR3C_VITAL of OR3C is for VITAL_ACT end for; end CFG_OR3C_VITAL; ----- CELL OR4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR4 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR4 : entity is TRUE; end OR4; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR4 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR (A_ipd) OR (C_ipd) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR4_VITAL of OR4 is for VITAL_ACT end for; end CFG_OR4_VITAL; ----- CELL OR4A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR4A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR4A : entity is TRUE; end OR4A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR4A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) OR ((NOT A_ipd)) OR (C_ipd) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (A_ipd'last_event, tpd_A_Y, TRUE), 1 => (D_ipd'last_event, tpd_D_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE), 3 => (B_ipd'last_event, tpd_B_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR4A_VITAL of OR4A is for VITAL_ACT end for; end CFG_OR4A_VITAL; ----- CELL OR4B ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR4B is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR4B : entity is TRUE; end OR4B; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR4B is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)) OR (C_ipd) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (D_ipd'last_event, tpd_D_Y, TRUE), 3 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR4B_VITAL of OR4B is for VITAL_ACT end for; end CFG_OR4B_VITAL; ----- CELL OR4C ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR4C is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR4C : entity is TRUE; end OR4C; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR4C is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT B_ipd)) OR ((NOT A_ipd)) OR ((NOT C_ipd)) OR (D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (C_ipd'last_event, tpd_C_Y, TRUE), 1 => (B_ipd'last_event, tpd_B_Y, TRUE), 2 => (A_ipd'last_event, tpd_A_Y, TRUE), 3 => (D_ipd'last_event, tpd_D_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR4C_VITAL of OR4C is for VITAL_ACT end for; end CFG_OR4C_VITAL; ----- CELL OR4D ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OR4D is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of OR4D : entity is TRUE; end OR4D; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OR4D is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd, D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := ((NOT C_ipd)) OR ((NOT ((B_ipd) AND (A_ipd)))) OR ((NOT D_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (D_ipd'last_event, tpd_D_Y, TRUE), 1 => (C_ipd'last_event, tpd_C_Y, TRUE), 2 => (B_ipd'last_event, tpd_B_Y, TRUE), 3 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OR4D_VITAL of OR4D is for VITAL_ACT end for; end CFG_OR4D_VITAL; ----- CELL OUTBUF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity OUTBUF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; PAD : out STD_ULOGIC); attribute VITAL_LEVEL0 of OUTBUF : entity is TRUE; end OUTBUF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of OUTBUF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS PAD_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE PAD_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- PAD_zd := TO_X01(D_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => PAD, GlitchData => PAD_GlitchData, OutSignalName => "PAD", OutTemp => PAD_zd, Paths => (0 => (D_ipd'last_event, tpd_D_PAD, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_OUTBUF_VITAL of OUTBUF is for VITAL_ACT end for; end CFG_OUTBUF_VITAL; ----- CELL TRIBUFF ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity TRIBUFF is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_E_PAD : VitalDelayType01z := (0.000 ns, 0.000 ns, 1.000 ns, 1.000 ns, 1.000 ns, 1.000 ns); tpd_D_PAD : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_D : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_E : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( D : in STD_ULOGIC; E : in STD_ULOGIC; PAD : out STD_ULOGIC); attribute VITAL_LEVEL0 of TRIBUFF : entity is TRUE; end TRIBUFF; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of TRIBUFF is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL D_ipd : STD_ULOGIC := 'X'; SIGNAL E_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (D_ipd, D, tipd_D); VitalWireDelay (E_ipd, E, tipd_E); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (D_ipd, E_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS PAD_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE PAD_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- PAD_zd := VitalBUFIF0 (data => D_ipd, enable => (NOT E_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01Z ( OutSignal => PAD, GlitchData => PAD_GlitchData, OutSignalName => "PAD", OutTemp => PAD_zd, Paths => (0 => (E_ipd'last_event, tpd_E_PAD, TRUE), 1 => (D_ipd'last_event, VitalExtendToFillDelay(tpd_D_PAD), TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING, OutputMap => "UX01ZWLH-"); end process; end VITAL_ACT; configuration CFG_TRIBUFF_VITAL of TRIBUFF is for VITAL_ACT end for; end CFG_TRIBUFF_VITAL; ----- CELL VCC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity VCC is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True); port( Y : out STD_ULOGIC := '1'); attribute VITAL_LEVEL0 of VCC : entity is TRUE; end VCC; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; architecture VITAL_ACT of VCC is attribute VITAL_LEVEL0 of VITAL_ACT : architecture is TRUE; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin -- empty end block; -------------------- -- BEHAVIOR SECTION -------------------- Y <= '1'; end VITAL_ACT; configuration CFG_VCC_VITAL of VCC is for VITAL_ACT end for; end CFG_VCC_VITAL; ----- CELL XA1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XA1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XA1 : entity is TRUE; end XA1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of XA1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((B_ipd) XOR (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XA1_VITAL of XA1 is for VITAL_ACT end for; end CFG_XA1_VITAL; ----- CELL XA1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XA1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XA1A : entity is TRUE; end XA1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of XA1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) AND ((NOT ((B_ipd) XOR (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XA1A_VITAL of XA1A is for VITAL_ACT end for; end CFG_XA1A_VITAL; ----- CELL XNOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XNOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XNOR2 : entity is TRUE; end XNOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of XNOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (NOT ((B_ipd) XOR (A_ipd))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XNOR2_VITAL of XNOR2 is for VITAL_ACT end for; end CFG_XNOR2_VITAL; ----- CELL XO1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XO1 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XO1 : entity is TRUE; end XO1; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of XO1 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((B_ipd) XOR (A_ipd)); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XO1_VITAL of XO1 is for VITAL_ACT end for; end CFG_XO1_VITAL; ----- CELL XO1A ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XO1A is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_C_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_C : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XO1A : entity is TRUE; end XO1A; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of XO1A is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; SIGNAL C_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); VitalWireDelay (C_ipd, C, tipd_C); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd, C_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (C_ipd) OR ((NOT ((B_ipd) XOR (A_ipd)))); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE), 2 => (C_ipd'last_event, tpd_C_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XO1A_VITAL of XO1A is for VITAL_ACT end for; end CFG_XO1A_VITAL; ----- CELL XOR2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; -- entity declaration -- entity XOR2 is generic( TimingChecksOn: Boolean := True; InstancePath: STRING := "*"; Xon: Boolean := False; MsgOn: Boolean := True; tpd_B_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tpd_A_Y : VitalDelayType01 := (1.000 ns, 1.000 ns); tipd_A : VitalDelayType01 := (0.000 ns, 0.000 ns); tipd_B : VitalDelayType01 := (0.000 ns, 0.000 ns)); port( A : in STD_ULOGIC; B : in STD_ULOGIC; Y : out STD_ULOGIC); attribute VITAL_LEVEL0 of XOR2 : entity is TRUE; end XOR2; -- architecture body -- library IEEE; use IEEE.VITAL_Primitives.all; library a40mx; use a40mx.VTABLES.all; architecture VITAL_ACT of XOR2 is attribute VITAL_LEVEL1 of VITAL_ACT : architecture is TRUE; SIGNAL A_ipd : STD_ULOGIC := 'X'; SIGNAL B_ipd : STD_ULOGIC := 'X'; begin --------------------- -- INPUT PATH DELAYs --------------------- WireDelay : block begin VitalWireDelay (A_ipd, A, tipd_A); VitalWireDelay (B_ipd, B, tipd_B); end block; -------------------- -- BEHAVIOR SECTION -------------------- VITALBehavior : process (A_ipd, B_ipd) -- functionality results VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); ALIAS Y_zd : STD_LOGIC is Results(1); -- output glitch detection variables VARIABLE Y_GlitchData : VitalGlitchDataType; begin ------------------------- -- Functionality Section ------------------------- Y_zd := (B_ipd) XOR (A_ipd); ---------------------- -- Path Delay Section ---------------------- VitalPathDelay01 ( OutSignal => Y, GlitchData => Y_GlitchData, OutSignalName => "Y", OutTemp => Y_zd, Paths => (0 => (B_ipd'last_event, tpd_B_Y, TRUE), 1 => (A_ipd'last_event, tpd_A_Y, TRUE)), Mode => OnDetect, Xon => Xon, MsgOn => MsgOn, MsgSeverity => WARNING); end process; end VITAL_ACT; configuration CFG_XOR2_VITAL of XOR2 is for VITAL_ACT end for; end CFG_XOR2_VITAL; ---- end of library ----