Project Information k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 09/08/2006 17:05:29 Copyright (C) 1988-2002 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful ** DEVICE SUMMARY ** Chip/ Input Output Bidir Memory Memory LCs POF Device Pins Pins Pins Bits % Utilized LCs % Utilized top_pre EP1K100QC208-2 4 17 0 0 0 % 111 2 % User Pins: 4 17 0 Project Information k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt ** PROJECT COMPILATION MESSAGES ** Warning: Node 'LED_GRN' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem Warning: Node 'LVDS_in0' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem Warning: Node 'LVDS_in1' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem Warning: Node 'LVDS_in2' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem Warning: Node 'LVDS_in3' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem Warning: Node 'pre_out_lvds' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem ** PROJECT TIMING MESSAGES ** Warning: Found ripple clock -- warning messages and Report File information on tco, tsu, and fmax may be inaccurate Project Information k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt ** PIN/LOCATION/CHIP ASSIGNMENTS ** Actual User Assignments Assignments (if different) Node Name top_pre@27 ADC_OEn top_pre@182 CLK top_pre@184 inp_sw top_pre@195 --------- LED_GRN top_pre@193 LED_RED top_pre@206 LVDS_EN top_pre@8 --------- LVDS_in0 top_pre@7 --------- LVDS_in1 top_pre@9 --------- LVDS_in2 top_pre@10 --------- LVDS_in3 top_pre@183 mode_sw top_pre@39 pre_in top_pre@208 --------- pre_out_lvds top_pre@25 pre_out0 top_pre@19 pre_out1 top_pre@17 pre_out2 top_pre@15 pre_out3 top_pre@192 R7S1 top_pre@180 R7S2 top_pre@186 R7S3 top_pre@187 R7S4 top_pre@189 R7S5 top_pre@191 R7S6 top_pre@190 R7S7 top_pre@125 SRAM_CEn top_pre@131 SRAM_OEn top_pre@37 tst_out Project Information k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt ** FILE HIERARCHY ** |lpm_counter:mode_ix7| |lpm_counter:mode_ix7|lpm_constant:scdw| |lpm_counter:div_clk_ix7| |lpm_counter:div_clk_ix7|lpm_constant:scdw| |carry_sum:result_inc_26_ix41_carry_sum| |carry_sum:result_inc_26_ix45_carry_sum| |carry_sum:result_inc_26_ix49_carry_sum| |carry_sum:result_inc_26_ix53_carry_sum| |carry_sum:result_inc_26_ix57_carry_sum| |carry_sum:result_inc_26_ix61_carry_sum| |carry_sum:result_inc_26_ix65_carry_sum| |carry_sum:result_inc_26_ix69_carry_sum| |carry_sum:result_inc_26_ix73_carry_sum| |carry_sum:result_inc_26_ix77_carry_sum| |carry_sum:result_inc_26_ix81_carry_sum| |carry_sum:result_inc_26_ix85_carry_sum| |carry_sum:result_inc_26_ix89_carry_sum| |carry_sum:result_inc_26_ix93_carry_sum| |carry_sum:result_inc_26_ix39_carry_sum| Device-Specific Information:k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt top_pre ***** Logic for device 'top_pre' compiled without errors. Device: EP1K100QC208-2 ACEX 1K Configuration Scheme: Passive Serial Device Options: User-Supplied Start-Up Clock = OFF Auto-Restart Configuration on Frame Error = OFF Release Clears Before Tri-States = OFF Enable Chip_Wide Reset = OFF Enable Chip-Wide Output Enable = OFF Enable INIT_DONE Output = OFF JTAG User Code = 7f MultiVolt I/O = OFF Enable Lock Output = OFF Device-Specific Information:k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt top_pre ** ERROR SUMMARY ** Info: Project fit with the following "Advanced Try Harder/Longer Compilation" Fitter Settings. Info: To preserve the fit in future compilations, change to "Custom" in the Fitter Settings dialog box and enter the options specified below. Info: 1. Turn on the Normal option under "Auto LCELL Insertion Options". Info: 2. Turn on the Output Pins Fed by Carry Chains option. R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R E E L E E E E E E E E E E L m E E E E E E E E E E E E E E E E E E E E S S V S S S S V S S S S S S E V i o S S S S S S S S S S S S S S S S S S S S E E D E E E E C E E E E E E V D C n d E V E E E E E E E E E E E V E E E E E E E E R R S R R R R C R R R R R R C _ R R R R R R C p e R R C R R R R R R R R R R R C R R R R R R R R V V _ V V V V I V V V V V V C R 7 7 7 7 G 7 7 I _ _ C G 7 V C V V V V V V G V V V V V C V V V V V V V V E E E E E E E N E E E E E E I E S S S S N S S N s s L N S E I E E E E E E N E E E E E I E E E E E E E E D D N D D D D T D D D D D D O D 1 6 7 5 D 4 3 T w w K D 2 D O D D D D D D D D D D D D O D D D D D D D D ----------------------------------------------------------------------------------------------------------_ / 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_ / 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 | #TCK | 1 156 | ^DATA0 ^CONF_DONE | 2 155 | ^DCLK ^nCEO | 3 154 | ^nCE #TDO | 4 153 | #TDI VCCIO | 5 152 | VCCINT GND | 6 151 | GND RESERVED | 7 150 | RESERVED RESERVED | 8 149 | RESERVED RESERVED | 9 148 | RESERVED RESERVED | 10 147 | RESERVED RESERVED | 11 146 | VCCIO RESERVED | 12 145 | GND RESERVED | 13 144 | RESERVED RESERVED | 14 143 | RESERVED pre_out3 | 15 142 | RESERVED RESERVED | 16 141 | RESERVED pre_out2 | 17 140 | RESERVED RESERVED | 18 139 | RESERVED pre_out1 | 19 138 | VCCIO GND | 20 137 | GND VCCINT | 21 136 | RESERVED VCCIO | 22 135 | RESERVED GND | 23 134 | RESERVED RESERVED | 24 133 | RESERVED pre_out0 | 25 132 | RESERVED RESERVED | 26 131 | SRAM_OEn ADC_OEn | 27 EP1K100QC208-2 130 | VCCINT RESERVED | 28 129 | GND RESERVED | 29 128 | RESERVED RESERVED | 30 127 | RESERVED RESERVED | 31 126 | RESERVED GND | 32 125 | SRAM_CEn VCCINT | 33 124 | VCCINT VCCIO | 34 123 | GND GND | 35 122 | RESERVED RESERVED | 36 121 | RESERVED tst_out | 37 120 | RESERVED RESERVED | 38 119 | RESERVED pre_in | 39 118 | VCCIO RESERVED | 40 117 | GND RESERVED | 41 116 | RESERVED VCCIO | 42 115 | RESERVED GND | 43 114 | RESERVED RESERVED | 44 113 | RESERVED RESERVED | 45 112 | RESERVED RESERVED | 46 111 | RESERVED RESERVED | 47 110 | VCCIO VCCINT | 48 109 | GND GND | 49 108 | ^MSEL0 #TMS | 50 107 | ^MSEL1 #TRST | 51 106 | VCCINT ^nSTATUS | 52 105 | ^nCONFIG | 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _| \ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 | \----------------------------------------------------------------------------------------------------------- R R R R R R G R R R R R R V R R R R R V R R R G V G G G G G R V R R R R R R V R R R R R R V R R R R R R E E E E E E N E E E E E E C E E E E E C E E E N C N N N N N E C E E E E E E C E E E E E E C E E E E E E S S S S S S D S S S S S S C S S S S S C S S S D C D D D D D S C S S S S S S C S S S S S S C S S S S S S E E E E E E E E E E E E I E E E E E I E E E _ _ E I E E E E E E I E E E E E E I E E E E E E R R R R R R R R R R R R O R R R R R N R R R C C R O R R R R R R N R R R R R R O R R R R R R V V V V V V V V V V V V V V V V V T V V V K K V V V V V V V T V V V V V V V V V V V V E E E E E E E E E E E E E E E E E E E E L L E E E E E E E E E E E E E E E E E E E D D D D D D D D D D D D D D D D D D D D K K D D D D D D D D D D D D D D D D D D D N.C. = No Connect. This pin has no internal connection to the device. VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts). VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts). GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which is tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. $ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant. Device-Specific Information:k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt top_pre ** RESOURCE USAGE ** Logic Column Row Array Interconnect Interconnect Clears/ External Block Logic Cells Driven Driven Clocks Presets Interconnect D38 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 19/26( 73%) D41 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 8/26( 30%) D45 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 9/26( 34%) D46 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/26( 19%) D47 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 8/26( 30%) D48 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/26( 3%) D49 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 9/26( 34%) D50 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 2/26( 7%) L25 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/26( 15%) L27 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/26( 15%) L30 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/26( 15%) L34 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/26( 15%) L35 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 8/26( 30%) L37 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 14/26( 53%) L38 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 6/26( 23%) L39 8/ 8(100%) 0/ 8( 0%) 0/ 8( 0%) 1/2 0/2 0/26( 0%) L41 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 0/26( 0%) L43 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 0/26( 0%) L45 5/ 8( 62%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 3/26( 11%) L52 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 2/26( 7%) Embedded Column Row Array Embedded Interconnect Interconnect Read/ External Block Cells Driven Driven Clocks Write Interconnect Total dedicated input pins used: 3/6 ( 50%) Total I/O pins used: 18/141 ( 12%) Total logic cells used: 111/4992 ( 2%) Total embedded cells used: 0/192 ( 0%) Total EABs used: 0/12 ( 0%) Average fan-in: 1.90/4 ( 47%) Total fan-in: 211/19968 ( 1%) Total input pins required: 4 Total input I/O cell registers required: 0 Total output pins required: 17 Total output I/O cell registers required: 0 Total buried I/O cell registers required: 0 Total bidirectional pins required: 0 Total reserved pins required 0 Total logic cells required: 111 Total flipflops required: 66 Total packed registers required: 0 Total logic cells in carry chains: 47 Total number of carry chains: 3 Total number of carry chains of length 1-8 : 1 Total number of carry chains of length 9-16: 1 Total number of carry chains of length 17-24: 0 Total number of carry chains of length 25-32: 1 Total logic cells in cascade chains: 15 Total number of cascade chains: 7 Total single-pin Clock Enables required: 0 Total single-pin Output Enables required: 0 Logic cells inserted for fitting: 1 Synthesized logic cells: 5/4992 ( 0%) Logic Cell and Embedded Cell Counts Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC) A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 8 0 0 0 8 8 8 1 8 3 0 0 52/0 E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 0 1 0 0 0 1 3 0 8 6 8 0 8 0 8 0 5 0 0 0 0 0 0 8 59/0 Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 0 1 0 0 0 1 3 0 8 14 8 0 16 0 8 0 13 8 8 1 8 3 0 8 111/0 Device-Specific Information:k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt top_pre ** INPUTS ** Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name 182 - - - -- INPUT G ^ 0 0 0 0 CLK 184 - - - -- INPUT ^ 0 0 0 1 inp_sw 183 - - - -- INPUT ^ 0 0 0 1 mode_sw 39 - - J -- INPUT ^ 0 0 0 1 pre_in Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell ^ = Increased input delay * = PCI I/O is enabled @ = Uses single-pin Clock Enable & = Uses single-pin Output Enable G = Global Source. Fan-out destinations counted here do not include destinations that are driven using global routing resources. Refer to the Auto Global Signals, Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals Sections of this Report File for information on which signals' fan-outs are used as Clock, Clear, Preset, Output Enable, and synchronous Load signals. Device-Specific Information:k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt top_pre ** OUTPUTS ** Fed By Fed By Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name 27 - - F -- OUTPUT 0 0 0 0 ADC_OEn 193 - - - 38 OUTPUT 0 1 0 0 LED_RED 206 - - - 50 OUTPUT 0 0 0 0 LVDS_EN 25 - - E -- OUTPUT 0 1 0 0 pre_out0 19 - - D -- OUTPUT 0 1 0 0 pre_out1 17 - - D -- OUTPUT 0 1 0 0 pre_out2 15 - - C -- OUTPUT 0 1 0 0 pre_out3 192 - - - 37 OUTPUT 0 1 0 0 R7S1 180 - - - 26 OUTPUT 0 1 0 0 R7S2 186 - - - 27 OUTPUT 0 1 0 0 R7S3 187 - - - 28 OUTPUT 0 1 0 0 R7S4 189 - - - 30 OUTPUT 0 1 0 0 R7S5 191 - - - 35 OUTPUT 0 1 0 0 R7S6 190 - - - 33 OUTPUT 0 1 0 0 R7S7 125 - - F -- OUTPUT 0 0 0 0 SRAM_CEn 131 - - E -- OUTPUT 0 0 0 0 SRAM_OEn 37 - - I -- OUTPUT 0 1 0 0 tst_out Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell ^ = Increased input delay * = PCI I/O is enabled @ = Uses single-pin Clock Enable & = Uses single-pin Output Enable Device-Specific Information:k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt top_pre ** BURIED LOGIC ** Fan-In Fan-Out IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name - 5 - D 46 DFFE + 0 2 0 2 pre_in_fil (fin_reg_q) - 1 - D 46 DFFE + 1 0 0 2 fin_SAMPLES_0 (fin_reg_SAMPLES_0) - 4 - D 46 DFFE + 0 1 0 1 fin_SAMPLES_1 (fin_reg_SAMPLES_1) - 8 - L 52 DFFE 0 4 0 4 mode_sw_f (fmd_reg_q) - 5 - L 52 DFFE 1 1 0 2 fmd_SAMPLES_0 (fmd_reg_SAMPLES_0) - 6 - L 52 DFFE 0 2 0 2 fmd_SAMPLES_1 (fmd_reg_SAMPLES_1) - 7 - L 52 DFFE 0 2 0 1 fmd_SAMPLES_2 (fmd_reg_SAMPLES_2) - 1 - L 38 DFFE 0 4 0 2 inp_sw_f (fmi_reg_q) - 3 - L 38 DFFE 1 1 0 2 fmi_SAMPLES_0 (fmi_reg_SAMPLES_0) - 4 - L 38 DFFE 0 2 0 2 fmi_SAMPLES_1 (fmi_reg_SAMPLES_1) - 5 - L 38 DFFE 0 2 0 1 fmi_SAMPLES_2 (fmi_reg_SAMPLES_2) - 7 - D 38 LCELL 0 4 0 1 nx454_lc (ix510_lc) - 1 - D 38 LCELL 0 4 0 2 nx456_lc (ix511_lc) - 6 - D 41 LCELL 0 4 0 1 nx457_lc (ix512_lc) - 6 - D 38 LCELL 0 4 0 1 nx458_lc (ix513_lc) - 8 - D 38 LCELL 0 4 0 1 nx459_lc (ix514_lc) - 4 - L 37 LCELL 0 5 0 1 nx460_lc (ix515_lc) - 4 - L 45 CASCADE 0 4 0 1 nx461_cas (ix516_cas) - 6 - L 37 LCELL 0 5 0 1 nx462_lc (ix517_lc) - 2 - L 35 LCELL 0 5 0 1 nx464_lc (ix518_lc) - 5 - L 45 LCELL 0 5 0 1 nx465_lc (ix519_lc) - 2 - D 38 LCELL 0 5 0 1 nx466_lc (ix520_lc) - 6 - L 38 LCELL 0 2 0 1 nx467_lc (ix521_lc) - 1 - L 35 CASCADE 0 4 0 1 nx468_cas (ix522_cas) - 3 - L 37 CASCADE 0 4 0 1 nx469_cas (ix523_cas) - 5 - L 37 CASCADE 0 4 0 1 nx470_cas (ix524_cas) - 7 - L 37 CASCADE 0 4 0 1 nx471_cas (ix525_cas) - 8 - L 37 LCELL 0 5 0 1 tst_out_lc (ix535_lc) - 1 - L 37 LCELL 0 4 1 0 R7S_1_lc (ix536_lc) - 4 - L 25 LCELL 0 4 1 0 R7S_2_lc (ix537_lc) - 1 - L 27 LCELL 0 4 1 0 R7S_3_lc (ix538_lc) - 2 - L 27 LCELL 0 4 1 0 R7S_4_lc (ix539_lc) - 1 - L 30 LCELL 0 4 1 0 R7S_5_lc (ix540_lc) - 6 - L 35 LCELL 0 4 1 0 R7S_6_lc (ix541_lc) - 4 - L 34 LCELL 0 4 1 0 R7S_7_lc (ix542_lc) - 4 - D 38 LCELL 0 4 0 2 nx455_lc (ix543_lc) - 3 - D 38 LCELL 0 4 0 2 nx453_lc (ix544_lc) - 8 - D 46 LCELL 0 4 0 1 nx583_lc (ix545_lc) - 1 - L 39 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs0 - 2 - L 39 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs1 - 3 - L 39 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs2 - 4 - L 39 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs3 - 5 - L 39 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs4 - 6 - L 39 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs5 - 7 - L 39 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs6 - 8 - L 39 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs7 - 1 - L 41 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs8 - 2 - L 41 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs9 - 3 - L 41 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs10 - 4 - L 41 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs11 - 5 - L 41 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs12 - 6 - L 41 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs13 - 7 - L 41 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs14 - 8 - L 41 DFFE + 0 0 0 9 |lpm_counter:div_clk_ix7|dffs15 - 1 - L 43 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs16 - 2 - L 43 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs17 - 3 - L 43 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs18 - 4 - L 43 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs19 - 5 - L 43 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs20 - 6 - L 43 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs21 - 7 - L 43 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs22 - 8 - L 43 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs23 - 1 - L 45 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs24 - 2 - L 45 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs25 - 3 - L 45 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs26 - 1 - L 52 DFFE 0 1 0 16 |lpm_counter:mode_ix7|dffs0 - 2 - L 52 DFFE 0 1 0 16 |lpm_counter:mode_ix7|dffs1 - 3 - L 52 DFFE 0 1 0 10 |lpm_counter:mode_ix7|dffs2 - 4 - L 52 DFFE 0 1 0 10 |lpm_counter:mode_ix7|dffs3 - 7 - D 50 OR2 s 0 2 0 1 nx602~3~1 - 2 - L 38 DFFE 0 4 1 1 reg_inp_sel - 6 - D 46 DFFE + 0 1 0 1 pre_in_fil_old (reg_pre_in_fil_old) - 6 - D 50 DFFE + 0 2 1 0 reg_pre_out_i - 4 - D 49 DFFE +s 0 2 1 0 reg_pre_out_i~1 - 7 - D 41 DFFE +s 0 2 1 0 reg_pre_out_i~2 - 8 - D 50 DFFE +s 0 2 1 0 reg_pre_out_i~3 - 2 - D 46 DFFE + 0 2 0 23 sm_0 (reg_sm_0) - 5 - D 38 DFFE + 0 4 0 21 sm_1 (reg_sm_1) - 1 - D 45 DFFE + 0 2 0 3 timer_0 (reg_timer_0) - 1 - D 49 DFFE + 0 3 0 3 timer_1 (reg_timer_1) - 2 - D 49 DFFE + 0 3 0 3 timer_2 (reg_timer_2) - 3 - D 46 DFFE + 0 3 0 3 timer_3 (reg_timer_3) - 3 - D 41 DFFE + 0 3 0 3 timer_4 (reg_timer_4) - 2 - D 41 DFFE + 0 3 0 3 timer_5 (reg_timer_5) - 1 - D 41 DFFE + 0 3 0 3 timer_6 (reg_timer_6) - 4 - D 41 DFFE + 0 3 0 3 timer_7 (reg_timer_7) - 7 - D 46 DFFE + 0 3 0 2 timer_8 (reg_timer_8) - 7 - D 49 DFFE + 0 3 0 2 timer_9 (reg_timer_9) - 6 - D 49 DFFE + 0 3 0 2 timer_10 (reg_timer_10) - 5 - D 41 DFFE + 0 3 0 2 timer_11 (reg_timer_11) - 8 - D 41 DFFE + 0 3 0 2 timer_12 (reg_timer_12) - 8 - D 49 DFFE + 0 3 0 2 timer_13 (reg_timer_13) - 3 - D 49 DFFE + 0 3 0 2 timer_14 (reg_timer_14) - 5 - D 49 DFFE + 0 3 0 2 timer_15 (reg_timer_15) - 3 - D 48 LCELL 0 1 0 1 nx134_lc (result_inc_26_ix37_lc) - 2 - D 45 LCELL 0 1 0 1 nx609_lc (result_inc_26_ix41_lc) - 3 - D 45 LCELL 0 1 0 1 nx611_lc (result_inc_26_ix45_lc) - 4 - D 45 LCELL 0 1 0 1 nx613_lc (result_inc_26_ix49_lc) - 5 - D 45 LCELL 0 1 0 1 nx615_lc (result_inc_26_ix53_lc) - 6 - D 45 LCELL 0 1 0 1 nx617_lc (result_inc_26_ix57_lc) - 7 - D 45 LCELL 0 1 0 1 nx619_lc (result_inc_26_ix61_lc) - 8 - D 45 LCELL 0 1 0 1 nx621_lc (result_inc_26_ix65_lc) - 1 - D 47 LCELL 0 1 0 1 nx623_lc (result_inc_26_ix69_lc) - 2 - D 47 LCELL 0 1 0 1 nx625_lc (result_inc_26_ix73_lc) - 3 - D 47 LCELL 0 1 0 1 nx627_lc (result_inc_26_ix77_lc) - 4 - D 47 LCELL 0 1 0 1 nx629_lc (result_inc_26_ix81_lc) - 5 - D 47 LCELL 0 1 0 1 nx631_lc (result_inc_26_ix85_lc) - 6 - D 47 LCELL 0 1 0 1 nx633_lc (result_inc_26_ix89_lc) - 7 - D 47 LCELL 0 1 0 1 nx635_lc (result_inc_26_ix93_lc) - 8 - D 47 LCELL 0 1 0 1 nx119_lc (result_inc_26_ix97_lc) - 2 - L 37 SOFT s r 0 1 1 0 tst_out~fit~in1 - 1 - D 45 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix39_carry_sum|:31 - 2 - D 45 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix41_carry_sum|:31 - 3 - D 45 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix45_carry_sum|:31 - 4 - D 45 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix49_carry_sum|:31 - 5 - D 45 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix53_carry_sum|:31 - 6 - D 45 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix57_carry_sum|:31 - 7 - D 45 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix61_carry_sum|:31 - 8 - D 45 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix65_carry_sum|:31 - 1 - D 47 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix69_carry_sum|:31 - 2 - D 47 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix73_carry_sum|:31 - 3 - D 47 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix77_carry_sum|:31 - 4 - D 47 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix81_carry_sum|:31 - 5 - D 47 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix85_carry_sum|:31 - 6 - D 47 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix89_carry_sum|:31 - 7 - D 47 CARRY 0 2 0 1 |carry_sum:result_inc_26_ix93_carry_sum|:31 - 1 - L 39 CARRY 0 0 0 1 |lpm_counter:div_clk_ix7|carrybit1 - 2 - L 39 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit2 - 3 - L 39 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit3 - 4 - L 39 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit4 - 5 - L 39 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit5 - 6 - L 39 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit6 - 7 - L 39 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit7 - 8 - L 39 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit8 - 1 - L 41 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit9 - 2 - L 41 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit10 - 3 - L 41 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit11 - 4 - L 41 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit12 - 5 - L 41 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit13 - 6 - L 41 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit14 - 7 - L 41 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit15 - 8 - L 41 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit16 - 1 - L 43 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit17 - 2 - L 43 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit18 - 3 - L 43 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit19 - 4 - L 43 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit20 - 5 - L 43 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit21 - 6 - L 43 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit22 - 7 - L 43 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit23 - 8 - L 43 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit24 - 1 - L 45 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit25 - 2 - L 45 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit26 - 1 - L 52 CARRY 0 0 0 1 |lpm_counter:mode_ix7|carrybit1 - 2 - L 52 CARRY 0 1 0 1 |lpm_counter:mode_ix7|carrybit2 - 3 - L 52 CARRY 0 1 0 1 |lpm_counter:mode_ix7|carrybit3 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell ^ = Increased input delay * = PCI I/O is enabled p = Packed register Device-Specific Information:k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt top_pre ** FASTTRACK INTERCONNECT UTILIZATION ** Row FastTrack Interconnect: Global Left Half- Right Half- FastTrack FastTrack FastTrack Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) C: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%) D: 38/208( 18%) 0/104( 0%) 3/104( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%) E: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%) F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%) G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) I: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%) J: 1/208( 0%) 0/104( 0%) 0/104( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%) K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) L: 5/208( 2%) 0/104( 0%) 15/104( 14%) 0/16( 0%) 0/16( 0%) 0/16( 0%) Column FastTrack Interconnect: FastTrack Column Interconnect Input Pins Output Pins Bidir Pins 01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 26: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 27: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 30: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 33: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 37: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 38: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 49: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 50: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 51: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) Device-Specific Information:k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt top_pre ** CLOCK SIGNALS ** Type Fan-out Name INPUT 53 CLK DFF 10 |lpm_counter:div_clk_ix7|dffs15 DFF 5 mode_sw_f DFF 3 inp_sw_f Device-Specific Information:k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt top_pre ** CARRY CHAINS ** Type Member Length Member Name: SUM, (CARRY) UP/DOWN COUNTER 1 |lpm_counter:div_clk_ix7|dffs0, (|lpm_counter:div_clk_ix7|carrybit1) UP/DOWN COUNTER 2 |lpm_counter:div_clk_ix7|dffs1, (|lpm_counter:div_clk_ix7|carrybit2) UP/DOWN COUNTER 3 |lpm_counter:div_clk_ix7|dffs2, (|lpm_counter:div_clk_ix7|carrybit3) UP/DOWN COUNTER 4 |lpm_counter:div_clk_ix7|dffs3, (|lpm_counter:div_clk_ix7|carrybit4) UP/DOWN COUNTER 5 |lpm_counter:div_clk_ix7|dffs4, (|lpm_counter:div_clk_ix7|carrybit5) UP/DOWN COUNTER 6 |lpm_counter:div_clk_ix7|dffs5, (|lpm_counter:div_clk_ix7|carrybit6) UP/DOWN COUNTER 7 |lpm_counter:div_clk_ix7|dffs6, (|lpm_counter:div_clk_ix7|carrybit7) UP/DOWN COUNTER 8 |lpm_counter:div_clk_ix7|dffs7, (|lpm_counter:div_clk_ix7|carrybit8) UP/DOWN COUNTER 9 |lpm_counter:div_clk_ix7|dffs8, (|lpm_counter:div_clk_ix7|carrybit9) UP/DOWN COUNTER 10 |lpm_counter:div_clk_ix7|dffs9, (|lpm_counter:div_clk_ix7|carrybit10) UP/DOWN COUNTER 11 |lpm_counter:div_clk_ix7|dffs10, (|lpm_counter:div_clk_ix7|carrybit11) UP/DOWN COUNTER 12 |lpm_counter:div_clk_ix7|dffs11, (|lpm_counter:div_clk_ix7|carrybit12) UP/DOWN COUNTER 13 |lpm_counter:div_clk_ix7|dffs12, (|lpm_counter:div_clk_ix7|carrybit13) UP/DOWN COUNTER 14 |lpm_counter:div_clk_ix7|dffs13, (|lpm_counter:div_clk_ix7|carrybit14) UP/DOWN COUNTER 15 |lpm_counter:div_clk_ix7|dffs14, (|lpm_counter:div_clk_ix7|carrybit15) UP/DOWN COUNTER 16 |lpm_counter:div_clk_ix7|dffs15, (|lpm_counter:div_clk_ix7|carrybit16) UP/DOWN COUNTER 17 |lpm_counter:div_clk_ix7|dffs16, (|lpm_counter:div_clk_ix7|carrybit17) UP/DOWN COUNTER 18 |lpm_counter:div_clk_ix7|dffs17, (|lpm_counter:div_clk_ix7|carrybit18) UP/DOWN COUNTER 19 |lpm_counter:div_clk_ix7|dffs18, (|lpm_counter:div_clk_ix7|carrybit19) UP/DOWN COUNTER 20 |lpm_counter:div_clk_ix7|dffs19, (|lpm_counter:div_clk_ix7|carrybit20) UP/DOWN COUNTER 21 |lpm_counter:div_clk_ix7|dffs20, (|lpm_counter:div_clk_ix7|carrybit21) UP/DOWN COUNTER 22 |lpm_counter:div_clk_ix7|dffs21, (|lpm_counter:div_clk_ix7|carrybit22) UP/DOWN COUNTER 23 |lpm_counter:div_clk_ix7|dffs22, (|lpm_counter:div_clk_ix7|carrybit23) UP/DOWN COUNTER 24 |lpm_counter:div_clk_ix7|dffs23, (|lpm_counter:div_clk_ix7|carrybit24) UP/DOWN COUNTER 25 |lpm_counter:div_clk_ix7|dffs24, (|lpm_counter:div_clk_ix7|carrybit25) UP/DOWN COUNTER 26 |lpm_counter:div_clk_ix7|dffs25, (|lpm_counter:div_clk_ix7|carrybit26) NORMAL 27 |lpm_counter:div_clk_ix7|dffs26 CLEARABLE COUNTER 1 timer_0, (|carry_sum:result_inc_26_ix39_carry_sum|:31) ARITHMETIC 2 nx609_lc, (|carry_sum:result_inc_26_ix41_carry_sum|:31) ARITHMETIC 3 nx611_lc, (|carry_sum:result_inc_26_ix45_carry_sum|:31) ARITHMETIC 4 nx613_lc, (|carry_sum:result_inc_26_ix49_carry_sum|:31) ARITHMETIC 5 nx615_lc, (|carry_sum:result_inc_26_ix53_carry_sum|:31) ARITHMETIC 6 nx617_lc, (|carry_sum:result_inc_26_ix57_carry_sum|:31) ARITHMETIC 7 nx619_lc, (|carry_sum:result_inc_26_ix61_carry_sum|:31) ARITHMETIC 8 nx621_lc, (|carry_sum:result_inc_26_ix65_carry_sum|:31) ARITHMETIC 9 nx623_lc, (|carry_sum:result_inc_26_ix69_carry_sum|:31) ARITHMETIC 10 nx625_lc, (|carry_sum:result_inc_26_ix73_carry_sum|:31) ARITHMETIC 11 nx627_lc, (|carry_sum:result_inc_26_ix77_carry_sum|:31) ARITHMETIC 12 nx629_lc, (|carry_sum:result_inc_26_ix81_carry_sum|:31) ARITHMETIC 13 nx631_lc, (|carry_sum:result_inc_26_ix85_carry_sum|:31) ARITHMETIC 14 nx633_lc, (|carry_sum:result_inc_26_ix89_carry_sum|:31) ARITHMETIC 15 nx635_lc, (|carry_sum:result_inc_26_ix93_carry_sum|:31) NORMAL 16 nx119_lc UP/DOWN COUNTER 1 |lpm_counter:mode_ix7|dffs0, (|lpm_counter:mode_ix7|carrybit1) UP/DOWN COUNTER 2 |lpm_counter:mode_ix7|dffs1, (|lpm_counter:mode_ix7|carrybit2) UP/DOWN COUNTER 3 |lpm_counter:mode_ix7|dffs2, (|lpm_counter:mode_ix7|carrybit3) NORMAL 4 |lpm_counter:mode_ix7|dffs3 Device-Specific Information:k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt top_pre ** EQUATIONS ** CLK : INPUT; inp_sw : INPUT; mode_sw : INPUT; pre_in : INPUT; -- Node name is 'ADC_OEn' from file "top_pre.edf" line 115 -- Equation name is 'ADC_OEn', type is output ADC_OEn = VCC; -- Node name is 'fin_reg_SAMPLES_0' = 'fin_SAMPLES_0' from file "top_pre.edf" line 276 -- Equation name is 'fin_reg_SAMPLES_0', location is LC1_D46, type is buried. fin_SAMPLES_0 = DFFE( pre_in, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'fin_reg_SAMPLES_1' = 'fin_SAMPLES_1' from file "top_pre.edf" line 275 -- Equation name is 'fin_reg_SAMPLES_1', location is LC4_D46, type is buried. fin_SAMPLES_1 = DFFE( fin_SAMPLES_0, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'fmd_reg_SAMPLES_0' = 'fmd_SAMPLES_0' from file "top_pre.edf" line 269 -- Equation name is 'fmd_reg_SAMPLES_0', location is LC5_L52, type is buried. fmd_SAMPLES_0 = DFFE( mode_sw, _LC8_L41, VCC, VCC, VCC); -- Node name is 'fmd_reg_SAMPLES_1' = 'fmd_SAMPLES_1' from file "top_pre.edf" line 268 -- Equation name is 'fmd_reg_SAMPLES_1', location is LC6_L52, type is buried. fmd_SAMPLES_1 = DFFE( fmd_SAMPLES_0, _LC8_L41, VCC, VCC, VCC); -- Node name is 'fmd_reg_SAMPLES_2' = 'fmd_SAMPLES_2' from file "top_pre.edf" line 267 -- Equation name is 'fmd_reg_SAMPLES_2', location is LC7_L52, type is buried. fmd_SAMPLES_2 = DFFE( fmd_SAMPLES_1, _LC8_L41, VCC, VCC, VCC); -- Node name is 'fmi_reg_SAMPLES_0' = 'fmi_SAMPLES_0' from file "top_pre.edf" line 273 -- Equation name is 'fmi_reg_SAMPLES_0', location is LC3_L38, type is buried. fmi_SAMPLES_0 = DFFE( inp_sw, _LC8_L41, VCC, VCC, VCC); -- Node name is 'fmi_reg_SAMPLES_1' = 'fmi_SAMPLES_1' from file "top_pre.edf" line 272 -- Equation name is 'fmi_reg_SAMPLES_1', location is LC4_L38, type is buried. fmi_SAMPLES_1 = DFFE( fmi_SAMPLES_0, _LC8_L41, VCC, VCC, VCC); -- Node name is 'fmi_reg_SAMPLES_2' = 'fmi_SAMPLES_2' from file "top_pre.edf" line 271 -- Equation name is 'fmi_reg_SAMPLES_2', location is LC5_L38, type is buried. fmi_SAMPLES_2 = DFFE( fmi_SAMPLES_1, _LC8_L41, VCC, VCC, VCC); -- Node name is 'fmi_reg_q' = 'inp_sw_f' from file "top_pre.edf" line 270 -- Equation name is 'fmi_reg_q', location is LC1_L38, type is buried. inp_sw_f = DFFE( _EQ001, _LC8_L41, VCC, VCC, VCC); _EQ001 = fmi_SAMPLES_0 & fmi_SAMPLES_1 & fmi_SAMPLES_2 # fmi_SAMPLES_2 & inp_sw_f # fmi_SAMPLES_1 & inp_sw_f # fmi_SAMPLES_0 & inp_sw_f; -- Node name is 'LED_RED' from file "top_pre.edf" line 113 -- Equation name is 'LED_RED', type is output LED_RED = reg_inp_sel; -- Node name is 'LVDS_EN' from file "top_pre.edf" line 114 -- Equation name is 'LVDS_EN', type is output LVDS_EN = GND; -- Node name is 'fmd_reg_q' = 'mode_sw_f' from file "top_pre.edf" line 266 -- Equation name is 'fmd_reg_q', location is LC8_L52, type is buried. mode_sw_f = DFFE( _EQ002, _LC8_L41, VCC, VCC, VCC); _EQ002 = fmd_SAMPLES_1 & mode_sw_f # fmd_SAMPLES_0 & mode_sw_f # fmd_SAMPLES_2 & mode_sw_f # fmd_SAMPLES_0 & fmd_SAMPLES_1 & fmd_SAMPLES_2; -- Node name is 'result_inc_26_ix97_lc' = 'nx119_lc' from file "top_pre.edf" line 494 -- Equation name is 'result_inc_26_ix97_lc', location is LC8_D47, type is buried. nx119_lc = LCELL( _EQ003); _EQ003 = _LC7_D47_CARRY & !timer_15 # !_LC7_D47_CARRY & timer_15; -- Node name is 'result_inc_26_ix37_lc' = 'nx134_lc' from file "top_pre.edf" line 479 -- Equation name is 'result_inc_26_ix37_lc', location is LC3_D48, type is buried. nx134_lc = LCELL(!timer_0); -- Node name is 'ix544_lc' = 'nx453_lc' from file "top_pre.edf" line 524 -- Equation name is 'ix544_lc', location is LC3_D38, type is buried. nx453_lc = LCELL( _EQ004C); _EQ004C = _EQ004; _EQ004 = !timer_12 & !timer_13 & !timer_14 & !timer_15; -- Node name is 'ix510_lc' = 'nx454_lc' from file "top_pre.edf" line 495 -- Equation name is 'ix510_lc', location is LC7_D38, type is buried. nx454_lc = LCELL( _EQ005); _EQ005 = timer_6 # !timer_7 # timer_5 # !timer_4; -- Node name is 'ix543_lc' = 'nx455_lc' from file "top_pre.edf" line 522 -- Equation name is 'ix543_lc', location is LC4_D38, type is buried. nx455_lc = LCELL( _EQ006C); _EQ006C = _EQ006 & CASCADE( _EQ004C); _EQ006 = nx456_lc & !nx457_lc & !nx458_lc; -- Node name is 'ix511_lc' = 'nx456_lc' from file "top_pre.edf" line 497 -- Equation name is 'ix511_lc', location is LC1_D38, type is buried. nx456_lc = LCELL( _EQ007C); _EQ007C = _EQ007; _EQ007 = !timer_8 & !timer_9 & !timer_10 & !timer_11; -- Node name is 'ix512_lc' = 'nx457_lc' from file "top_pre.edf" line 498 -- Equation name is 'ix512_lc', location is LC6_D41, type is buried. nx457_lc = LCELL( _EQ008); _EQ008 = timer_6 # timer_7 # !timer_5 # !timer_4; -- Node name is 'ix513_lc' = 'nx458_lc' from file "top_pre.edf" line 499 -- Equation name is 'ix513_lc', location is LC6_D38, type is buried. nx458_lc = LCELL( _EQ009); _EQ009 = !timer_1 # timer_0 # timer_3 # timer_2; -- Node name is 'ix514_lc' = 'nx459_lc' from file "top_pre.edf" line 500 -- Equation name is 'ix514_lc', location is LC8_D38, type is buried. nx459_lc = LCELL( _EQ010); _EQ010 = sm_0 # nx466_lc & timer_2 & !timer_3; -- Node name is 'ix515_lc' = 'nx460_lc' from file "top_pre.edf" line 501 -- Equation name is 'ix515_lc', location is LC4_L37, type is buried. nx460_lc = LCELL( _EQ011C); _EQ011C = _EQ011 & CASCADE( _EQ012C); _EQ011 = !_LC1_L52 & _LC7_L41 # _LC1_L52 & _LC8_L41 # !_LC2_L52; -- Node name is 'ix516_cas' = 'nx461_cas' from file "top_pre.edf" line 502 -- Equation name is 'ix516_cas', location is LC4_L45, type is buried. nx461_cas = LCELL( _EQ013C); _EQ013C = _EQ013; _EQ013 = _LC1_L52 & !_LC2_L52 # !_LC1_L45 & !_LC2_L52 # !inp_sw_f & _LC2_L52 # !_LC1_L52 & _LC2_L52; -- Node name is 'ix517_lc' = 'nx462_lc' from file "top_pre.edf" line 503 -- Equation name is 'ix517_lc', location is LC6_L37, type is buried. nx462_lc = LCELL( _EQ014C); _EQ014C = _EQ014 & CASCADE( _EQ015C); _EQ014 = !_LC1_L52 & _LC7_L43 # _LC1_L52 & _LC8_L43 # !_LC2_L52; -- Node name is 'ix518_lc' = 'nx464_lc' from file "top_pre.edf" line 504 -- Equation name is 'ix518_lc', location is LC2_L35, type is buried. nx464_lc = LCELL( _EQ016C); _EQ016C = _EQ016 & CASCADE( _EQ017C); _EQ016 = !_LC1_L52 & _LC3_L43 # _LC1_L52 & _LC4_L43 # !_LC2_L52; -- Node name is 'ix519_lc' = 'nx465_lc' from file "top_pre.edf" line 505 -- Equation name is 'ix519_lc', location is LC5_L45, type is buried. nx465_lc = LCELL( _EQ018C); _EQ018C = _EQ018 & CASCADE( _EQ013C); _EQ018 = _LC1_L52 & _LC2_L52 # _LC2_L52 & !_LC3_L45 # !_LC1_L52 & !_LC2_L52 # !_LC2_L45 & !_LC2_L52; -- Node name is 'ix520_lc' = 'nx466_lc' from file "top_pre.edf" line 506 -- Equation name is 'ix520_lc', location is LC2_D38, type is buried. nx466_lc = LCELL( _EQ019C); _EQ019C = _EQ019 & CASCADE( _EQ007C); _EQ019 = nx453_lc & !nx454_lc & !timer_0 & timer_1; -- Node name is 'ix521_lc' = 'nx467_lc' from file "top_pre.edf" line 507 -- Equation name is 'ix521_lc', location is LC6_L38, type is buried. nx467_lc = LCELL( _EQ020); _EQ020 = !_LC2_L52 # !_LC3_L52; -- Node name is 'ix522_cas' = 'nx468_cas' from file "top_pre.edf" line 508 -- Equation name is 'ix522_cas', location is LC1_L35, type is buried. nx468_cas = LCELL( _EQ017C); _EQ017C = _EQ017; _EQ017 = _LC1_L43 & !_LC1_L52 # _LC1_L52 & _LC2_L43 # _LC2_L52; -- Node name is 'ix523_cas' = 'nx469_cas' from file "top_pre.edf" line 509 -- Equation name is 'ix523_cas', location is LC3_L37, type is buried. nx469_cas = LCELL( _EQ012C); _EQ012C = _EQ012; _EQ012 = !_LC1_L52 & _LC5_L41 # _LC1_L52 & _LC6_L41 # _LC2_L52; -- Node name is 'ix524_cas' = 'nx470_cas' from file "top_pre.edf" line 510 -- Equation name is 'ix524_cas', location is LC5_L37, type is buried. nx470_cas = LCELL( _EQ015C); _EQ015C = _EQ015; _EQ015 = !_LC1_L52 & _LC5_L43 # _LC1_L52 & _LC6_L43 # _LC2_L52; -- Node name is 'ix525_cas' = 'nx471_cas' from file "top_pre.edf" line 511 -- Equation name is 'ix525_cas', location is LC7_L37, type is buried. nx471_cas = LCELL( _EQ021C); _EQ021C = _EQ021; _EQ021 = _LC3_L52 & nx464_lc # !_LC3_L52 & nx460_lc # _LC4_L52; -- Node name is 'ix545_lc' = 'nx583_lc' from file "top_pre.edf" line 525 -- Equation name is 'ix545_lc', location is LC8_D46, type is buried. nx583_lc = LCELL( _EQ022); _EQ022 = pre_in_fil & !pre_in_fil_old & !sm_0 & !sm_1; -- Node name is 'nx602~3~1' from file "top_pre.edf" line 439 -- Equation name is 'nx602~3~1', location is LC7_D50, type is buried. -- synthesized logic cell _LC7_D50 = LCELL( _EQ023); _EQ023 = sm_0 # sm_1; -- Node name is 'result_inc_26_ix41_lc' = 'nx609_lc' from file "top_pre.edf" line 480 -- Equation name is 'result_inc_26_ix41_lc', location is LC2_D45, type is buried. nx609_lc = LCELL( _EQ024); _EQ024 = _LC1_D45_CARRY & !timer_1 # !_LC1_D45_CARRY & timer_1; -- Node name is 'result_inc_26_ix45_lc' = 'nx611_lc' from file "top_pre.edf" line 481 -- Equation name is 'result_inc_26_ix45_lc', location is LC3_D45, type is buried. nx611_lc = LCELL( _EQ025); _EQ025 = _LC2_D45_CARRY & !timer_2 # !_LC2_D45_CARRY & timer_2; -- Node name is 'result_inc_26_ix49_lc' = 'nx613_lc' from file "top_pre.edf" line 482 -- Equation name is 'result_inc_26_ix49_lc', location is LC4_D45, type is buried. nx613_lc = LCELL( _EQ026); _EQ026 = _LC3_D45_CARRY & !timer_3 # !_LC3_D45_CARRY & timer_3; -- Node name is 'result_inc_26_ix53_lc' = 'nx615_lc' from file "top_pre.edf" line 483 -- Equation name is 'result_inc_26_ix53_lc', location is LC5_D45, type is buried. nx615_lc = LCELL( _EQ027); _EQ027 = _LC4_D45_CARRY & !timer_4 # !_LC4_D45_CARRY & timer_4; -- Node name is 'result_inc_26_ix57_lc' = 'nx617_lc' from file "top_pre.edf" line 484 -- Equation name is 'result_inc_26_ix57_lc', location is LC6_D45, type is buried. nx617_lc = LCELL( _EQ028); _EQ028 = _LC5_D45_CARRY & !timer_5 # !_LC5_D45_CARRY & timer_5; -- Node name is 'result_inc_26_ix61_lc' = 'nx619_lc' from file "top_pre.edf" line 485 -- Equation name is 'result_inc_26_ix61_lc', location is LC7_D45, type is buried. nx619_lc = LCELL( _EQ029); _EQ029 = _LC6_D45_CARRY & !timer_6 # !_LC6_D45_CARRY & timer_6; -- Node name is 'result_inc_26_ix65_lc' = 'nx621_lc' from file "top_pre.edf" line 486 -- Equation name is 'result_inc_26_ix65_lc', location is LC8_D45, type is buried. nx621_lc = LCELL( _EQ030); _EQ030 = _LC7_D45_CARRY & !timer_7 # !_LC7_D45_CARRY & timer_7; -- Node name is 'result_inc_26_ix69_lc' = 'nx623_lc' from file "top_pre.edf" line 487 -- Equation name is 'result_inc_26_ix69_lc', location is LC1_D47, type is buried. nx623_lc = LCELL( _EQ031); _EQ031 = _LC8_D45_CARRY & !timer_8 # !_LC8_D45_CARRY & timer_8; -- Node name is 'result_inc_26_ix73_lc' = 'nx625_lc' from file "top_pre.edf" line 488 -- Equation name is 'result_inc_26_ix73_lc', location is LC2_D47, type is buried. nx625_lc = LCELL( _EQ032); _EQ032 = _LC1_D47_CARRY & !timer_9 # !_LC1_D47_CARRY & timer_9; -- Node name is 'result_inc_26_ix77_lc' = 'nx627_lc' from file "top_pre.edf" line 489 -- Equation name is 'result_inc_26_ix77_lc', location is LC3_D47, type is buried. nx627_lc = LCELL( _EQ033); _EQ033 = _LC2_D47_CARRY & !timer_10 # !_LC2_D47_CARRY & timer_10; -- Node name is 'result_inc_26_ix81_lc' = 'nx629_lc' from file "top_pre.edf" line 490 -- Equation name is 'result_inc_26_ix81_lc', location is LC4_D47, type is buried. nx629_lc = LCELL( _EQ034); _EQ034 = _LC3_D47_CARRY & !timer_11 # !_LC3_D47_CARRY & timer_11; -- Node name is 'result_inc_26_ix85_lc' = 'nx631_lc' from file "top_pre.edf" line 491 -- Equation name is 'result_inc_26_ix85_lc', location is LC5_D47, type is buried. nx631_lc = LCELL( _EQ035); _EQ035 = _LC4_D47_CARRY & !timer_12 # !_LC4_D47_CARRY & timer_12; -- Node name is 'result_inc_26_ix89_lc' = 'nx633_lc' from file "top_pre.edf" line 492 -- Equation name is 'result_inc_26_ix89_lc', location is LC6_D47, type is buried. nx633_lc = LCELL( _EQ036); _EQ036 = _LC5_D47_CARRY & !timer_13 # !_LC5_D47_CARRY & timer_13; -- Node name is 'result_inc_26_ix93_lc' = 'nx635_lc' from file "top_pre.edf" line 493 -- Equation name is 'result_inc_26_ix93_lc', location is LC7_D47, type is buried. nx635_lc = LCELL( _EQ037); _EQ037 = _LC6_D47_CARRY & !timer_14 # !_LC6_D47_CARRY & timer_14; -- Node name is 'fin_reg_q' = 'pre_in_fil' from file "top_pre.edf" line 274 -- Equation name is 'fin_reg_q', location is LC5_D46, type is buried. pre_in_fil = DFFE( _EQ038, GLOBAL( CLK), VCC, VCC, VCC); _EQ038 = fin_SAMPLES_0 & pre_in_fil # fin_SAMPLES_1 & pre_in_fil # fin_SAMPLES_0 & fin_SAMPLES_1; -- Node name is 'reg_pre_in_fil_old' = 'pre_in_fil_old' from file "top_pre.edf" line 265 -- Equation name is 'reg_pre_in_fil_old', location is LC6_D46, type is buried. pre_in_fil_old = DFFE( pre_in_fil, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'pre_out0' from file "top_pre.edf" line 108 -- Equation name is 'pre_out0', type is output pre_out0 = _LC8_D50; -- Node name is 'pre_out1' from file "top_pre.edf" line 109 -- Equation name is 'pre_out1', type is output pre_out1 = _LC7_D41; -- Node name is 'pre_out2' from file "top_pre.edf" line 110 -- Equation name is 'pre_out2', type is output pre_out2 = _LC4_D49; -- Node name is 'pre_out3' from file "top_pre.edf" line 111 -- Equation name is 'pre_out3', type is output pre_out3 = reg_pre_out_i; -- Node name is 'reg_inp_sel' from file "top_pre.edf" line 245 -- Equation name is 'reg_inp_sel', location is LC2_L38, type is buried. reg_inp_sel = DFFE( _EQ039, inp_sw_f, VCC, VCC, VCC); _EQ039 = nx467_lc & !reg_inp_sel # !_LC1_L52 & !reg_inp_sel # !_LC4_L52 & !reg_inp_sel # _LC1_L52 & _LC4_L52 & !nx467_lc & reg_inp_sel; -- Node name is 'reg_pre_out_i' from file "top_pre.edf" line 264 -- Equation name is 'reg_pre_out_i', location is LC6_D50, type is buried. reg_pre_out_i = DFFE( _EQ040, GLOBAL( CLK), VCC, VCC, VCC); _EQ040 = sm_0 # sm_1; -- Node name is 'reg_pre_out_i~1' from file "top_pre.edf" line 264 -- Equation name is 'reg_pre_out_i~1', location is LC4_D49, type is buried. -- synthesized logic cell _LC4_D49 = DFFE( _EQ041, GLOBAL( CLK), VCC, VCC, VCC); _EQ041 = sm_0 # sm_1; -- Node name is 'reg_pre_out_i~2' from file "top_pre.edf" line 264 -- Equation name is 'reg_pre_out_i~2', location is LC7_D41, type is buried. -- synthesized logic cell _LC7_D41 = DFFE( _EQ042, GLOBAL( CLK), VCC, VCC, VCC); _EQ042 = sm_0 # sm_1; -- Node name is 'reg_pre_out_i~3' from file "top_pre.edf" line 264 -- Equation name is 'reg_pre_out_i~3', location is LC8_D50, type is buried. -- synthesized logic cell _LC8_D50 = DFFE( _EQ043, GLOBAL( CLK), VCC, VCC, VCC); _EQ043 = sm_0 # sm_1; -- Node name is 'ix536_lc' = 'R7S_1_lc' from file "top_pre.edf" line 514 -- Equation name is 'ix536_lc', location is LC1_L37, type is buried. R7S_1_lc = LCELL( _EQ044); _EQ044 = _LC1_L52 & !_LC2_L52 & _LC3_L52 & _LC4_L52 # !_LC1_L52 & !_LC2_L52 & _LC3_L52 & !_LC4_L52 # _LC1_L52 & !_LC2_L52 & !_LC3_L52 & !_LC4_L52 # _LC1_L52 & _LC2_L52 & !_LC3_L52 & _LC4_L52; -- Node name is 'R7S1' from file "top_pre.edf" line 112 -- Equation name is 'R7S1', type is output R7S1 = R7S_1_lc; -- Node name is 'ix537_lc' = 'R7S_2_lc' from file "top_pre.edf" line 515 -- Equation name is 'ix537_lc', location is LC4_L25, type is buried. R7S_2_lc = LCELL( _EQ045); _EQ045 = _LC1_L52 & !_LC2_L52 & _LC3_L52 & !_LC4_L52 # !_LC1_L52 & _LC3_L52 & _LC4_L52 # _LC1_L52 & _LC2_L52 & _LC4_L52 # !_LC1_L52 & _LC2_L52 & _LC3_L52; -- Node name is 'R7S2' from file "top_pre.edf" line 112 -- Equation name is 'R7S2', type is output R7S2 = R7S_2_lc; -- Node name is 'ix538_lc' = 'R7S_3_lc' from file "top_pre.edf" line 516 -- Equation name is 'ix538_lc', location is LC1_L27, type is buried. R7S_3_lc = LCELL( _EQ046); _EQ046 = !_LC1_L52 & _LC3_L52 & _LC4_L52 # !_LC1_L52 & _LC2_L52 & !_LC3_L52 & !_LC4_L52 # _LC2_L52 & _LC3_L52 & _LC4_L52; -- Node name is 'R7S3' from file "top_pre.edf" line 112 -- Equation name is 'R7S3', type is output R7S3 = R7S_3_lc; -- Node name is 'ix539_lc' = 'R7S_4_lc' from file "top_pre.edf" line 517 -- Equation name is 'ix539_lc', location is LC2_L27, type is buried. R7S_4_lc = LCELL( _EQ047); _EQ047 = _LC1_L52 & _LC2_L52 & _LC3_L52 # !_LC1_L52 & _LC2_L52 & !_LC3_L52 & _LC4_L52 # _LC1_L52 & !_LC2_L52 & !_LC3_L52 # !_LC1_L52 & !_LC2_L52 & _LC3_L52 & !_LC4_L52; -- Node name is 'R7S4' from file "top_pre.edf" line 112 -- Equation name is 'R7S4', type is output R7S4 = R7S_4_lc; -- Node name is 'ix540_lc' = 'R7S_5_lc' from file "top_pre.edf" line 518 -- Equation name is 'ix540_lc', location is LC1_L30, type is buried. R7S_5_lc = LCELL( _EQ048); _EQ048 = _LC1_L52 & !_LC2_L52 & !_LC3_L52 # !_LC2_L52 & _LC3_L52 & !_LC4_L52 # _LC1_L52 & !_LC4_L52; -- Node name is 'R7S5' from file "top_pre.edf" line 112 -- Equation name is 'R7S5', type is output R7S5 = R7S_5_lc; -- Node name is 'ix541_lc' = 'R7S_6_lc' from file "top_pre.edf" line 519 -- Equation name is 'ix541_lc', location is LC6_L35, type is buried. R7S_6_lc = LCELL( _EQ049); _EQ049 = _LC1_L52 & !_LC3_L52 & !_LC4_L52 # _LC1_L52 & _LC2_L52 & !_LC4_L52 # _LC2_L52 & !_LC3_L52 & !_LC4_L52 # _LC1_L52 & !_LC2_L52 & _LC3_L52 & _LC4_L52; -- Node name is 'R7S6' from file "top_pre.edf" line 112 -- Equation name is 'R7S6', type is output R7S6 = R7S_6_lc; -- Node name is 'ix542_lc' = 'R7S_7_lc' from file "top_pre.edf" line 520 -- Equation name is 'ix542_lc', location is LC4_L34, type is buried. R7S_7_lc = LCELL( _EQ050); _EQ050 = _LC1_L52 & _LC2_L52 & _LC3_L52 & !_LC4_L52 # !_LC1_L52 & !_LC2_L52 & _LC3_L52 & _LC4_L52 # !_LC2_L52 & !_LC3_L52 & !_LC4_L52; -- Node name is 'R7S7' from file "top_pre.edf" line 112 -- Equation name is 'R7S7', type is output R7S7 = R7S_7_lc; -- Node name is 'reg_sm_0' = 'sm_0' from file "top_pre.edf" line 247 -- Equation name is 'reg_sm_0', location is LC2_D46, type is buried. sm_0 = DFFE( _EQ051, GLOBAL( CLK), VCC, VCC, VCC); _EQ051 = !nx455_lc & sm_0 # nx583_lc; -- Node name is 'reg_sm_1' = 'sm_1' from file "top_pre.edf" line 246 -- Equation name is 'reg_sm_1', location is LC5_D38, type is buried. sm_1 = DFFE( _EQ052C, GLOBAL( CLK), VCC, VCC, nx459_lc); _EQ052C = _EQ052 & CASCADE( _EQ006C); _EQ052 = !reg_inp_sel & sm_0; -- Node name is 'SRAM_CEn' from file "top_pre.edf" line 116 -- Equation name is 'SRAM_CEn', type is output SRAM_CEn = VCC; -- Node name is 'SRAM_OEn' from file "top_pre.edf" line 117 -- Equation name is 'SRAM_OEn', type is output SRAM_OEn = VCC; -- Node name is 'reg_timer_0' = 'timer_0' from file "top_pre.edf" line 263 -- Equation name is 'reg_timer_0', location is LC1_D45, type is buried. -- timer_0 is in Clearable Counter Mode -- synchronous clear = _LC7_D50 timer_0 = DFFE( nx134_lc & _LC7_D50, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'reg_timer_1' = 'timer_1' from file "top_pre.edf" line 262 -- Equation name is 'reg_timer_1', location is LC1_D49, type is buried. timer_1 = DFFE( _EQ053, GLOBAL( CLK), VCC, VCC, VCC); _EQ053 = nx609_lc & sm_0 # nx609_lc & sm_1; -- Node name is 'reg_timer_2' = 'timer_2' from file "top_pre.edf" line 261 -- Equation name is 'reg_timer_2', location is LC2_D49, type is buried. timer_2 = DFFE( _EQ054, GLOBAL( CLK), VCC, VCC, VCC); _EQ054 = nx611_lc & sm_0 # nx611_lc & sm_1; -- Node name is 'reg_timer_3' = 'timer_3' from file "top_pre.edf" line 260 -- Equation name is 'reg_timer_3', location is LC3_D46, type is buried. timer_3 = DFFE( _EQ055, GLOBAL( CLK), VCC, VCC, VCC); _EQ055 = nx613_lc & sm_0 # nx613_lc & sm_1; -- Node name is 'reg_timer_4' = 'timer_4' from file "top_pre.edf" line 259 -- Equation name is 'reg_timer_4', location is LC3_D41, type is buried. timer_4 = DFFE( _EQ056, GLOBAL( CLK), VCC, VCC, VCC); _EQ056 = nx615_lc & sm_0 # nx615_lc & sm_1; -- Node name is 'reg_timer_5' = 'timer_5' from file "top_pre.edf" line 258 -- Equation name is 'reg_timer_5', location is LC2_D41, type is buried. timer_5 = DFFE( _EQ057, GLOBAL( CLK), VCC, VCC, VCC); _EQ057 = nx617_lc & sm_0 # nx617_lc & sm_1; -- Node name is 'reg_timer_6' = 'timer_6' from file "top_pre.edf" line 257 -- Equation name is 'reg_timer_6', location is LC1_D41, type is buried. timer_6 = DFFE( _EQ058, GLOBAL( CLK), VCC, VCC, VCC); _EQ058 = nx619_lc & sm_0 # nx619_lc & sm_1; -- Node name is 'reg_timer_7' = 'timer_7' from file "top_pre.edf" line 256 -- Equation name is 'reg_timer_7', location is LC4_D41, type is buried. timer_7 = DFFE( _EQ059, GLOBAL( CLK), VCC, VCC, VCC); _EQ059 = nx621_lc & sm_0 # nx621_lc & sm_1; -- Node name is 'reg_timer_8' = 'timer_8' from file "top_pre.edf" line 255 -- Equation name is 'reg_timer_8', location is LC7_D46, type is buried. timer_8 = DFFE( _EQ060, GLOBAL( CLK), VCC, VCC, VCC); _EQ060 = nx623_lc & sm_0 # nx623_lc & sm_1; -- Node name is 'reg_timer_9' = 'timer_9' from file "top_pre.edf" line 254 -- Equation name is 'reg_timer_9', location is LC7_D49, type is buried. timer_9 = DFFE( _EQ061, GLOBAL( CLK), VCC, VCC, VCC); _EQ061 = nx625_lc & sm_0 # nx625_lc & sm_1; -- Node name is 'reg_timer_10' = 'timer_10' from file "top_pre.edf" line 253 -- Equation name is 'reg_timer_10', location is LC6_D49, type is buried. timer_10 = DFFE( _EQ062, GLOBAL( CLK), VCC, VCC, VCC); _EQ062 = nx627_lc & sm_0 # nx627_lc & sm_1; -- Node name is 'reg_timer_11' = 'timer_11' from file "top_pre.edf" line 252 -- Equation name is 'reg_timer_11', location is LC5_D41, type is buried. timer_11 = DFFE( _EQ063, GLOBAL( CLK), VCC, VCC, VCC); _EQ063 = nx629_lc & sm_0 # nx629_lc & sm_1; -- Node name is 'reg_timer_12' = 'timer_12' from file "top_pre.edf" line 251 -- Equation name is 'reg_timer_12', location is LC8_D41, type is buried. timer_12 = DFFE( _EQ064, GLOBAL( CLK), VCC, VCC, VCC); _EQ064 = nx631_lc & sm_0 # nx631_lc & sm_1; -- Node name is 'reg_timer_13' = 'timer_13' from file "top_pre.edf" line 250 -- Equation name is 'reg_timer_13', location is LC8_D49, type is buried. timer_13 = DFFE( _EQ065, GLOBAL( CLK), VCC, VCC, VCC); _EQ065 = nx633_lc & sm_0 # nx633_lc & sm_1; -- Node name is 'reg_timer_14' = 'timer_14' from file "top_pre.edf" line 249 -- Equation name is 'reg_timer_14', location is LC3_D49, type is buried. timer_14 = DFFE( _EQ066, GLOBAL( CLK), VCC, VCC, VCC); _EQ066 = nx635_lc & sm_0 # nx635_lc & sm_1; -- Node name is 'reg_timer_15' = 'timer_15' from file "top_pre.edf" line 248 -- Equation name is 'reg_timer_15', location is LC5_D49, type is buried. timer_15 = DFFE( _EQ067, GLOBAL( CLK), VCC, VCC, VCC); _EQ067 = nx119_lc & sm_0 # nx119_lc & sm_1; -- Node name is 'tst_out' from file "top_pre.edf" line 107 -- Equation name is 'tst_out', type is output tst_out = _LC2_L37; -- Node name is 'tst_out~fit~in1' from file "top_pre.edf" line 107 -- Equation name is 'tst_out~fit~in1', location is LC2_L37, type is buried. -- synthesized logic cell _LC2_L37 = LCELL( tst_out_lc); -- Node name is 'ix535_lc' = 'tst_out_lc' from file "top_pre.edf" line 513 -- Equation name is 'ix535_lc', location is LC8_L37, type is buried. tst_out_lc = LCELL( _EQ068C); _EQ068C = _EQ068 & CASCADE( _EQ021C); _EQ068 = _LC3_L52 & !nx465_lc # !_LC3_L52 & nx462_lc # !_LC4_L52; -- Node name is '|carry_sum:result_inc_26_ix39_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC1_D45_CARRY', type is buried -- |carry_sum:result_inc_26_ix39_carry_sum|:31 is in Clearable Counter Mode _LC1_D45_CARRY = CARRY( timer_0); -- Node name is '|carry_sum:result_inc_26_ix41_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC2_D45_CARRY', type is buried _LC2_D45_CARRY = CARRY( _EQ069); _EQ069 = _LC1_D45_CARRY & timer_1; -- Node name is '|carry_sum:result_inc_26_ix45_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC3_D45_CARRY', type is buried _LC3_D45_CARRY = CARRY( _EQ070); _EQ070 = _LC2_D45_CARRY & timer_2; -- Node name is '|carry_sum:result_inc_26_ix49_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC4_D45_CARRY', type is buried _LC4_D45_CARRY = CARRY( _EQ071); _EQ071 = _LC3_D45_CARRY & timer_3; -- Node name is '|carry_sum:result_inc_26_ix53_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC5_D45_CARRY', type is buried _LC5_D45_CARRY = CARRY( _EQ072); _EQ072 = _LC4_D45_CARRY & timer_4; -- Node name is '|carry_sum:result_inc_26_ix57_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC6_D45_CARRY', type is buried _LC6_D45_CARRY = CARRY( _EQ073); _EQ073 = _LC5_D45_CARRY & timer_5; -- Node name is '|carry_sum:result_inc_26_ix61_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC7_D45_CARRY', type is buried _LC7_D45_CARRY = CARRY( _EQ074); _EQ074 = _LC6_D45_CARRY & timer_6; -- Node name is '|carry_sum:result_inc_26_ix65_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC8_D45_CARRY', type is buried _LC8_D45_CARRY = CARRY( _EQ075); _EQ075 = _LC7_D45_CARRY & timer_7; -- Node name is '|carry_sum:result_inc_26_ix69_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC1_D47_CARRY', type is buried _LC1_D47_CARRY = CARRY( _EQ076); _EQ076 = _LC8_D45_CARRY & timer_8; -- Node name is '|carry_sum:result_inc_26_ix73_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC2_D47_CARRY', type is buried _LC2_D47_CARRY = CARRY( _EQ077); _EQ077 = _LC1_D47_CARRY & timer_9; -- Node name is '|carry_sum:result_inc_26_ix77_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC3_D47_CARRY', type is buried _LC3_D47_CARRY = CARRY( _EQ078); _EQ078 = _LC2_D47_CARRY & timer_10; -- Node name is '|carry_sum:result_inc_26_ix81_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC4_D47_CARRY', type is buried _LC4_D47_CARRY = CARRY( _EQ079); _EQ079 = _LC3_D47_CARRY & timer_11; -- Node name is '|carry_sum:result_inc_26_ix85_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC5_D47_CARRY', type is buried _LC5_D47_CARRY = CARRY( _EQ080); _EQ080 = _LC4_D47_CARRY & timer_12; -- Node name is '|carry_sum:result_inc_26_ix89_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC6_D47_CARRY', type is buried _LC6_D47_CARRY = CARRY( _EQ081); _EQ081 = _LC5_D47_CARRY & timer_13; -- Node name is '|carry_sum:result_inc_26_ix93_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC7_D47_CARRY', type is buried _LC7_D47_CARRY = CARRY( _EQ082); _EQ082 = _LC6_D47_CARRY & timer_14; -- Node name is '|lpm_counter:div_clk_ix7|carrybit1' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC1_L39_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit1 is in Up/Down Counter Mode _LC1_L39_CARRY = CARRY( _LC1_L39); -- Node name is '|lpm_counter:div_clk_ix7|carrybit2' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC2_L39_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit2 is in Up/Down Counter Mode _LC2_L39_CARRY = CARRY( _EQ083); _EQ083 = _LC1_L39_CARRY & _LC2_L39; -- Node name is '|lpm_counter:div_clk_ix7|carrybit3' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC3_L39_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit3 is in Up/Down Counter Mode _LC3_L39_CARRY = CARRY( _EQ084); _EQ084 = _LC2_L39_CARRY & _LC3_L39; -- Node name is '|lpm_counter:div_clk_ix7|carrybit4' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC4_L39_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit4 is in Up/Down Counter Mode _LC4_L39_CARRY = CARRY( _EQ085); _EQ085 = _LC3_L39_CARRY & _LC4_L39; -- Node name is '|lpm_counter:div_clk_ix7|carrybit5' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC5_L39_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit5 is in Up/Down Counter Mode _LC5_L39_CARRY = CARRY( _EQ086); _EQ086 = _LC4_L39_CARRY & _LC5_L39; -- Node name is '|lpm_counter:div_clk_ix7|carrybit6' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC6_L39_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit6 is in Up/Down Counter Mode _LC6_L39_CARRY = CARRY( _EQ087); _EQ087 = _LC5_L39_CARRY & _LC6_L39; -- Node name is '|lpm_counter:div_clk_ix7|carrybit7' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC7_L39_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit7 is in Up/Down Counter Mode _LC7_L39_CARRY = CARRY( _EQ088); _EQ088 = _LC6_L39_CARRY & _LC7_L39; -- Node name is '|lpm_counter:div_clk_ix7|carrybit8' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC8_L39_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit8 is in Up/Down Counter Mode _LC8_L39_CARRY = CARRY( _EQ089); _EQ089 = _LC7_L39_CARRY & _LC8_L39; -- Node name is '|lpm_counter:div_clk_ix7|carrybit9' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC1_L41_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit9 is in Up/Down Counter Mode _LC1_L41_CARRY = CARRY( _EQ090); _EQ090 = _LC1_L41 & _LC8_L39_CARRY; -- Node name is '|lpm_counter:div_clk_ix7|carrybit10' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC2_L41_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit10 is in Up/Down Counter Mode _LC2_L41_CARRY = CARRY( _EQ091); _EQ091 = _LC1_L41_CARRY & _LC2_L41; -- Node name is '|lpm_counter:div_clk_ix7|carrybit11' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC3_L41_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit11 is in Up/Down Counter Mode _LC3_L41_CARRY = CARRY( _EQ092); _EQ092 = _LC2_L41_CARRY & _LC3_L41; -- Node name is '|lpm_counter:div_clk_ix7|carrybit12' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC4_L41_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit12 is in Up/Down Counter Mode _LC4_L41_CARRY = CARRY( _EQ093); _EQ093 = _LC3_L41_CARRY & _LC4_L41; -- Node name is '|lpm_counter:div_clk_ix7|carrybit13' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC5_L41_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit13 is in Up/Down Counter Mode _LC5_L41_CARRY = CARRY( _EQ094); _EQ094 = _LC4_L41_CARRY & _LC5_L41; -- Node name is '|lpm_counter:div_clk_ix7|carrybit14' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC6_L41_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit14 is in Up/Down Counter Mode _LC6_L41_CARRY = CARRY( _EQ095); _EQ095 = _LC5_L41_CARRY & _LC6_L41; -- Node name is '|lpm_counter:div_clk_ix7|carrybit15' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC7_L41_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit15 is in Up/Down Counter Mode _LC7_L41_CARRY = CARRY( _EQ096); _EQ096 = _LC6_L41_CARRY & _LC7_L41; -- Node name is '|lpm_counter:div_clk_ix7|carrybit16' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC8_L41_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit16 is in Up/Down Counter Mode _LC8_L41_CARRY = CARRY( _EQ097); _EQ097 = _LC7_L41_CARRY & _LC8_L41; -- Node name is '|lpm_counter:div_clk_ix7|carrybit17' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC1_L43_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit17 is in Up/Down Counter Mode _LC1_L43_CARRY = CARRY( _EQ098); _EQ098 = _LC1_L43 & _LC8_L41_CARRY; -- Node name is '|lpm_counter:div_clk_ix7|carrybit18' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC2_L43_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit18 is in Up/Down Counter Mode _LC2_L43_CARRY = CARRY( _EQ099); _EQ099 = _LC1_L43_CARRY & _LC2_L43; -- Node name is '|lpm_counter:div_clk_ix7|carrybit19' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC3_L43_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit19 is in Up/Down Counter Mode _LC3_L43_CARRY = CARRY( _EQ100); _EQ100 = _LC2_L43_CARRY & _LC3_L43; -- Node name is '|lpm_counter:div_clk_ix7|carrybit20' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC4_L43_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit20 is in Up/Down Counter Mode _LC4_L43_CARRY = CARRY( _EQ101); _EQ101 = _LC3_L43_CARRY & _LC4_L43; -- Node name is '|lpm_counter:div_clk_ix7|carrybit21' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC5_L43_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit21 is in Up/Down Counter Mode _LC5_L43_CARRY = CARRY( _EQ102); _EQ102 = _LC4_L43_CARRY & _LC5_L43; -- Node name is '|lpm_counter:div_clk_ix7|carrybit22' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC6_L43_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit22 is in Up/Down Counter Mode _LC6_L43_CARRY = CARRY( _EQ103); _EQ103 = _LC5_L43_CARRY & _LC6_L43; -- Node name is '|lpm_counter:div_clk_ix7|carrybit23' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC7_L43_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit23 is in Up/Down Counter Mode _LC7_L43_CARRY = CARRY( _EQ104); _EQ104 = _LC6_L43_CARRY & _LC7_L43; -- Node name is '|lpm_counter:div_clk_ix7|carrybit24' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC8_L43_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit24 is in Up/Down Counter Mode _LC8_L43_CARRY = CARRY( _EQ105); _EQ105 = _LC7_L43_CARRY & _LC8_L43; -- Node name is '|lpm_counter:div_clk_ix7|carrybit25' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC1_L45_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit25 is in Up/Down Counter Mode _LC1_L45_CARRY = CARRY( _EQ106); _EQ106 = _LC1_L45 & _LC8_L43_CARRY; -- Node name is '|lpm_counter:div_clk_ix7|carrybit26' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC2_L45_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit26 is in Up/Down Counter Mode _LC2_L45_CARRY = CARRY( _EQ107); _EQ107 = _LC1_L45_CARRY & _LC2_L45; -- Node name is '|lpm_counter:div_clk_ix7|dffs0' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC1_L39', type is buried -- |lpm_counter:div_clk_ix7|dffs0 is in Up/Down Counter Mode _LC1_L39 = DFFE(!_LC1_L39, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is '|lpm_counter:div_clk_ix7|dffs1' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC2_L39', type is buried -- |lpm_counter:div_clk_ix7|dffs1 is in Up/Down Counter Mode _LC2_L39 = DFFE( _EQ108, GLOBAL( CLK), VCC, VCC, VCC); _EQ108 = !_LC1_L39_CARRY & _LC2_L39 # _LC1_L39_CARRY & !_LC2_L39; -- Node name is '|lpm_counter:div_clk_ix7|dffs2' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC3_L39', type is buried -- |lpm_counter:div_clk_ix7|dffs2 is in Up/Down Counter Mode _LC3_L39 = DFFE( _EQ109, GLOBAL( CLK), VCC, VCC, VCC); _EQ109 = !_LC2_L39_CARRY & _LC3_L39 # _LC2_L39_CARRY & !_LC3_L39; -- Node name is '|lpm_counter:div_clk_ix7|dffs3' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC4_L39', type is buried -- |lpm_counter:div_clk_ix7|dffs3 is in Up/Down Counter Mode _LC4_L39 = DFFE( _EQ110, GLOBAL( CLK), VCC, VCC, VCC); _EQ110 = !_LC3_L39_CARRY & _LC4_L39 # _LC3_L39_CARRY & !_LC4_L39; -- Node name is '|lpm_counter:div_clk_ix7|dffs4' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC5_L39', type is buried -- |lpm_counter:div_clk_ix7|dffs4 is in Up/Down Counter Mode _LC5_L39 = DFFE( _EQ111, GLOBAL( CLK), VCC, VCC, VCC); _EQ111 = !_LC4_L39_CARRY & _LC5_L39 # _LC4_L39_CARRY & !_LC5_L39; -- Node name is '|lpm_counter:div_clk_ix7|dffs5' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC6_L39', type is buried -- |lpm_counter:div_clk_ix7|dffs5 is in Up/Down Counter Mode _LC6_L39 = DFFE( _EQ112, GLOBAL( CLK), VCC, VCC, VCC); _EQ112 = !_LC5_L39_CARRY & _LC6_L39 # _LC5_L39_CARRY & !_LC6_L39; -- Node name is '|lpm_counter:div_clk_ix7|dffs6' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC7_L39', type is buried -- |lpm_counter:div_clk_ix7|dffs6 is in Up/Down Counter Mode _LC7_L39 = DFFE( _EQ113, GLOBAL( CLK), VCC, VCC, VCC); _EQ113 = !_LC6_L39_CARRY & _LC7_L39 # _LC6_L39_CARRY & !_LC7_L39; -- Node name is '|lpm_counter:div_clk_ix7|dffs7' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC8_L39', type is buried -- |lpm_counter:div_clk_ix7|dffs7 is in Up/Down Counter Mode _LC8_L39 = DFFE( _EQ114, GLOBAL( CLK), VCC, VCC, VCC); _EQ114 = !_LC7_L39_CARRY & _LC8_L39 # _LC7_L39_CARRY & !_LC8_L39; -- Node name is '|lpm_counter:div_clk_ix7|dffs8' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC1_L41', type is buried -- |lpm_counter:div_clk_ix7|dffs8 is in Up/Down Counter Mode _LC1_L41 = DFFE( _EQ115, GLOBAL( CLK), VCC, VCC, VCC); _EQ115 = _LC1_L41 & !_LC8_L39_CARRY # !_LC1_L41 & _LC8_L39_CARRY; -- Node name is '|lpm_counter:div_clk_ix7|dffs9' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC2_L41', type is buried -- |lpm_counter:div_clk_ix7|dffs9 is in Up/Down Counter Mode _LC2_L41 = DFFE( _EQ116, GLOBAL( CLK), VCC, VCC, VCC); _EQ116 = !_LC1_L41_CARRY & _LC2_L41 # _LC1_L41_CARRY & !_LC2_L41; -- Node name is '|lpm_counter:div_clk_ix7|dffs10' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC3_L41', type is buried -- |lpm_counter:div_clk_ix7|dffs10 is in Up/Down Counter Mode _LC3_L41 = DFFE( _EQ117, GLOBAL( CLK), VCC, VCC, VCC); _EQ117 = !_LC2_L41_CARRY & _LC3_L41 # _LC2_L41_CARRY & !_LC3_L41; -- Node name is '|lpm_counter:div_clk_ix7|dffs11' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC4_L41', type is buried -- |lpm_counter:div_clk_ix7|dffs11 is in Up/Down Counter Mode _LC4_L41 = DFFE( _EQ118, GLOBAL( CLK), VCC, VCC, VCC); _EQ118 = !_LC3_L41_CARRY & _LC4_L41 # _LC3_L41_CARRY & !_LC4_L41; -- Node name is '|lpm_counter:div_clk_ix7|dffs12' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC5_L41', type is buried -- |lpm_counter:div_clk_ix7|dffs12 is in Up/Down Counter Mode _LC5_L41 = DFFE( _EQ119, GLOBAL( CLK), VCC, VCC, VCC); _EQ119 = !_LC4_L41_CARRY & _LC5_L41 # _LC4_L41_CARRY & !_LC5_L41; -- Node name is '|lpm_counter:div_clk_ix7|dffs13' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC6_L41', type is buried -- |lpm_counter:div_clk_ix7|dffs13 is in Up/Down Counter Mode _LC6_L41 = DFFE( _EQ120, GLOBAL( CLK), VCC, VCC, VCC); _EQ120 = !_LC5_L41_CARRY & _LC6_L41 # _LC5_L41_CARRY & !_LC6_L41; -- Node name is '|lpm_counter:div_clk_ix7|dffs14' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC7_L41', type is buried -- |lpm_counter:div_clk_ix7|dffs14 is in Up/Down Counter Mode _LC7_L41 = DFFE( _EQ121, GLOBAL( CLK), VCC, VCC, VCC); _EQ121 = !_LC6_L41_CARRY & _LC7_L41 # _LC6_L41_CARRY & !_LC7_L41; -- Node name is '|lpm_counter:div_clk_ix7|dffs15' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC8_L41', type is buried -- |lpm_counter:div_clk_ix7|dffs15 is in Up/Down Counter Mode _LC8_L41 = DFFE( _EQ122, GLOBAL( CLK), VCC, VCC, VCC); _EQ122 = !_LC7_L41_CARRY & _LC8_L41 # _LC7_L41_CARRY & !_LC8_L41; -- Node name is '|lpm_counter:div_clk_ix7|dffs16' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC1_L43', type is buried -- |lpm_counter:div_clk_ix7|dffs16 is in Up/Down Counter Mode _LC1_L43 = DFFE( _EQ123, GLOBAL( CLK), VCC, VCC, VCC); _EQ123 = _LC1_L43 & !_LC8_L41_CARRY # !_LC1_L43 & _LC8_L41_CARRY; -- Node name is '|lpm_counter:div_clk_ix7|dffs17' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC2_L43', type is buried -- |lpm_counter:div_clk_ix7|dffs17 is in Up/Down Counter Mode _LC2_L43 = DFFE( _EQ124, GLOBAL( CLK), VCC, VCC, VCC); _EQ124 = !_LC1_L43_CARRY & _LC2_L43 # _LC1_L43_CARRY & !_LC2_L43; -- Node name is '|lpm_counter:div_clk_ix7|dffs18' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC3_L43', type is buried -- |lpm_counter:div_clk_ix7|dffs18 is in Up/Down Counter Mode _LC3_L43 = DFFE( _EQ125, GLOBAL( CLK), VCC, VCC, VCC); _EQ125 = !_LC2_L43_CARRY & _LC3_L43 # _LC2_L43_CARRY & !_LC3_L43; -- Node name is '|lpm_counter:div_clk_ix7|dffs19' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC4_L43', type is buried -- |lpm_counter:div_clk_ix7|dffs19 is in Up/Down Counter Mode _LC4_L43 = DFFE( _EQ126, GLOBAL( CLK), VCC, VCC, VCC); _EQ126 = !_LC3_L43_CARRY & _LC4_L43 # _LC3_L43_CARRY & !_LC4_L43; -- Node name is '|lpm_counter:div_clk_ix7|dffs20' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC5_L43', type is buried -- |lpm_counter:div_clk_ix7|dffs20 is in Up/Down Counter Mode _LC5_L43 = DFFE( _EQ127, GLOBAL( CLK), VCC, VCC, VCC); _EQ127 = !_LC4_L43_CARRY & _LC5_L43 # _LC4_L43_CARRY & !_LC5_L43; -- Node name is '|lpm_counter:div_clk_ix7|dffs21' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC6_L43', type is buried -- |lpm_counter:div_clk_ix7|dffs21 is in Up/Down Counter Mode _LC6_L43 = DFFE( _EQ128, GLOBAL( CLK), VCC, VCC, VCC); _EQ128 = !_LC5_L43_CARRY & _LC6_L43 # _LC5_L43_CARRY & !_LC6_L43; -- Node name is '|lpm_counter:div_clk_ix7|dffs22' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC7_L43', type is buried -- |lpm_counter:div_clk_ix7|dffs22 is in Up/Down Counter Mode _LC7_L43 = DFFE( _EQ129, GLOBAL( CLK), VCC, VCC, VCC); _EQ129 = !_LC6_L43_CARRY & _LC7_L43 # _LC6_L43_CARRY & !_LC7_L43; -- Node name is '|lpm_counter:div_clk_ix7|dffs23' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC8_L43', type is buried -- |lpm_counter:div_clk_ix7|dffs23 is in Up/Down Counter Mode _LC8_L43 = DFFE( _EQ130, GLOBAL( CLK), VCC, VCC, VCC); _EQ130 = !_LC7_L43_CARRY & _LC8_L43 # _LC7_L43_CARRY & !_LC8_L43; -- Node name is '|lpm_counter:div_clk_ix7|dffs24' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC1_L45', type is buried -- |lpm_counter:div_clk_ix7|dffs24 is in Up/Down Counter Mode _LC1_L45 = DFFE( _EQ131, GLOBAL( CLK), VCC, VCC, VCC); _EQ131 = _LC1_L45 & !_LC8_L43_CARRY # !_LC1_L45 & _LC8_L43_CARRY; -- Node name is '|lpm_counter:div_clk_ix7|dffs25' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC2_L45', type is buried -- |lpm_counter:div_clk_ix7|dffs25 is in Up/Down Counter Mode _LC2_L45 = DFFE( _EQ132, GLOBAL( CLK), VCC, VCC, VCC); _EQ132 = !_LC1_L45_CARRY & _LC2_L45 # _LC1_L45_CARRY & !_LC2_L45; -- Node name is '|lpm_counter:div_clk_ix7|dffs26' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC3_L45', type is buried _LC3_L45 = DFFE( _EQ133, GLOBAL( CLK), VCC, VCC, VCC); _EQ133 = !_LC2_L45_CARRY & _LC3_L45 # _LC2_L45_CARRY & !_LC3_L45; -- Node name is '|lpm_counter:mode_ix7|carrybit1' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC1_L52_CARRY', type is buried -- |lpm_counter:mode_ix7|carrybit1 is in Up/Down Counter Mode _LC1_L52_CARRY = CARRY( _LC1_L52); -- Node name is '|lpm_counter:mode_ix7|carrybit2' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC2_L52_CARRY', type is buried -- |lpm_counter:mode_ix7|carrybit2 is in Up/Down Counter Mode _LC2_L52_CARRY = CARRY( _EQ134); _EQ134 = _LC1_L52_CARRY & _LC2_L52; -- Node name is '|lpm_counter:mode_ix7|carrybit3' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC3_L52_CARRY', type is buried -- |lpm_counter:mode_ix7|carrybit3 is in Up/Down Counter Mode _LC3_L52_CARRY = CARRY( _EQ135); _EQ135 = _LC2_L52_CARRY & _LC3_L52; -- Node name is '|lpm_counter:mode_ix7|dffs0' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC1_L52', type is buried -- |lpm_counter:mode_ix7|dffs0 is in Up/Down Counter Mode _LC1_L52 = DFFE(!_LC1_L52, mode_sw_f, VCC, VCC, VCC); -- Node name is '|lpm_counter:mode_ix7|dffs1' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC2_L52', type is buried -- |lpm_counter:mode_ix7|dffs1 is in Up/Down Counter Mode _LC2_L52 = DFFE( _EQ136, mode_sw_f, VCC, VCC, VCC); _EQ136 = !_LC1_L52_CARRY & _LC2_L52 # _LC1_L52_CARRY & !_LC2_L52; -- Node name is '|lpm_counter:mode_ix7|dffs2' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC3_L52', type is buried -- |lpm_counter:mode_ix7|dffs2 is in Up/Down Counter Mode _LC3_L52 = DFFE( _EQ137, mode_sw_f, VCC, VCC, VCC); _EQ137 = !_LC2_L52_CARRY & _LC3_L52 # _LC2_L52_CARRY & !_LC3_L52; -- Node name is '|lpm_counter:mode_ix7|dffs3' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC4_L52', type is buried _LC4_L52 = DFFE( _EQ138, mode_sw_f, VCC, VCC, VCC); _EQ138 = !_LC3_L52_CARRY & _LC4_L52 # _LC3_L52_CARRY & !_LC4_L52; Project Information k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt ** TIMING ASSIGNMENTS ** INFORMATION: One or more paths have been found between register controlled by different clocks--can't calculate fmax for those paths User Actual Type Location Assignment Value Status Critical Path fmax CLK 90.00 MHz 106.38 MHz CLK to register |lpm_counter:div_clk_ix7|dffs15.Q to register sm_1.Q Project Information k:\angelov\acex_designs.svn\trigg_ori\maxplus\top_pre.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Multi-Level Default Synthesis Style = FAST Logic option settings in 'FAST' style for 'ACEX1K' family CARRY_CHAIN = auto CARRY_CHAIN_LENGTH = 32 CASCADE_CHAIN = auto CASCADE_CHAIN_LENGTH = 2 DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on REDUCE_LOGIC = on REFACTORIZATION = off REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SUBFACTOR_EXTRACTION = off IGNORE_SOFT_BUFFERS = on USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = off Automatic Register Packing = off Automatic Open-Drain Pins = off Automatic Implement in EAB = off Optimize = 10 Default Timing Specifications: Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = off Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = ADVANCED Use Quartus Fitter = on Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:01 Database Builder 00:00:00 Logic Synthesizer 00:00:00 Partitioner 00:00:01 Fitter 00:00:06 Timing SNF Extractor 00:00:01 Assembler 00:00:01 -------------------------- -------- Total Time 00:00:10 Memory Allocated ----------------- Peak memory allocated during compilation = 49,919K