LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

entity top_pre is
generic(
    duration1 : Integer :=  50;
    duration2 : Integer := 150);
    port (
        clk             : in  std_logic; -- 80 MHz

        -- user IO
        mode_sw         : in  std_logic;
        inp_sw          : in  std_logic;
        pre_in          : in  std_logic; -- ADC1_D0, ADC connector pin 19
        tst_out         : out std_logic; -- ADC1_D2, ADC connector pin 17
        pre_out0        : out std_logic; -- ADC2_D0, ADC connector pin 11
        pre_out1        : out std_logic; -- ADC2_D2, ADC connector pin 13
        pre_out2        : out std_logic; -- ADC2_D4, ADC connector pin 15
        pre_out3        : out std_logic; -- ADC2_D6, ADC connector pin 17
        R7S             : out std_logic_vector(1     to 7);

        LED_RED         : out std_logic; -- 0 is on
        LVDS_EN         : out std_logic;
        ADC_OEn         : out std_logic;
        SRAM_CEn        : out std_logic;
        SRAM_OEn        : out std_logic
        );
end top_pre;


architecture a of top_pre is

component dbl7seg IS
        PORT(
                CL, CR  : IN    STD_LOGIC_VECTOR(3 downto 0); -- code for left/right
                mx      : IN    STD_LOGIC; -- 100Hz
                dis     : IN    STD_LOGIC; -- disable outputs (switch off)
                mx_out  : OUT   STD_LOGIC;
                Q       : OUT   STD_LOGIC_VECTOR(1 to 7) -- output to 7segm ind.
                );
END component;

component filt2s IS
        PORT(
                clk, d          : IN    STD_LOGIC;
                q               : OUT   STD_LOGIC);
END component;

component filt3s IS
        PORT(
                clk, d          : IN    STD_LOGIC;
                q               : OUT   STD_LOGIC);
END component;

signal  pre_in_fil      : std_logic;
signal  pre_in_fil_old  : std_logic;
signal  mode            : std_logic_vector(3 downto 0);
signal  mode_sw_f       : std_logic;

signal  div_clk         : std_logic_vector(27 downto 0);
signal  timer           : std_logic_vector(15 downto 0);
signal  clk_slow        : std_logic;

signal  inp_sel         : std_logic;
signal  inp_sw_f        : std_logic;
signal  pre_out_i       : std_logic;

type sm_type is (idle, pulse1, pulse2);

signal sm : sm_type;

begin

        LVDS_EN  <= '0';
        ADC_OEn  <= '1';
        SRAM_CEn <= '1';
        SRAM_OEn <= '1';

        clk_slow <= div_clk(15);

fmd:    filt3s
        PORT map(
                clk  => clk_slow,
                d    => mode_sw,
                q    => mode_sw_f);

        process(mode_sw_f)
        begin
            if mode_sw_f'event and mode_sw_f='1' then
                mode <= mode + 1;
            end if;
        end process;

sg:    dbl7seg
        PORT map(
                CL     => mode,
                CR     => mode,
                mx     => '0',
                dis    => '0',
                mx_out => open,
                Q      => R7S);

fmi:    filt3s
        PORT map(
                clk  => clk_slow,
                d    => inp_sw,
                q    => inp_sw_f);

        process(inp_sw_f)
        begin
            if inp_sw_f'event and inp_sw_f='1' then
                if mode /= "1111" then inp_sel <= not inp_sel; end if;
            end if;
        end process;
        LED_RED <= inp_sel;

fin:    filt2s
        PORT map(
                clk  => clk,
                d    => pre_in,
                q    => pre_in_fil);

        process(clk)
        begin
            if clk'event and clk= '1' then
                div_clk <= div_clk + 1;
                pre_in_fil_old <= pre_in_fil;
                pre_out_i <= '0';
                case sm is
                when idle =>
                    if pre_in_fil='1' and pre_in_fil_old='0' then sm <= pulse1; end if;
                    timer <= (others => '0');
                when pulse1 =>
                    pre_out_i <= '1';
                    timer <= timer + 1;
                    if timer = duration1 then
                        if inp_sel='1' then sm <= idle;
                                       else sm <= pulse2;
                        end if;
                    end if;
                when pulse2 =>
                    pre_out_i <= '1';
                    timer <= timer + 1;
                    if timer = duration2 then sm <= idle; end if;
                when others => sm <= idle;
                end case;
            end if;
        end process;

        pre_out0 <= pre_out_i;
        pre_out1 <= pre_out_i;
        pre_out2 <= pre_out_i;
        pre_out3 <= pre_out_i;

        with mode select
        tst_out <= div_clk(12) when "0000",
                   div_clk(13) when "0001",
                   div_clk(14) when "0010",
                   div_clk(15) when "0011",
                   div_clk(16) when "0100",
                   div_clk(17) when "0101",
                   div_clk(18) when "0110",
                   div_clk(19) when "0111",
                   div_clk(20) when "1000",
                   div_clk(21) when "1001",
                   div_clk(22) when "1010",
                   div_clk(23) when "1011",
                   div_clk(24) when "1100",
                   div_clk(25) when "1101",
                   div_clk(26) when "1110",
                   inp_sw_f    when "1111",
                   '-'         when others;
end;