LIBRARY IEEE;
use IEEE.std_logic_1164.all;
-- a simple debounce filter: the output will be changed only if
-- 3 successive samples are equal ("111" or "000").
ENTITY filt3s IS
	PORT(
		clk, d		: IN	STD_LOGIC;
		q			: OUT	STD_LOGIC);
END filt3s;

architecture a of filt3s is
SIGNAL SAMPLES : STD_LOGIC_VECTOR(2 downto 0);
begin
	process(clk)
	begin
		if clk'event and clk='1' then
			SAMPLES(2 downto 0) <= SAMPLES(1 downto 0) & d;
			CASE SAMPLES is
			when "111" => q <= '1';
			when "000" => q <= '0';
			when others => NULL;
			end case;
		end if;
	end process;
end;