LIBRARY IEEE;
use IEEE.std_logic_1164.all;
-- a simple debounce filter: the output will be changed only if
-- 2 successive samples are equal ("11" or "00").
ENTITY filt2s IS
        PORT(
                clk, d          : IN    STD_LOGIC;
                q               : OUT   STD_LOGIC);
END filt2s;

architecture a of filt2s is
SIGNAL SAMPLES : STD_LOGIC_VECTOR(1 downto 0);
begin
        process(clk)
        begin
                if clk'event and clk='1' then
                        SAMPLES <= SAMPLES(0) & d;
                        CASE SAMPLES is
                        when "11" => q <= '1';
                        when "00" => q <= '0';
                        when others => NULL;
                        end case;
                end if;
        end process;
end;