library IEEE;
use  IEEE.STD_LOGIC_1164.all;

ENTITY dbl7seg IS
	PORT(
		CL, CR	: IN	STD_LOGIC_VECTOR(3 downto 0); -- code for left/right
		mx		: IN    STD_LOGIC; -- 100Hz
		dis		: IN    STD_LOGIC; -- disable outputs (switch off)
		mx_out  : OUT   STD_LOGIC;
		Q		: OUT	STD_LOGIC_VECTOR(1 to 7) -- output to 7segm ind.
		);
END dbl7seg;

architecture angel of dbl7seg is

component s7segm IS
	PORT(
		DIN	: IN	STD_LOGIC_VECTOR(3 downto 0);
		a	: OUT	STD_LOGIC;
		b	: OUT	STD_LOGIC;
		c	: OUT	STD_LOGIC;
		d	: OUT	STD_LOGIC;
		e	: OUT	STD_LOGIC;
		f	: OUT	STD_LOGIC;
		g	: OUT	STD_LOGIC
		);
END component;

signal CM : STD_LOGIC_VECTOR(3 downto 0);
signal QM : STD_LOGIC_VECTOR(1 to 7);
signal mx_q : STD_LOGIC;
begin
	process(mx)
	begin
		if mx'event and mx='1' then
			mx_q<= not mx_q;
		end if;
	end process;
	mx_out <= mx_q;
	CM <= CL when mx_q='0' else CR;
u1: s7segm port map(DIN => CM, a=>QM(1), b=>QM(2), c=>QM(3), d=>QM(4), 
                               e=>QM(5), f=>QM(6), g=>QM(7) );
	Q <= QM when dis='0' else (others => '1');
end;