LeonardoSpectrum Level 3 - 2005a.82 (Release Production Release, compiled Aug 2 2005 at 02:10:57) Copyright 1990-2004 Mentor Graphics. All rights reserved. Portions copyright 1991-2004 Compuware Corporation Checking Security ... -- Reading file C:\LS2005a_82\\data\standard.vhd for unit standard -- Loading package standard into library std -- Reading vhdl file K:/angelov/ACEX_designs.svn/trigg_ori/SRC/filt2s.vhd into library work -- Reading file C:\LS2005a_82\\data\std_1164.vhd for unit std_logic_1164 -- Loading package std_logic_1164 into library IEEE -- Loading entity filt2s into library work -- Loading architecture a of filt2s into library work -- Reading vhdl file K:/angelov/ACEX_designs.svn/trigg_ori/SRC/filt3s.vhd into library work -- Loading entity filt3s into library work -- Loading architecture a of filt3s into library work -- Reading vhdl file K:/angelov/ACEX_designs.svn/trigg_ori/SRC/s7segm.vhd into library work -- Searching for SYNOPSYS package STD_LOGIC_ARITH.. -- Reading file C:\LS2005a_82\\data\syn_arit.vhd for unit STD_LOGIC_ARITH -- Loading package std_logic_arith into library IEEE -- Searching for SYNOPSYS package STD_LOGIC_UNSIGNED.. -- Reading file C:\LS2005a_82\\data\syn_unsi.vhd for unit STD_LOGIC_UNSIGNED -- Loading package STD_LOGIC_UNSIGNED into library IEEE -- Loading entity s7segm into library work -- Loading architecture angel of s7segm into library work -- Reading vhdl file K:/angelov/ACEX_designs.svn/trigg_ori/SRC/dbl7seg.vhd into library work -- Loading entity dbl7seg into library work -- Loading architecture angel of dbl7seg into library work -- Reading vhdl file K:/angelov/ACEX_designs.svn/trigg_ori/SRC/top_pre.vhd into library work -- Loading entity top_pre into library work "K:/angelov/ACEX_designs.svn/trigg_ori/SRC/top_pre.vhd",line 70: Info, Enumerated type sm_type with 3 elements encoded as binary. Encodings for sm_type values value sm_type[1-0] ============================= idle 00 pulse1 -1 pulse2 10 -- Loading architecture a of top_pre into library work -- Compiling root entity top_pre(a) -- Compiling entity filt3s(a) -- Compiling entity dbl7seg(angel) -- Compiling entity s7segm(angel) -- Compiling entity filt2s(a) "K:/angelov/ACEX_designs.svn/trigg_ori/SRC/top_pre.vhd",line 147: Info, others clause is never selected for synthesis. "K:/angelov/ACEX_designs.svn/trigg_ori/SRC/top_pre.vhd",line 147: Warning, Integer range is less than necessary range to cover others clause, may produce bad logic. "K:/angelov/ACEX_designs.svn/trigg_ori/SRC/top_pre.vhd",line 157: Info, others clause is never selected for synthesis. "K:/angelov/ACEX_designs.svn/trigg_ori/SRC/dbl7seg.vhd", line 31:Info, D-Flipflop reg_mx_q is always 0, optimizing... -- Boundary optimization. -- Start pre-optimization for design .work.filt3s.a -- Start pre-optimization for design .work.s7segm.angel -- Start pre-optimization for design .work.dbl7seg.angel_unfold_1176 -- Start pre-optimization for design .work.filt2s.a -- Start pre-optimization for design .work.top_pre.a "K:/angelov/ACEX_designs.svn/trigg_ori/SRC/top_pre.vhd", line 92:Info, Inferred counter instance 'mode' of type 'counter_up_clock_4' "K:/angelov/ACEX_designs.svn/trigg_ori/SRC/top_pre.vhd", line 128:Info, Inferred counter instance 'div_clk' of type 'counter_up_clock_28' -- Start pre-optimization for design .work.filt3s.a -- Start pre-optimization for design .work.s7segm.angel -- Start pre-optimization for design .work.dbl7seg.angel_unfold_1176 -- Start pre-optimization for design .work.filt2s.a -- Start pre-optimization for design .work.top_pre.a Info: setting part to EP1K100QC208 Info: setting process to 2 Reading library file `C:\LS2005a_82\\lib\acex1.syn`... Library version = 4.5 Delays assume: Process=2 Info: setting encoding to auto Using default wire table: STD-1 -- Start optimization for design .work.top_pre.a Using default wire table: STD-1 est est Pass LCs Delay DFFs TRIs PIs POs --CPU-- min:sec 1 118 17 32 0 4 17 00:03 2 118 20 32 0 4 17 00:04 3 115 20 32 0 4 17 00:04 4 108 13 32 0 4 17 00:03 Info, Pass 4 was selected as best. Info: setting opt_best_result to 1390.564800 Info: setting opt_best_pass to 4 Using default wire table: STD-1 -- Start timing optimization for design .work.top_pre.a Initial Timing Optimization Statistics: --------------------------------------- Clock : Frequency ------------------------------------ clk : 76.6 MHz div_clk(15) : 171.7 MHz mode_sw_f : N/A inp_sw_f : 130.3 MHz Most Critical Slack : -1.1 Sum of Negative Slacks : -11.3 Area : 108.0 Final Timing Optimization Statistics: ------------------------------------- Clock : Frequency ------------------------------------ clk : 80.3 MHz div_clk(15) : 171.7 MHz mode_sw_f : N/A inp_sw_f : 130.3 MHz Most Critical Slack : -0.4 Sum of Negative Slacks : -1.3 Area : 107.0 Total time taken : 1 cpu secs AutoWrite args are : NETLIST/top_pre.edf -- Applying renaming rule 'ALTERA' to database Warning, Renaming will cause your database to change -- Calling set_altera_eqn to set up writing Equations -- Writing file NETLIST/top_pre.edf Info, Writing batch file 'NETLIST/top_pre.tcl' Using default wire table: STD-1