# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # The default values for assignments are stored in the file # top_pci_scsn_assignment_defaults.qdf # If this file doesn't exist, and for assignments not listed, see file # assignment_defaults.qdf # Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # Project-Wide Assignments # ======================== set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2 set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:47:23 APRIL 01, 2004" set_global_assignment -name LAST_QUARTUS_VERSION 5.0 set_global_assignment -name AHDL_FILE pci_contr.tdf set_global_assignment -name EDIF_FILE top_pci_scsn.edf set_global_assignment -name CDF_FILE Chain1.cdf # Pin & Location Assignments # ========================== set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" set_location_assignment PIN_39 -to TDO set_location_assignment PIN_38 -to TDI set_location_assignment PIN_37 -to TMS set_location_assignment PIN_36 -to TCK set_location_assignment PIN_31 -to digital_io[4] set_location_assignment PIN_30 -to digital_io[5] set_location_assignment PIN_29 -to digital_io[6] set_location_assignment PIN_28 -to digital_io[7] set_location_assignment PIN_25 -to digital_io[8] set_location_assignment PIN_24 -to digital_io[9] set_location_assignment PIN_19 -to digital_io[10] set_location_assignment PIN_18 -to digital_io[11] set_location_assignment PIN_17 -to digital_io[12] set_location_assignment PIN_16 -to digital_io[13] set_location_assignment PIN_15 -to digital_io[14] set_location_assignment PIN_14 -to digital_io[15] set_location_assignment PIN_26 -to ADC_CLK set_location_assignment PIN_27 -to ADC_OEn set_location_assignment PIN_119 -to AUDIO_CLK set_location_assignment PIN_120 -to AUDIO_CSn set_location_assignment PIN_116 -to AUDIO_DAT set_location_assignment PIN_200 -to BLUE set_location_assignment PIN_182 -to CLK50M set_location_assignment PIN_71 -to CLK_OUT set_location_assignment PIN_199 -to GREEN set_location_assignment PIN_196 -to H_SYNC set_location_assignment PIN_205 -to digital_io[1] set_location_assignment PIN_204 -to digital_io[0] set_location_assignment PIN_195 -to LED_GRN set_location_assignment PIN_193 -to LED_RED set_location_assignment PIN_206 -to LVDS_EN set_location_assignment PIN_8 -to LVDS_in[0] set_location_assignment PIN_7 -to LVDS_in[1] set_location_assignment PIN_9 -to LVDS_in[2] set_location_assignment PIN_10 -to LVDS_in[3] set_location_assignment PIN_207 -to LVDS_out[0] set_location_assignment PIN_208 -to LVDS_out[1] set_location_assignment PIN_13 -to LVDS_out[2] set_location_assignment PIN_12 -to LVDS_out[3] set_location_assignment PIN_203 -to digital_io[3] set_location_assignment PIN_202 -to digital_io[2] set_location_assignment PIN_183 -to PCLK set_location_assignment PIN_192 -to R7S[1] set_location_assignment PIN_180 -to R7S[2] set_location_assignment PIN_186 -to R7S[3] set_location_assignment PIN_187 -to R7S[4] set_location_assignment PIN_189 -to R7S[5] set_location_assignment PIN_191 -to R7S[6] set_location_assignment PIN_190 -to R7S[7] set_location_assignment PIN_179 -to R7S_mux set_location_assignment PIN_198 -to RED set_location_assignment PIN_184 -to RST set_location_assignment PIN_172 -to SRAM_AD[0] set_location_assignment PIN_134 -to SRAM_AD[10] set_location_assignment PIN_170 -to SRAM_AD[11] set_location_assignment PIN_169 -to SRAM_AD[12] set_location_assignment PIN_168 -to SRAM_AD[13] set_location_assignment PIN_167 -to SRAM_AD[14] set_location_assignment PIN_166 -to SRAM_AD[15] set_location_assignment PIN_164 -to SRAM_AD[16] set_location_assignment PIN_163 -to SRAM_AD[17] set_location_assignment PIN_173 -to SRAM_AD[1] set_location_assignment PIN_174 -to SRAM_AD[2] set_location_assignment PIN_175 -to SRAM_AD[3] set_location_assignment PIN_176 -to SRAM_AD[4] set_location_assignment PIN_177 -to SRAM_AD[5] set_location_assignment PIN_121 -to SRAM_AD[6] set_location_assignment PIN_122 -to SRAM_AD[7] set_location_assignment PIN_132 -to SRAM_AD[8] set_location_assignment PIN_133 -to SRAM_AD[9] set_location_assignment PIN_125 -to SRAM_CEn set_location_assignment PIN_128 -to SRAM_CLK set_location_assignment PIN_162 -to SRAM_IO[0] set_location_assignment PIN_142 -to SRAM_IO[10] set_location_assignment PIN_143 -to SRAM_IO[11] set_location_assignment PIN_148 -to SRAM_IO[12] set_location_assignment PIN_149 -to SRAM_IO[13] set_location_assignment PIN_158 -to SRAM_IO[14] set_location_assignment PIN_159 -to SRAM_IO[15] set_location_assignment PIN_139 -to SRAM_IO[16] set_location_assignment PIN_160 -to SRAM_IO[17] set_location_assignment PIN_161 -to SRAM_IO[1] set_location_assignment PIN_157 -to SRAM_IO[2] set_location_assignment PIN_150 -to SRAM_IO[3] set_location_assignment PIN_147 -to SRAM_IO[4] set_location_assignment PIN_144 -to SRAM_IO[5] set_location_assignment PIN_141 -to SRAM_IO[6] set_location_assignment PIN_140 -to SRAM_IO[7] set_location_assignment PIN_135 -to SRAM_IO[8] set_location_assignment PIN_136 -to SRAM_IO[9] set_location_assignment PIN_131 -to SRAM_OEn set_location_assignment PIN_197 -to V_SYNC set_location_assignment PIN_102 -to pci_AD[0] set_location_assignment PIN_90 -to pci_AD[10] set_location_assignment PIN_89 -to pci_AD[11] set_location_assignment PIN_88 -to pci_AD[12] set_location_assignment PIN_87 -to pci_AD[13] set_location_assignment PIN_86 -to pci_AD[14] set_location_assignment PIN_85 -to pci_AD[15] set_location_assignment PIN_67 -to pci_AD[16] set_location_assignment PIN_65 -to pci_AD[17] set_location_assignment PIN_64 -to pci_AD[18] set_location_assignment PIN_63 -to pci_AD[19] set_location_assignment PIN_101 -to pci_AD[1] set_location_assignment PIN_62 -to pci_AD[20] set_location_assignment PIN_61 -to pci_AD[21] set_location_assignment PIN_60 -to pci_AD[22] set_location_assignment PIN_58 -to pci_AD[23] set_location_assignment PIN_57 -to pci_AD[24] set_location_assignment PIN_56 -to pci_AD[25] set_location_assignment PIN_55 -to pci_AD[26] set_location_assignment PIN_54 -to pci_AD[27] set_location_assignment PIN_53 -to pci_AD[28] set_location_assignment PIN_47 -to pci_AD[29] set_location_assignment PIN_100 -to pci_AD[2] set_location_assignment PIN_46 -to pci_AD[30] set_location_assignment PIN_45 -to pci_AD[31] set_location_assignment PIN_99 -to pci_AD[3] set_location_assignment PIN_97 -to pci_AD[4] set_location_assignment PIN_96 -to pci_AD[5] set_location_assignment PIN_95 -to pci_AD[6] set_location_assignment PIN_94 -to pci_AD[7] set_location_assignment PIN_93 -to pci_AD[8] set_location_assignment PIN_92 -to pci_AD[9] set_location_assignment PIN_111 -to pci_CBEn[0] set_location_assignment PIN_112 -to pci_CBEn[1] set_location_assignment PIN_113 -to pci_CBEn[2] set_location_assignment PIN_114 -to pci_CBEn[3] set_location_assignment PIN_74 -to pci_DEVSELn set_location_assignment PIN_69 -to pci_FRAMEn set_location_assignment PIN_68 -to pci_GNTn set_location_assignment PIN_44 -to pci_IDSEL set_location_assignment PIN_40 -to pci_INTAn set_location_assignment PIN_70 -to pci_IRDYn set_location_assignment PIN_83 -to pci_LOCKn set_location_assignment PIN_104 -to pci_PAR set_location_assignment PIN_103 -to pci_PERRn set_location_assignment PIN_41 -to pci_REQn set_location_assignment PIN_78 -to pci_RSTn set_location_assignment PIN_115 -to pci_SERRn set_location_assignment PIN_75 -to pci_STOPn set_location_assignment PIN_73 -to pci_TRDYn set_location_assignment PIN_79 -to pci_clk # Timing Assignments # ================== set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF # Analysis & Synthesis Assignments # ================================ set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL LEONARDOSPECTRUM set_global_assignment -name FAMILY ACEX1K set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON set_global_assignment -name TOP_LEVEL_ENTITY top_pci_scsn set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name USER_LIBRARIES "F:\\altera\\MegaCore\\pci_compiler-v2.4.0\\lib;F:/altera/MegaCore/pci_compiler-v4.0.0/lib" # Fitter Assignments # ================== set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 3.0 set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0 set_global_assignment -name DEVICE "EP1K100QC208-1" set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" set_global_assignment -name SLOW_SLEW_RATE ON set_global_assignment -name PCI_IO ON set_global_assignment -name AUTO_GLOBAL_CLOCK OFF set_global_assignment -name AUTO_GLOBAL_OE OFF set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS OFF set_global_assignment -name FLEX10K_DEVICE_IO_STANDARD "3.3-V PCI" set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 # Timing Analysis Assignments # =========================== set_global_assignment -name MAX_SCC_SIZE 50 # EDA Netlist Writer Assignments # ============================== set_global_assignment -name EDA_SIMULATION_TOOL "" set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" set_global_assignment -name EDA_RESYNTHESIS_TOOL "" # Assembler Assignments # ===================== set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2 set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2 set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2 set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1 set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2 set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPC2 set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPC2 set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF # Design Assistant Assignments # ============================ set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF set_global_assignment -name CLK_CAT OFF set_global_assignment -name CLK_RULE_COMB_CLOCK OFF set_global_assignment -name CLK_RULE_INV_CLOCK OFF set_global_assignment -name CLK_RULE_GATING_SCHEME OFF set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF set_global_assignment -name CLK_RULE_MIX_EDGES OFF set_global_assignment -name RESET_CAT OFF set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF set_global_assignment -name TIMING_CAT OFF set_global_assignment -name TIMING_RULE_SHIFT_REG OFF set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF set_global_assignment -name NONSYNCHSTRUCT_CAT OFF set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF set_global_assignment -name SIGNALRACE_CAT OFF set_global_assignment -name ACLK_CAT OFF set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF set_global_assignment -name HCPY_CAT OFF set_global_assignment -name HCPY_VREF_PINS OFF # -------------------- # start CLOCK(clk_pci) # Timing Assignments # ================== set_global_assignment -name DUTY_CYCLE 50 -section_id clk_pci set_global_assignment -name FMAX_REQUIREMENT "40.0 MHz" -section_id clk_pci set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id clk_pci # end CLOCK(clk_pci) # ------------------ # --------------------- # start CLOCK(clk_scsn) # Timing Assignments # ================== set_global_assignment -name DUTY_CYCLE 50 -section_id clk_scsn set_global_assignment -name FMAX_REQUIREMENT "120.0 MHz" -section_id clk_scsn set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id clk_scsn # end CLOCK(clk_scsn) # ------------------- # ---------------- # start CLOCK(tck) # Timing Assignments # ================== set_global_assignment -name FMAX_REQUIREMENT "10.0 MHz" -section_id tck set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id tck # end CLOCK(tck) # -------------- # ----------------------------------------- # start EDA_TOOL_SETTINGS(eda_board_design) # EDA Netlist Writer Assignments # ============================== set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_board_design # end EDA_TOOL_SETTINGS(eda_board_design) # --------------------------------------- # --------------------------------------------- # start EDA_TOOL_SETTINGS(eda_design_synthesis) # Analysis & Synthesis Assignments # ================================ set_global_assignment -name EDA_LMF_FILE exemplar.lmf -section_id eda_design_synthesis # EDA Netlist Writer Assignments # ============================== set_global_assignment -name EDA_OUTPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis # end EDA_TOOL_SETTINGS(eda_design_synthesis) # ------------------------------------------- # ------------------------------------------------ # start EDA_TOOL_SETTINGS(eda_formal_verification) # EDA Netlist Writer Assignments # ============================== set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_formal_verification # end EDA_TOOL_SETTINGS(eda_formal_verification) # ---------------------------------------------- # ----------------------------------- # start EDA_TOOL_SETTINGS(eda_palace) # EDA Netlist Writer Assignments # ============================== set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_palace # end EDA_TOOL_SETTINGS(eda_palace) # --------------------------------- # --------------------------------------- # start EDA_TOOL_SETTINGS(eda_simulation) # EDA Netlist Writer Assignments # ============================== set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_simulation # end EDA_TOOL_SETTINGS(eda_simulation) # ------------------------------------- # -------------------------------------------- # start EDA_TOOL_SETTINGS(eda_timing_analysis) # EDA Netlist Writer Assignments # ============================== set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_timing_analysis # end EDA_TOOL_SETTINGS(eda_timing_analysis) # ------------------------------------------ # -------------------------- # start ENTITY(top_pci_scsn) # Timing Assignments # ================== set_instance_assignment -name CLOCK_SETTINGS clk_scsn -to CLK50M set_instance_assignment -name CLOCK_SETTINGS clk_pci -to pci_clk set_instance_assignment -name CLOCK_SETTINGS tck -to scsn_jtg_jtgtms_reg_TCK # end ENTITY(top_pci_scsn) # ------------------------