Generation Report - PCI Compiler v2.4.0 |
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| Entity Name | pci_mt32 | | Variation Name | pci_contr | | Variation HDL | AHDL | | Output Directory | J:\angelov\scsn_trap2\quartus |
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File SummaryIP Toolbench is creating the following files in the output directory: |
| File | Description |
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| pci_contr.tdf | A MegaCore® Variation File. It defines an AHDL top-level description of the customized MegaCore IP block. To use this MegaCore, instantiate the module defined by this file inside of your design. | | pci_contr.cmp | A VHDL component declaration for the MegaCore Variation. The contents of this file should be added to any VHDL architecture which instantiates the MegaCore. | | pci_contr.inc | An AHDL Include Declaration for the MegaCore Variation. This file should be included by any AHDL architecture which instantiates the MegaCore. | | pci_contr_bb.v | A Verilog Black Box file for the MegaCore Variation. This file is used to create a black box for the MegaCore variation when synthesizing your design with third party synthesis tools. Instantiate this entity in your design when synthesizing, and use the MegaCore Variation File when compiling the synthesized design in Quartus® II. | | pci_contr.bsf | Quartus® II Symbol file for the MegaCore Variation. This file can be used in the Quartus II block diagram editor. | | pci_contr.html | This MegaCore report file. |
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MegaCore Variation File Parameters| Name | Value |
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| CLASS_CODE | FF0000 | | DEVICE_ID | 0005 | | REVISION_ID | 01 | | SUBSYSTEM_ID | 0000 | | SUBSYSTEM_VENDOR_ID | 0000 | | TARGET_DEVICE | NEW | | VENDOR_ID | 1172 | | MIN_GRANT | 00 | | MAX_LATENCY | 00 | | CAP_PTR | 40 | | CIS_PTR | 00000000 | | BAR0 | FFF00000 | | BAR1 | FFF00000 | | BAR2 | FFF00000 | | BAR3 | FFF00000 | | BAR4 | FFF00000 | | BAR5 | FFF00000 | | NUMBER_OF_BARS | 1 | | HARDWIRE_BAR0 | 00000000 | | HARDWIRE_BAR1 | 00000000 | | HARDWIRE_BAR2 | 00000000 | | HARDWIRE_BAR3 | 00000000 | | HARDWIRE_BAR4 | 00000000 | | HARDWIRE_BAR5 | 00000000 | | HARDWIRE_EXP_ROM | 00000001 | | EXP_ROM_BAR | FFF00000 | | PCI_66MHZ_CAPABLE | NO | | INTERRUPT_PIN_REG | 0 | | ENABLE_BITS | 00000000 |
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MegaCore Variation File Ports| Name | Direction | Width |
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| clk | INPUT | 1 | | rstn | INPUT | 1 | | gntn | INPUT | 1 | | idsel | INPUT | 1 | | l_adi | INPUT | 32 | | l_cbeni | INPUT | 4 | | lm_req32n | INPUT | 1 | | lm_lastn | INPUT | 1 | | lm_rdyn | INPUT | 1 | | lt_rdyn | INPUT | 1 | | lt_abortn | INPUT | 1 | | lt_discn | INPUT | 1 | | lirqn | INPUT | 1 | | intan | OUTPUT | 1 | | reqn | OUTPUT | 1 | | serrn | OUTPUT | 1 | | l_adro | OUTPUT | 32 | | l_dato | OUTPUT | 32 | | l_beno | OUTPUT | 4 | | l_cmdo | OUTPUT | 4 | | lm_adr_ackn | OUTPUT | 1 | | lm_ackn | OUTPUT | 1 | | lm_dxfrn | OUTPUT | 1 | | lm_tsr | OUTPUT | 10 | | lt_framen | OUTPUT | 1 | | lt_ackn | OUTPUT | 1 | | lt_dxfrn | OUTPUT | 1 | | lt_tsr | OUTPUT | 12 | | cmd_reg | OUTPUT | 6 | | stat_reg | OUTPUT | 6 | | cache | OUTPUT | 8 | | ad | BIDIR | 32 | | cben | BIDIR | 4 | | par | BIDIR | 1 | | perrn | BIDIR | 1 | | framen_in | INPUT | 1 | | irdyn_in | INPUT | 1 | | devseln_in | INPUT | 1 | | trdyn_in | INPUT | 1 | | stopn_in | INPUT | 1 | | framen_out | OUTPUT | 1 | | irdyn_out | OUTPUT | 1 | | devseln_out | OUTPUT | 1 | | trdyn_out | OUTPUT | 1 | | stopn_out | OUTPUT | 1 |
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