Network-interface to CPU:

 IRQ is set on any incoming frame. and reset when reading
 the status register.

      address         : in  std_logic_vector( 3 downto 0);
      WE,CS           : in  std_logic;
      data_in         : in  std_logic_vector(15 downto 0);
      data_out        : out std_logic_vector(15 downto 0);
      IRQ             : out std_logic;

 address

 Ring 0:
 0, 1 - Data
 2    - address (Global I/O)
 3    - command
 4    - mcmaddress, writing here also starts sending
 7    - status (bits 3-0 equal for both rings) (read only)
 Ring 1:
 8, 9 - Data
 10   - address (Global I/O)
 11   - command
 12   - mcmaddress, writing here also starts sending
 15   - status (bits 3-0 equal for both rings) (read only)

 mcmaddress "0" is the reserved id for this master-unit.
 so first mcm in row is addressed with "1".
 setting mcmaddress to 127 means broadcast.

 Status Data
      status(0) <= d0_recieved
      status(1) <= d0_recieve_error
      status(2) <= recieved frame (ring0) is an answer-frame
      status(3) <= currently sending data out on ring0.
      status(4) <= d1_recieved
      status(5) <= d1_recieve_error
      status(6) <= recieved frame (ring1) is an answer-frame
      status(7) <= currently sending data out on ring1.
      status(15 downto 8) <= hop counter of recieved frame.

 MCM-Commands
              0x1 -> read
              0x2 -> write
              0x3 -> read_broadcast (check status)
                     MCM performs read. and if read_data[0] is '1'
                     this command is interpreted as read and
                     replied, else the command-request
                     it is forwarded to the next MCM.
              0x4 -> bridge
                     set bridge to value of data[0]
                     '0' is serial, '1' is bridged
                     default state after reset is '0'. address is ignored.
              0x7 -> NOP
                     just forward the frame.

BAR(0) - scsn master
DWORD addresses
Base address of the scsn master is 0x000
Base address of the soft reset  is 0x040
Base address of the pretriggger enc is 0x010
Base address of the config register is 0x020 (16-bit)
currently the lower 8 bits will be shown on the LED display

--- JTAG Master for TRAP3 - Base address 0x100

NOTE!!! When reading through JTAG:
        1) For inputs these are the input values at the chip pins
        2) For outputs are the output values from chip core
        When writing through jtag:
        1) For outputs these are the output values at the chip pins
        2) For inputs are the input values to the chip core

        jtag masters

   Offset
    0       rw  JTAG group (see below)
    0x20    rw  identical to 0, for compatibility only
    0x40    rw  identical to 0, for compatibility only
    0x60    rw  identical to 0, for compatibility only
    0x80    rw  identical to 0, for compatibility only

                Bit
    0xA0    r   0       status of the tms state machine, 0 ready, 1 busy
    0xA0+i  w   31..0   shifts i+1 bits of the write data (LSB first)
                        to the TMS

    0xC0    rw  1..0    speed of the TMS sender, 0 slowest, 3 fastest.
            rw  2       JTAG enable for chip 1
            rw  3       JTAG enable for chip 2
            rw  4       JTAG enable for chip 3
            rw  5       JTAG enable for chip 4
            rw  6       JTAG enable for chip 5

    0xE0    r   4       TDO
            r   3..0    the expected state of the JTAG state machine
                        in TRAP (see below)



   JTAG group (for one TRAP3 chip):

   For x = 0..3 the NI_Px_JTAG register has the following structure:
        14          13          12         11       10        9..0
    NI_Px_CTRL NI_Px_PREout NI_Px_CLKout   -     NI_Px_STRB  NI_Px_D

    NI_P4_JTAG
        14          13          12         11       10        9..0
    NI_P4_CTRL   PTRG_IN   CLK_DIG_IN   NI_P_CTRL NI_P4_STRB  NI_P4_D

   Mapping to the IO:
   Offset       Bits        Name
    0           14.. 0      NI_P0_JTAG
                30..16      NI_P1_JTAG
    1           14.. 0      NI_P2_JTAG
                30..16      NI_P3_JTAG
    2           14.. 0      NI_P4_JTAG
                 16         SER0_DIN
                 17         SER0_DOUT
    3            1..0       JTAG instr register


   The states of the JTAG state machine:

    0   0000  Test_Logic_Reset
    1   0001  Run_Test_Idle
    2   0010  Select_DR_Scan
    3   0011  Capture_DR
    4   0100  Shift_DR
    5   0101  Exit1_DR
    6   0110  Pause_DR
    7   0111  Exit2_DR
    8   1000  Update_DR
    9   1001  Select_IR_Scan
   10   1010  Capture_IR
   11   1011  Shift_IR
   12   1100  Exit1_IR
   13   1101  Pause_IR
   14   1110  Exit2_IR
   15   1111  Update_IR




  ADC connector on the ACEX board
       ----------------
      / VCC     ADCOEn |
      |                |
      | ADCCLK  io15   |
      |                |
      | io14    io13   |
      |                |
      | io12    io11   |
      |                |
      | io10    io9    |
      |                |
      | io8     io7    |
      |                |
      | io6     io5    |
      |                |
      | io4     TCK    |
      |                |
      | TMS     TDI    |
      |                |
      | TDO     GND    |
      |________________|

PS2, Keyboard, KDAT io0
PS2, Keyboard, KCLK io1
PS2, Mouse   , MDAT io2
PS2, Mouse   , MCLK io3

writing to 0x20 sets internal the output(15..0)
writing to 0x80 sets output_enable(15..0)
reading from 0x20 gets as bits 15..0 output(15..0)
reading from 0x80 gets as bits 15..0 output_enable(15..0)
reading from 0x20 or 0x80 gets as bits 31..16 the actual input(15..0)