F:\Mentor\LeoSpec\LS2004b_56\bin\win32\spectrum -file read_pci_master.tcl \ -logfile REPORTS/compile_pci_master.txt ------------------------------------------------- LeonardoSpectrum Level 3 - 2004b.56 (Release Production Release, compiled Feb 14 2005 at 16:36:15) Copyright 1990-2004 Mentor Graphics. All rights reserved. Portions copyright 1991-2004 Compuware Corporation Checking Security ... Info, Working Directory is now 'J:/angelov/scsn_trap2' Info, Log file moved to new working directory -- Reading file F:\Mentor\LeoSpec\LS2004b_56\\data\standard.vhd for unit standard -- Loading package standard into library std -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/hamm34enc67.vhd into library work -- Reading file F:\Mentor\LeoSpec\LS2004b_56\\data\std_1164.vhd for unit STD_LOGIC_1164 -- Loading package std_logic_1164 into library IEEE -- Loading entity hamm34enc67 into library work -- Loading architecture a of hamm34enc67 into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/hamm67dec34.vhd into library work -- Loading entity hamm67dec34 into library work -- Loading architecture a of hamm67dec34 into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/hamm_reg.vhd into library work -- Searching for SYNOPSYS package std_logic_arith.. -- Reading file F:\Mentor\LeoSpec\LS2004b_56\\data\syn_arit.vhd for unit std_logic_arith -- Loading package std_logic_arith into library IEEE -- Searching for SYNOPSYS package std_logic_unsigned.. -- Reading file F:\Mentor\LeoSpec\LS2004b_56\\data\syn_unsi.vhd for unit std_logic_unsigned -- Loading package STD_LOGIC_UNSIGNED into library IEEE -- Loading entity hamm_reg into library work -- Loading architecture a of hamm_reg into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_apl.vhd into library work -- Loading entity mcm_nw_apl into library work -- Loading architecture structural of mcm_nw_apl into library work "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_apl.vhd",line 172: Warning, signal req_fall is never used. "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_apl.vhd",line 178: Warning, signal ack_oase is never used. "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_apl.vhd",line 178: Warning, signal ack_oase is never assigned a value. "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_apl.vhd",line 182: Warning, signal bus_req_intrnl is never used. "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_apl.vhd",line 183: Warning, signal bus_we_intrnl is never used. -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_timer.vhd into library work -- Loading entity mcm_nw_timer into library work -- Loading architecture structural of mcm_nw_timer into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_destuffing.vhd into library work -- Loading entity mcm_nw_destuffing into library work -- Loading architecture structural of mcm_nw_destuffing into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_stuffing.vhd into library work -- Loading entity mcm_nw_stuffing into library work -- Loading architecture structural of mcm_nw_stuffing into library work "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_stuffing.vhd",line 60: Warning, signal stuff is never used. "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_stuffing.vhd",line 60: Warning, signal stuff is never assigned a value. -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_outbuf.vhd into library work -- Loading entity mcm_nw_outbuf into library work -- Loading architecture structural of mcm_nw_outbuf into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_inbuf.vhd into library work -- Loading entity mcm_nw_inbuf into library work -- Loading architecture structural of mcm_nw_inbuf into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_bittiming.vhd into library work -- Loading entity mcm_nw_bittiming into library work -- Loading architecture structural of mcm_nw_bittiming into library work "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_bittiming.vhd",line 123: Warning, signal sync_debug is never used. -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_sendtiming.vhd into library work -- Loading entity mcm_nw_sendtiming into library work -- Loading architecture structural of mcm_nw_sendtiming into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_dll.vhd into library work -- Loading entity mcm_nw_dll into library work -- Loading architecture structural of mcm_nw_dll into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_nwsl.vhd into library work -- Loading entity mcm_nw_nwsl into library work -- Loading architecture structural of mcm_nw_nwsl into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_nwl.vhd into library work -- Loading entity mcm_nw_nwl into library work -- Loading architecture structural of mcm_nw_nwl into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_pl.vhd into library work -- Loading entity mcm_nw_pl into library work -- Loading architecture structural of mcm_nw_pl into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_scsn/mcm_excalibur_simulator.vhd into library work -- Loading entity mcm_excalibur_simulator into library work "J:/angelov/scsn_trap2/SRC_scsn/mcm_excalibur_simulator.vhd",line 120: Info, Enumerated type excalibur_send_state_type with 3 elements encoded as binary. Encodings for excalibur_send_state_type values value excalibur_send_state_type[1-0] =============================================== idle 00 start_send -1 wait_for_send_to_finish 10 -- Loading architecture structural of mcm_excalibur_simulator into library work "J:/angelov/scsn_trap2/SRC_scsn/mcm_excalibur_simulator.vhd",line 128: Warning, signal d0_recv_buffer_half is never used. "J:/angelov/scsn_trap2/SRC_scsn/mcm_excalibur_simulator.vhd",line 133: Warning, signal d1_recv_buffer_half is never used. -- Reading vhdl file J:/angelov/scsn_trap2/SRC/par2ser_pci.vhd into library work -- Loading entity par2ser_pci into library work "J:/angelov/scsn_trap2/SRC/par2ser_pci.vhd",line 79: Info, Enumerated type sm with 5 elements encoded as onehot. Encodings for sm values value sm[4-0] ======================== waiting ----1 shd ---1- shc --1-- str -1--- str1 1---- -- Loading architecture a of par2ser_pci into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC/pre_enc.vhd into library work -- Loading entity pre_enc into library work "J:/angelov/scsn_trap2/SRC/pre_enc.vhd",line 36: Info, Enumerated type sm with 2 elements encoded as binary. Encodings for sm values value sm[0] ================= idle 0 send 1 -- Loading architecture a of pre_enc into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC/pre_dir.vhd into library work -- Loading entity pre_dir into library work -- Loading architecture a of pre_dir into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC/tsr_translate.vhd into library work -- Loading entity tsr_translate into library work -- Loading architecture a of tsr_translate into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC/decoder.vhd into library work -- Loading entity decoder into library work -- Loading architecture a of decoder into library work "J:/angelov/scsn_trap2/SRC/decoder.vhd",line 103: Warning, signal Q_par2s is never used. "J:/angelov/scsn_trap2/SRC/decoder.vhd",line 103: Warning, signal Q_par2s is never assigned a value. "J:/angelov/scsn_trap2/SRC/decoder.vhd",line 29: Warning, output SCLK is never assigned a value. "J:/angelov/scsn_trap2/SRC/decoder.vhd",line 30: Warning, output SDAT is never assigned a value. "J:/angelov/scsn_trap2/SRC/decoder.vhd",line 31: Warning, output SSTR is never assigned a value. -- Reading vhdl file J:/angelov/scsn_trap2/SRC_JTAG/jtag_sm.vhd into library work -- Loading entity jtag_sm into library work "J:/angelov/scsn_trap2/SRC_JTAG/jtag_sm.vhd",line 22: Info, Enumerated type JTAG_states with 16 elements encoded as onehot. Encodings for JTAG_states values value JTAG_states[15-0] ================================== Test_Logic_Reset ---------------1 Run_Test_Idle --------------1- Select_DR_Scan -------------1-- Capture_DR ------------1--- Shift_DR -----------1---- Exit1_DR ----------1----- Pause_DR ---------1------ Exit2_DR --------1------- Update_DR -------1-------- Select_IR_Scan ------1--------- Capture_IR -----1---------- Shift_IR ----1----------- Exit1_IR ---1------------ Pause_IR --1------------- Exit2_IR -1-------------- Update_IR 1--------------- -- Loading architecture a of jtag_sm into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_JTAG/jtag_send.vhd into library work -- Loading entity jtag_send into library work -- Loading architecture a of jtag_send into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_JTAG/jtag_recv.vhd into library work -- Loading entity jtag_recv into library work -- Loading architecture a of jtag_recv into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_JTAG/jtag_tms.vhd into library work -- Loading entity jtag_tms into library work "J:/angelov/scsn_trap2/SRC_JTAG/jtag_tms.vhd",line 37: Info, Enumerated type tms_sm_type with 4 elements encoded as binary. Encodings for tms_sm_type values value tms_sm_type[1-0] ================================= idle 00 wait_ch 01 wait_cl 10 finish 11 -- Loading architecture a of jtag_tms into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC_JTAG/jtag_master.vhd into library work -- Loading entity jtag_master into library work -- Loading architecture a of jtag_master into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC/scsn_pci.vhd into library work -- Loading entity scsn_pci into library work -- Loading architecture a of scsn_pci into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC/s7segm.vhd into library work -- Loading entity s7segm into library work -- Loading architecture angel of s7segm into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC/dbl7seg.vhd into library work -- Loading entity dbl7seg into library work -- Loading architecture angel of dbl7seg into library work -- Reading vhdl file J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd into library work -- Loading entity top_pci_scsn into library work -- Loading architecture a of top_pci_scsn into library work "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 181: Warning, signal lm_req32n is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 182: Warning, signal lm_req64n is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 182: Warning, signal lm_req64n is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 194: Warning, signal l_hdat_ackn is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 194: Warning, signal l_hdat_ackn is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 195: Warning, signal lm_adr_ackn is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 195: Warning, signal lm_adr_ackn is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 196: Warning, signal lm_ackn is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 196: Warning, signal lm_ackn is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 197: Warning, signal lm_dxfrn is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 197: Warning, signal lm_dxfrn is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 198: Warning, signal lm_tsr is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 198: Warning, signal lm_tsr is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 199: Warning, signal lt_framen is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 199: Warning, signal lt_framen is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 201: Warning, signal lt_dxfrn is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 201: Warning, signal lt_dxfrn is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 212: Warning, signal PreTrigg_dir is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 215: Warning, signal LVDS0i is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 218: Warning, signal req64n is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 218: Warning, signal req64n is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 219: Warning, signal acq64n is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 219: Warning, signal acq64n is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 220: Warning, signal par64 is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 220: Warning, signal par64 is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 233: Warning, signal sc_out is never used. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 12: Warning, output pci_reqn is never assigned a value. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 23: Warning, input pci_lockn is never used. -- Compiling root entity top_pci_scsn(a) "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 174: Warning, component LCELL has no visible entity binding. "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 169: Warning, component GLOBAL has no visible entity binding. -- Compiling entity pre_dir(a) -- Compiling entity dbl7seg(angel) -- Compiling entity s7segm(angel) -- Compiling entity scsn_pci(a) -- Compiling entity jtag_master_2(a) -- Compiling entity jtag_send_4(a) -- Compiling entity jtag_recv_2(a) -- Compiling entity jtag_sm(a) -- Compiling entity jtag_tms(a) "J:/angelov/scsn_trap2/SRC_JTAG/jtag_tms.vhd",line 41: Info, others clause is never selected for synthesis. "J:/angelov/scsn_trap2/SRC_JTAG/jtag_master.vhd",line 320: Info, others clause is never selected for synthesis. "J:/angelov/scsn_trap2/SRC/scsn_pci.vhd",line 113: Warning, component lpm_counter has no visible entity binding. -- Compiling entity decoder(a) -- Compiling entity tsr_translate(a) -- Compiling entity mcm_excalibur_simulator(structural) -- Compiling entity mcm_nw_pl_1(structural) -- Compiling entity mcm_nw_dll_4_2_7_63_69_4_7(structural) -- Compiling entity mcm_nw_inbuf_69_4_7(structural) -- Compiling entity mcm_nw_outbuf_69_7(structural) -- Compiling entity mcm_nw_bittiming_4_2_7_7_2(structural) -- Compiling entity mcm_nw_timer_4_2(structural) -- Compiling entity mcm_nw_destuffing_7(structural) "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_bittiming.vhd",line 268: Warning, sync_counter is not assigned under reset; need loops to preserve its value. -- Compiling entity hamm_reg_4_0_1(a) -- Compiling entity mcm_nw_sendtiming_4_7_63(structural) -- Compiling entity mcm_nw_timer_4_0(structural) -- Compiling entity mcm_nw_timer_63_63(structural) -- Compiling entity mcm_nw_stuffing_7(structural) -- Compiling entity hamm_reg_3_0_1(a) "J:/angelov/scsn_trap2/SRC_scsn/mcm_excalibur_simulator.vhd",line 150: Warning, new_frame is not always assigned. Storage may be needed.. -- Compiling entity pre_enc(a) "J:/angelov/scsn_trap2/SRC/top_pci_scsn.vhd",line 104: Warning, component pci_contr has no visible entity binding. Warning, Multiple drivers on lm_rdyn. -- Boundary optimization. -- Boundary optimization. -- Start pre-optimization for design .work.s7segm.angel -- Start pre-optimization for design .work.dbl7seg.angel_unfold_1539 -- Start pre-optimization for design .work.jtag_send_4.a_unfold_1547 -- Start pre-optimization for design .work.jtag_recv_2.a_unfold_1553 -- Start pre-optimization for design .work.jtag_sm.a -- Start pre-optimization for design .work.jtag_tms.a "J:/angelov/scsn_trap2/SRC_JTAG/jtag_tms.vhd", line 75:Info, Inferred counter instance 'b_cnt' of type 'counter_dn_cnt_en_sload_clock_5' -- Start pre-optimization for design .work.jtag_master_2.a_unfold_1014 -- Start pre-optimization for design .work.decoder.a_unfold_989 -- Start pre-optimization for design .work.mcm_nw_pl_1.structural_unfold_3025 -- Start pre-optimization for design .work.mcm_nw_inbuf_69_4_7.structural_unfold_2439_0 "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_inbuf.vhd", line 133:Info, Inferred counter instance 'bitcounter' of type 'counter_up_cnt_en_sclear_aclear_clock_7' -- Start pre-optimization for design .work.mcm_nw_outbuf_69_7.structural_unfold_2445_0 "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_outbuf.vhd", line 133:Info, Inferred counter instance 'bitcounter' of type 'counter_up_cnt_en_sclear_aclear_clock_7' -- Start pre-optimization for design .work.mcm_nw_timer_4_2.structural_unfold_3126 -- Start pre-optimization for design .work.mcm_nw_destuffing_7.structural "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_destuffing.vhd", line 78:Info, Inferred counter instance 'counter' of type 'counter_up_sclear_clock_clk_en_3' -- Start pre-optimization for design .work.hamm_reg_4_0_1.a -- Start pre-optimization for design .work.mcm_nw_bittiming_4_2_7_7_2.structural -- Start pre-optimization for design .work.mcm_nw_timer_4_0.structural_unfold_3057 -- Start pre-optimization for design .work.mcm_nw_timer_63_63.structural_unfold_3220 -- Start pre-optimization for design .work.mcm_nw_stuffing_7.structural "J:/angelov/scsn_trap2/SRC_scsn/mcm_nw_stuffing.vhd", line 78:Info, Inferred counter instance 'state' of type 'counter_up_sclear_aclear_clock_clk_en_3' -- Start pre-optimization for design .work.hamm_reg_3_0_1.a -- Start pre-optimization for design .work.mcm_nw_sendtiming_4_7_63.structural -- Start pre-optimization for design .work.mcm_nw_dll_4_2_7_63_69_4_7.structural_unfold_3089 -- Start pre-optimization for design .work.mcm_excalibur_simulator.structural_unfold_1824 -- Start pre-optimization for design .work.pre_enc.a "J:/angelov/scsn_trap2/SRC/pre_enc.vhd", line 92:Info, Inferred counter instance 'counter' of type 'counter_dn_sload_aset_clock_2' -- Start pre-optimization for design .work.scsn_pci.a_unfold_1402 -- Start pre-optimization for design .work.top_pci_scsn.a -- Start pre-optimization for design .work.s7segm.angel -- Start pre-optimization for design .work.dbl7seg.angel_unfold_1539 -- Start pre-optimization for design .work.jtag_send_4.a_unfold_1547 -- Start pre-optimization for design .work.jtag_recv_2.a_unfold_1553 -- Start pre-optimization for design .work.jtag_sm.a -- Start pre-optimization for design .work.jtag_tms.a -- Start pre-optimization for design .work.jtag_master_2.a_unfold_1014 -- Start pre-optimization for design .work.decoder.a_unfold_989 -- Start pre-optimization for design .work.mcm_nw_pl_1.structural_unfold_3025 -- Start pre-optimization for design .work.mcm_nw_inbuf_69_4_7.structural_unfold_2439_0 -- Start pre-optimization for design .work.mcm_nw_outbuf_69_7.structural_unfold_2445_0 -- Start pre-optimization for design .work.mcm_nw_timer_4_2.structural_unfold_3126 -- Start pre-optimization for design .work.mcm_nw_destuffing_7.structural -- Start pre-optimization for design .work.hamm_reg_4_0_1.a -- Start pre-optimization for design .work.mcm_nw_bittiming_4_2_7_7_2.structural -- Start pre-optimization for design .work.mcm_nw_timer_4_0.structural_unfold_3057 -- Start pre-optimization for design .work.mcm_nw_timer_63_63.structural_unfold_3220 -- Start pre-optimization for design .work.mcm_nw_stuffing_7.structural -- Start pre-optimization for design .work.hamm_reg_3_0_1.a -- Start pre-optimization for design .work.mcm_nw_sendtiming_4_7_63.structural -- Start pre-optimization for design .work.mcm_nw_dll_4_2_7_63_69_4_7.structural_unfold_3089 -- Start pre-optimization for design .work.mcm_excalibur_simulator.structural_unfold_1824 -- Start pre-optimization for design .work.pre_enc.a -- Start pre-optimization for design .work.scsn_pci.a_unfold_1402 -- Start pre-optimization for design .work.top_pci_scsn.a Info: setting part to EP1K100QC208 Info: setting process to 1 Reading library file `F:\Mentor\LeoSpec\LS2004b_56\\lib\acex1.syn`... Library version = 4.5 Delays assume: Process=1 Info: setting encoding to auto Using default wire table: STD-1 -- Start optimization for design .work.top_pci_scsn.a Using default wire table: STD-1 Warning, port pci_reqn is connected to a disabled tristate, possibly unconnected port in design. est est Pass LCs Delay DFFs TRIs PIs POs --CPU-- min:sec 1 1545 14 877 0 8 83 00:19 2 1845 12 877 0 8 83 00:24 3 1862 12 877 0 8 83 00:32 4 1589 14 877 0 8 83 00:26 Info, Pass 1 was selected as best. Info: setting opt_best_result to 21212.850000 Info: setting opt_best_pass to 1 Using default wire table: STD-1 -- Start timing optimization for design .work.top_pci_scsn.a No critical paths to optimize at this level AutoWrite args are : NETLIST/top_pci_scsn.edf -- Applying renaming rule 'ALTERA' to database Warning, Renaming will cause your database to change -- Calling set_altera_eqn to set up writing Equations Info: setting edif_eqn_or to + Info: setting edif_eqn_and to Info: setting edif_eqn_not to ' Info: setting edif_eqn_not_is_prefix to FALSE Info: setting edif_function_property to lut_function -- Writing file NETLIST/top_pci_scsn.edf Info, About to call 'setacf' for generating/modifying ACF file Info, 'setacf' done. Info, Writing batch file 'NETLIST/top_pci_scsn.tcl' Info: setting quartus_exec_path to F:\altera\quartus50/bin Using default wire table: STD-1