-- -- Transition Radiation Detector -- -- MCM Control Unit - Configuration Network -- -- -- -- $Id: mcm_nw_dll.vhd,v 1.1 2002/05/16 08:33:38 rgareus Exp $ -- -- Robin Gareus, Kirchhoff Institute for Physics, Heidelberg -- rgareus@kip.uni-heidelberg.de -- ------------------------------------------------------------ -- -- Data Link Layer (dll) Implementation -- See .../report_1/main.ps (page 7 ff.) -- -- there are two sender and two reciever parts build up: -- incoming data is fed through the bittiming-unit (generate strobe, -- destuff) into the input-buffer, that verifys the Checksum -- -- outgoing data is buffered (output-buffer) and -- serialized by the sendtiming-unit, that also adds in stuff bits. -- during the serialisation a checksum is generated in the output-buffer. -- -- this file only connects internal components (port maps) -- the only process in here is to bridge the network-outputs. -- -- To physical layer there are signals of serialized data to be -- transmitted over the network. -- -- The interface to Network layer is described in detail in -- .../report_2/main.ps -- -- here's a summary of the Signals: -- (recv) -- dX_to_nwl : buffered revieved data -- sX_to_nwl : strobe - buffered data is valid. -- bufX_half : buffer is almost full. - see inbuf source documentation -- bufX_err : frame with incorrect checksum recvieved. -- (send) -- dX_fr_nwl : data to be sent -- dX_we : write enable. 'd0_fr_nwl' is stored in output-buffer -- dX_send : initiate send of the buffered data -- dX_buffer_ready : buffer is writeable <=> currently not sending. -- (x-bar) -- bridge : cross the output lines. divide into 2 Rings. -- -- All the generic values in here are just forwarded to -- the internal components, and are documented there, as well as -- in the top-level entity. -- -------------------------------------------------- -- standard includes, library definitions. -------------------------------------------------- library ieee,work; use ieee.std_logic_1164.all; use work.mcm_nw_bittiming; use work.mcm_nw_inbuf; use work.mcm_nw_outbuf; use work.mcm_nw_sendtiming; -------------------------------------------------- -- ENTITY -------------------------------------------------- entity mcm_nw_dll is generic (timing_count_range : integer := 7; timing_recv_on : integer := 2; stuff_length : integer := 4; timing_sleep_length : integer := 63; BUFSIZ : integer := 69; BUFHALF : integer := 4; COUNTER : integer := 7); port( -- Signals from/to phyiscal layer : serial data d0_fr_pl : in std_logic; d0_to_pl : out std_logic; d1_fr_pl : in std_logic; d1_to_pl : out std_logic; clk_buf : in std_logic; -- Signals to Network Layer (recv) d0_to_nwl : out std_logic_vector(BUFSIZ-1 downto 0); s0_to_nwl : out std_logic ; buf0_half : out std_logic ; buf0_err : out std_logic ; d1_to_nwl : out std_logic_vector(BUFSIZ-1 downto 0); s1_to_nwl : out std_logic ; buf1_half : out std_logic ; buf1_err : out std_logic ; -- Signals from Network Layer (send) d0_fr_nwl : in std_logic_vector(BUFSIZ-1 downto 0); d0_we : in std_logic; d0_send : in std_logic; d0_buffer_ready : out std_logic; d1_fr_nwl : in std_logic_vector(BUFSIZ-1 downto 0); d1_we : in std_logic; d1_send : in std_logic; d1_buffer_ready : out std_logic; -- X-bar data paths bridge : in std_logic; reset_n : in std_logic; clk : in std_logic ); end mcm_nw_dll; -------------------------------------------------- -- ARCHITECTURE -------------------------------------------------- architecture structural of mcm_nw_dll is -------------------------------------------------- -- internal signals -------------------------------------------------- SIGNAL ib0_half,ib0_full,ib0_strobe,ib0_data,ib0_flush_n,ib0_to_nwl : std_logic; SIGNAL ob0_request,ob0_data,ob0_freeze,ob0_empty : std_logic; SIGNAL ib1_half,ib1_full,ib1_strobe,ib1_data,ib1_flush_n,ib1_to_nwl : std_logic; SIGNAL ob1_request,ob1_data,ob1_freeze,ob1_empty : std_logic; SIGNAL d0_out,d1_out : std_logic; -------------------------------------------------- -- components -------------------------------------------------- COMPONENT mcm_nw_inbuf generic ( BUFSIZ : integer := 69; BUFHALF : integer := 4; COUNTER : integer := 7 ); port( -- Signals to/from bittiming/destuffing in DLL strobe_in : in std_logic; data_in : in std_logic; flush_in_n : in std_logic; buffer_half : out std_logic; buffer_full : out std_logic; -- Signals to upper layer data_out : out std_logic_vector (BUFSIZ-1 DOWNTO 0); data_valid : out std_logic; -- clock and reset clk_buf : in std_logic; clk : in std_logic; reset_n : in std_logic ); END COMPONENT; COMPONENT mcm_nw_outbuf is generic ( BUFSIZ : integer := 69; COUNTER : integer := 7 ); port( -- Signals to Serial Link (bittiming/stuffing) in DLL request_in : in std_logic; freeze_in : in std_logic; data_out : out std_logic; buffer_empty : out std_logic; -- Signals to upper layer data_in : in std_logic_vector (BUFSIZ-1 DOWNTO 0); buffer_ready : out std_logic; data_we : in std_logic; -- clock and reset clk_buf : in std_logic; clk : in std_logic; reset_n : in std_logic ); END COMPONENT; COMPONENT mcm_nw_bittiming generic ( timing_count_range : integer := 7; timing_recv_on : integer := 2; stuff_length : integer := 4 ); port( -- Signals to phyiscal layer d_fr_pl : in std_logic ; -- Signals to/from inputbuffer strobe_out : out std_logic; data_out : out std_logic; buffer_full : in std_logic; buffer_flush_n : out std_logic; reset_n : in std_logic; clk : in std_logic ); END COMPONENT; COMPONENT mcm_nw_sendtiming is generic ( timing_count_range : integer := 7; stuff_length : integer := 4; timing_sleep_length : integer := 63 ); port( -- Signals to phyiscal layer data_out_to_pl : out std_logic; --- Input Buffer initiate_send : in std_logic; -- start freezing out buffer --- Output Buffer buffer_empty : in std_logic; -- no more data in buffer data_in : in std_logic; -- next data from buffer request_data : out std_logic; -- strobe_in (read next enable) freeze_buffer : out std_logic; -- set pointer to start of buffer -- buffer is now r/o -> -- command is no longer exec. reset_n : in std_logic; clk : in std_logic ); END COMPONENT; -------------------------------------------------- -- port maps -------------------------------------------------- begin -- -- Data Path 0 -- ib0: mcm_nw_inbuf generic map ( BUFSIZ => BUFSIZ, BUFHALF => BUFHALF, COUNTER => COUNTER ) port map ( strobe_in => ib0_strobe, data_in => ib0_data, buffer_half => ib0_half, buffer_full => ib0_full, flush_in_n => ib0_flush_n, data_out => d0_to_nwl, data_valid => ib0_to_nwl, clk_buf => clk_buf, clk => clk, reset_n => reset_n ); ob0: mcm_nw_outbuf generic map ( BUFSIZ => BUFSIZ, COUNTER => COUNTER ) port map ( request_in => ob0_request, data_out => ob0_data, freeze_in => ob0_freeze, buffer_empty => ob0_empty, data_in => d0_fr_nwl, buffer_ready => d0_buffer_ready, data_we => d0_we, clk_buf => clk_buf, clk => clk, reset_n => reset_n ); bt0: mcm_nw_bittiming generic map(timing_count_range => timing_count_range, timing_recv_on => timing_recv_on, stuff_length => stuff_length ) port map ( d_fr_pl => d0_fr_pl, strobe_out => ib0_strobe, data_out => ib0_data, buffer_full => ib0_full, buffer_flush_n => ib0_flush_n, reset_n => reset_n, clk => clk ); st0: mcm_nw_sendtiming generic map(timing_count_range => timing_count_range, timing_sleep_length => timing_sleep_length, stuff_length => stuff_length ) port map ( data_out_to_pl => d0_out, initiate_send => d0_send, data_in => ob0_data, request_data => ob0_request, buffer_empty => ob0_empty, freeze_buffer => ob0_freeze, reset_n => reset_n, clk => clk ); buf0_half <= ib0_half; buf0_err <= ib0_full and (not ib0_to_nwl); s0_to_nwl <= ib0_to_nwl; -- -- Data Path 1 -- ib1: mcm_nw_inbuf generic map ( BUFSIZ => BUFSIZ, BUFHALF => BUFHALF, COUNTER => COUNTER ) port map ( strobe_in => ib1_strobe, data_in => ib1_data, buffer_half => ib1_half, buffer_full => ib1_full, flush_in_n => ib1_flush_n, data_out => d1_to_nwl, data_valid => ib1_to_nwl, clk_buf => clk_buf, clk => clk, reset_n => reset_n ); ob1: mcm_nw_outbuf generic map ( BUFSIZ => BUFSIZ, COUNTER => COUNTER ) port map ( request_in => ob1_request, data_out => ob1_data, freeze_in => ob1_freeze, buffer_empty => ob1_empty, data_in => d1_fr_nwl, buffer_ready => d1_buffer_ready, data_we => d1_we, clk_buf => clk_buf, clk => clk, reset_n => reset_n ); bt1: mcm_nw_bittiming generic map(timing_count_range => timing_count_range, timing_recv_on => timing_recv_on, stuff_length => stuff_length ) port map ( d_fr_pl => d1_fr_pl, strobe_out => ib1_strobe, data_out => ib1_data, buffer_full => ib1_full, buffer_flush_n => ib1_flush_n, reset_n => reset_n, clk => clk ); st1: mcm_nw_sendtiming generic map(timing_count_range => timing_count_range, timing_sleep_length => timing_sleep_length, stuff_length => stuff_length ) port map ( data_out_to_pl => d1_out, initiate_send => d1_send, data_in => ob1_data, request_data => ob1_request, buffer_empty => ob1_empty, freeze_buffer => ob1_freeze, reset_n => reset_n, clk => clk ); buf1_half <= ib1_half; buf1_err <= ib1_full and (not ib1_to_nwl); s1_to_nwl <= ib1_to_nwl; -------------------------------------------------- -- processes -------------------------------------------------- -- crossbar - bridge x_bar_bridge: process (bridge,d0_out,d1_out) begin if (bridge = '0') then d0_to_pl <= d0_out; d1_to_pl <= d1_out; else d0_to_pl <= d1_out; d1_to_pl <= d0_out; end if; end process x_bar_bridge; end structural; -------------------------------------------------- -- CONFIGURATION -------------------------------------------------- -- synopsys translate_off CONFIGURATION mcm_nw_dll_CFG of mcm_nw_dll is for structural for ALL : mcm_nw_inbuf use configuration WORK.mcm_nw_inbuf_CFG; end for; for ALL : mcm_nw_outbuf use configuration WORK.mcm_nw_outbuf_CFG; end for; for ALL : mcm_nw_sendtiming use configuration WORK.mcm_nw_sendtiming_CFG; end for; for ALL : mcm_nw_bittiming use configuration WORK.mcm_nw_bittiming_CFG; end for; end for; end mcm_nw_dll_CFG; -- synopsys translate_on