LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; entity top_pci_scsn is --GENERIC (BaseAddr : Integer := 16#110#); port ( pci_clk : IN STD_LOGIC ; pci_rstn : IN STD_LOGIC ; pci_gntn : IN STD_LOGIC ; pci_idsel : IN STD_LOGIC ; pci_intan : OUT STD_LOGIC ; pci_reqn : OUT STD_LOGIC ; pci_serrn : OUT STD_LOGIC ; pci_framen : INOUT STD_LOGIC ; pci_irdyn : INOUT STD_LOGIC ; pci_devseln : INOUT STD_LOGIC ; pci_trdyn : INOUT STD_LOGIC ; pci_stopn : INOUT STD_LOGIC ; pci_ad : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); pci_cben : INOUT STD_LOGIC_VECTOR ( 3 DOWNTO 0); pci_par : INOUT STD_LOGIC ; pci_perrn : INOUT STD_LOGIC ; pci_lockn : IN STD_LOGIC ; -- SCSN R7S : out std_logic_vector(1 to 7); R7S_mux : out std_logic; LVDS_in : in std_logic_vector(3 downto 0); LVDS_out : out std_logic_vector(3 downto 0); LED_GRN : out std_logic; LED_RED : out std_logic; CLK50M : in std_logic; digital_io : inout std_logic_vector(15 downto 0); -- bits 15..8 = ADC2_D -- bits 7..4 = ADC1_D7..4 -- bits 3..2 = MCLK & MDAT -- bits 1..0 = KCLK & KDAT TCK : out std_logic; -- ADC1_D0..3 TMS : out std_logic; TDI : out std_logic; TDO : in std_logic; -- MCLK : out std_logic; -- MDAT : out std_logic; -- -- KCLK : out std_logic; -- KDAT : out std_logic; LVDS_EN : out std_logic; ADC_OEn : out std_logic; SRAM_CEn : out std_logic; SRAM_OEn : out std_logic ); end top_pci_scsn; -------------------------------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------------------------------- architecture a of top_pci_scsn is component scsn_pci is --GENERIC (BaseAddr : Integer := 16#110#); port ( clk_pci : in std_logic; reset_n : in std_logic; -- the bus interface data_in : in std_logic_vector(31 downto 0); addr_in : in std_logic_vector(31 downto 0); LT_TSR : in std_logic_vector(11 downto 0); LT_CMD : in std_logic_vector( 3 downto 0); LT_ACQ_n : in std_logic; -- L_Ldat_acq_n : in std_logic; LT_RDY_n : out std_logic; data_out : out std_logic_vector(31 downto 0); -- SCSN clk_scsn : in std_logic ; IRQ : out std_logic ; dis_clk : out std_logic ; data_conf : out std_logic_vector(15 downto 0); digital_in : in std_logic_vector(15 downto 0); digital_oe : out std_logic_vector(15 downto 0); -- external Network Interface d_in_0 : in std_logic ; d_out_0 : out std_logic ; d_in_1 : in std_logic ; d_out_1 : out std_logic ; -- SCLK : OUT STD_LOGIC; -- Serial Clock -- SDAT : OUT STD_LOGIC; -- Serial Data -- SSTR : OUT STD_LOGIC; -- Serial Strobe PreTrigg : out std_logic; TCK : out std_logic; TMS : out std_logic; TDI : out std_logic; TDO : in std_logic ); end component; component pci_contr PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; gntn : IN STD_LOGIC; idsel : IN STD_LOGIC; l_adi : IN STD_LOGIC_VECTOR (31 DOWNTO 0); l_cbeni : IN STD_LOGIC_VECTOR (3 DOWNTO 0); lm_req32n : IN STD_LOGIC; lm_lastn : IN STD_LOGIC; lm_rdyn : IN STD_LOGIC; lt_rdyn : IN STD_LOGIC; lt_abortn : IN STD_LOGIC; lt_discn : IN STD_LOGIC; lirqn : IN STD_LOGIC; framen : INOUT STD_LOGIC; irdyn : INOUT STD_LOGIC; devseln : INOUT STD_LOGIC; trdyn : INOUT STD_LOGIC; stopn : INOUT STD_LOGIC; intan : OUT STD_LOGIC; reqn : OUT STD_LOGIC; serrn : OUT STD_LOGIC; l_adro : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); l_dato : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); l_beno : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); l_cmdo : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); lm_adr_ackn : OUT STD_LOGIC; lm_ackn : OUT STD_LOGIC; lm_dxfrn : OUT STD_LOGIC; lm_tsr : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); lt_framen : OUT STD_LOGIC; lt_ackn : OUT STD_LOGIC; lt_dxfrn : OUT STD_LOGIC; lt_tsr : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); cmd_reg : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); stat_reg : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); cache : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); ad : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); cben : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0); par : INOUT STD_LOGIC; perrn : INOUT STD_LOGIC ); end component; component dbl7seg IS PORT( CL, CR : IN STD_LOGIC_VECTOR(3 downto 0); -- code for left/right mx : IN STD_LOGIC; -- 100Hz dis : IN STD_LOGIC; -- disable outputs (switch off) mx_out : OUT STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(1 to 7) -- output to 7segm ind. ); END component; component pre_dir IS PORT( CLK : IN STD_LOGIC; -- fast clock 120MHz RSTn : IN STD_LOGIC; -- global reset (active low) start : IN STD_LOGIC; PRE : OUT STD_LOGIC -- pre-trigger input ); END component; COMPONENT GLOBAL PORT (a_in : IN STD_LOGIC; a_out: OUT STD_LOGIC); END COMPONENT; COMPONENT LCELL PORT (IN1 : IN STD_LOGIC; Y : OUT STD_LOGIC); END COMPONENT; signal l_cbeni : STD_LOGIC_VECTOR ( 3 DOWNTO 0); signal l_adi : STD_LOGIC_VECTOR (31 DOWNTO 0); signal lm_req32n : STD_LOGIC ; signal lm_req64n : STD_LOGIC ; signal lm_lastn : STD_LOGIC ; signal lm_rdyn : STD_LOGIC ; signal lt_rdyn : STD_LOGIC ; signal lt_abortn : STD_LOGIC ; signal lt_discn : STD_LOGIC ; signal lirqn : STD_LOGIC ; signal l_adro : STD_LOGIC_VECTOR (31 DOWNTO 0); signal l_dato : STD_LOGIC_VECTOR (31 DOWNTO 0); --signal l_beno : STD_LOGIC_VECTOR ( 7 DOWNTO 0); signal l_cmdo : STD_LOGIC_VECTOR ( 3 DOWNTO 0); --signal l_ldat_ackn : STD_LOGIC ; signal l_hdat_ackn : STD_LOGIC ; signal lm_adr_ackn : STD_LOGIC ; signal lm_ackn : STD_LOGIC ; signal lm_dxfrn : STD_LOGIC ; signal lm_tsr : STD_LOGIC_VECTOR ( 9 DOWNTO 0); signal lt_framen : STD_LOGIC ; signal lt_ackn : STD_LOGIC ; signal lt_dxfrn : STD_LOGIC ; signal lt_tsr : STD_LOGIC_VECTOR (11 DOWNTO 0); --signal ad_int : STD_LOGIC_VECTOR (63 DOWNTO 0); --signal cben_int : STD_LOGIC_VECTOR ( 7 DOWNTO 0); signal clk_scsn : std_logic; signal d_in_0 : std_logic; signal d_in_1 : std_logic; signal d_out_0 : std_logic; signal d_out_1 : std_logic; signal PreTrigg : std_logic; signal PreTrigg_dir : std_logic; signal dseg : std_logic_vector(7 downto 0); signal slow_clk : std_logic; signal LVDS0i : std_logic; signal clk_pci : std_logic; signal req64n : std_logic; signal acq64n : std_logic; signal par64 : std_logic; signal data_conf : std_logic_vector(15 downto 0); signal clk_mux : std_logic; signal clk25m : std_logic; signal clk_local : std_logic; signal start_pre : std_logic; --signal PA_SCLK : std_logic; --signal PA_SDAT : std_logic; --signal PA_SSTR : std_logic; signal sc_in : std_logic_vector(7 downto 0); -- DUMMY signal sc_out : std_logic_vector(7 downto 0); -- DUMMY signal digital_oe : std_logic_vector(15 downto 0); signal digital_in : std_logic_vector(15 downto 0); begin sc_in <= (others => '0'); -- DUMMY LVDS_EN <= '1'; ADC_OEn <= '1'; SRAM_CEn <= '1'; SRAM_OEn <= '1'; process(clk50m) begin if clk50m'event and clk50m='1' then clk25m <= not clk25m; end if; end process; -- CLK_local <= clk50m when data_conf(14)='0' else clk25m; -- clk_mux <= LVDS0i when ADC2_D(0)='0' else CLK_local; CLK_local <= clk50m; clk_mux <= CLK_local; lc1: LCELL PORT map(IN1 => LVDS_in(0), Y => LVDS0i ); lc2: LCELL PORT map(IN1 => clk_mux , Y => LVDS_out(0)); LVDS_out(1) <= PreTrigg; -- LVDS_out(2) <= d_out_0; -- LVDS_out(3) <= d_out_1; -- LVDS_out(3) <= data_conf(data_conf'high); -- use the power as P4_CTRL sclk: GLOBAL PORT map(a_in => clk_mux, a_out => clk_scsn); pclk: GLOBAL PORT map(a_in => pci_clk, a_out => clk_pci ); -- MCLK <= data_conf(11); -- MDAT <= data_conf(10); -- -- KCLK <= data_conf(9); -- KDAT <= data_conf(8); dseg <= data_conf(dseg'range); LED_GRN <= not data_conf(8); LED_RED <= not data_conf(9); digital_in <= digital_io; --ADC2_D & ADC1_D & MCLK & MDAT & KCLK & KDAT; dio: for i in 0 to 15 generate dioi: digital_io(i) <= data_conf(i) when digital_oe(i)='1' else 'Z'; end generate; -- ADC2_D <= data_conf(15 downto 8); -- ADC1_D <= data_conf(15 downto 8); -- ADC1_D <= data_conf(15 downto 12); -- start_pre <= ADC2_D(2); start_pre <= '0'; pdir: pre_dir PORT map( CLK => clk_scsn, RSTn => pci_rstn, start => start_pre, PRE => PreTrigg_dir ); sg: dbl7seg PORT map( CL => dseg(7 downto 4), CR => dseg(3 downto 0), mx => slow_clk, dis => '0', mx_out => R7S_mux, Q => R7S); process(clk_scsn) begin if clk_scsn'event and clk_scsn='1' then sc_out <= (others => '0'); LVDS_out(2) <= '0'; LVDS_out(3) <= '0'; case data_conf(10 downto 8) is when "100" => d_in_0 <= sc_in(0); d_in_1 <= sc_in(1); sc_out(0) <= d_out_0; sc_out(1) <= d_out_1; when "101" => d_in_0 <= sc_in(2); d_in_1 <= sc_in(3); sc_out(2) <= d_out_0; sc_out(3) <= d_out_1; when "110" => d_in_0 <= sc_in(4); d_in_1 <= sc_in(5); sc_out(4) <= d_out_0; sc_out(5) <= d_out_1; when "111" => d_in_0 <= sc_in(6); d_in_1 <= sc_in(7); sc_out(6) <= d_out_0; sc_out(7) <= d_out_1; when others => d_in_0 <= LVDS_in(2); d_in_1 <= LVDS_in(3); LVDS_out(2) <= d_out_0; LVDS_out(3) <= d_out_1; end case; end if; end process; scsn: scsn_pci port map( clk_pci => clk_pci , reset_n => pci_rstn , -- the bus interface data_in => l_dato , addr_in => l_adro , LT_TSR => lt_tsr , LT_CMD => l_cmdo , LT_ACQ_n => lt_ackn , -- L_Ldat_acq_n => l_ldat_ackn, LT_RDY_n => lt_rdyn , data_out => l_adi , -- SCSN clk_scsn => clk_scsn , IRQ => open , dis_clk => slow_clk , digital_in => digital_in, digital_oe => digital_oe, data_conf => data_conf, -- external Network Interface d_in_0 => d_in_0 , d_out_0 => d_out_0 , d_in_1 => d_in_1 , d_out_1 => d_out_1 , -- SCLK => PA_SCLK, -- SDAT => PA_SDAT, -- SSTR => PA_SSTR, PreTrigg => PreTrigg, TCK => TCK, TMS => TMS, TDI => TDI, TDO => TDO ); -- ADC2oD(4) <= PA_SCLK; -- ADC2oD(5) <= PA_SDAT; -- ADC2oD(6) <= PA_SSTR; -- ADC2oD(7) <= '0'; pci: pci_contr PORT map( clk => clk_pci, rstn => pci_rstn, gntn => pci_gntn, l_cbeni => l_cbeni, idsel => pci_idsel, l_adi => l_adi, lm_req32n => lm_req32n, -- lm_req64n => lm_req64n, lm_lastn => lm_lastn, lm_rdyn => lm_rdyn, lt_rdyn => lt_rdyn, lt_abortn => lt_abortn, lt_discn => lt_discn, lirqn => lirqn, intan => pci_intan, -- reqn => pci_reqn, serrn => pci_serrn, l_adro => l_adro, l_dato => l_dato, l_beno => open, l_cmdo => l_cmdo, -- l_ldat_ackn => l_ldat_ackn, -- l_hdat_ackn => open, -- lm_adr_ackn => open, -- lm_ackn => open, -- lm_dxfrn => open, -- lm_tsr => open, lt_framen => open, lt_ackn => lt_ackn, lt_dxfrn => open, lt_tsr => lt_tsr, cmd_reg => open, stat_reg => open, -- cache => open, framen => pci_framen, irdyn => pci_irdyn, devseln => pci_devseln, trdyn => pci_trdyn, stopn => pci_stopn, -- req64n => req64n, -- ack64n => acq64n, ad => pci_AD, cben => pci_CBEn, par => pci_par, -- par64 => par64, perrn => pci_perrn ); -- req64n <= 'Z'; -- acq64n <= 'Z'; -- par64 <= 'Z'; -- -- pci_AD <= ad_int(pci_AD'range); -- pci_CBEn <= cben_int(pci_CBEn'range); l_cbeni <= (others => '0'); -- lm_req32n <= '1'; -- lm_req64n <= '1'; lm_lastn <= '1'; lm_rdyn <= '1'; lt_abortn <= '1'; lt_discn <= '1'; lirqn <= '1'; end;