LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; entity scsn_pci is port ( clk_pci : in std_logic; reset_n : in std_logic; -- the bus interface data_in : in std_logic_vector(31 downto 0); addr_in : in std_logic_vector(31 downto 0); LT_TSR : in std_logic_vector(11 downto 0); LT_CMD : in std_logic_vector( 3 downto 0); LT_ACQ_n : in std_logic; LT_RDY_n : out std_logic; data_out : out std_logic_vector(31 downto 0); -- SCSN clk_scsn : in std_logic ; IRQ : out std_logic ; dis_clk : out std_logic ; data_conf : out std_logic_vector(15 downto 0); digital_in : in std_logic_vector(15 downto 0); digital_oe : out std_logic_vector(15 downto 0); -- external Network Interface d_in_0 : in std_logic ; d_out_0 : out std_logic ; d_in_1 : in std_logic ; d_out_1 : out std_logic ; SCLK : OUT STD_LOGIC; -- Serial Clock SDAT : OUT STD_LOGIC; -- Serial Data SSTR : OUT STD_LOGIC; -- Serial Strobe PreTrigg : out std_logic; TCK : out std_logic; TMS : out std_logic; TDI : out std_logic; TDO : in std_logic ); end scsn_pci; -------------------------------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------------------------------- architecture a of scsn_pci is component mcm_excalibur_simulator is port( -- external Network Interface d_in_0 : in std_logic ; d_out_0 : out std_logic ; d_in_1 : in std_logic ; d_out_1 : out std_logic ; --- clock and reset Signals reset_n : in std_logic; clk : in std_logic; -- CPU interface address : in std_logic_vector(3 downto 0); CLK_CPU, CS, WE : in std_logic; data_in : in std_logic_vector(15 downto 0); data_out : out std_logic_vector(15 downto 0); IRQ : out std_logic ); end component; component decoder is port( clk_pci : in std_logic; reset_n : in std_logic; data_in_pci : in std_logic_vector(31 downto 0); addr_in_pci : in std_logic_vector(31 downto 0); LT_TSR_pci : in std_logic_vector(11 downto 0); LT_CMD_pci : in std_logic_vector( 3 downto 0); LT_ACQ_n_pci : in std_logic; LT_RDY_n_pci : out std_logic; data_out_pci : out std_logic_vector(31 downto 0); wdata : out std_logic_vector(31 downto 0); word_addr : out std_logic_vector( 7 downto 0); rdata_scsn : in std_logic_vector(15 downto 0); rdata_jtag : in std_logic_vector(31 downto 0); data_conf : out std_logic_vector(15 downto 0); digital_in : in std_logic_vector(15 downto 0); digital_oe : out std_logic_vector(15 downto 0); WE : out std_logic; CS_scsn : out std_logic; CS_jtag : out std_logic; WE_pre_enc : out std_logic; SCLK : OUT STD_LOGIC; -- Serial Clock SDAT : OUT STD_LOGIC; -- Serial Data SSTR : OUT STD_LOGIC; -- Serial Strobe soft_rst_n : out std_logic ); end component; component pre_enc IS PORT( CLK : IN STD_LOGIC; -- fast clock 120MHz RSTn : IN STD_LOGIC; -- global reset (active low) WR : IN STD_LOGIC; -- write clock WE : IN STD_LOGIC; FUNC : IN STD_LOGIC_VECTOR(2 downto 0); -- PRE : OUT STD_LOGIC -- pre-trigger input ); END component; COMPONENT lpm_counter GENERIC (LPM_WIDTH: POSITIVE; LPM_MODULUS: NATURAL := 0; LPM_DIRECTION: STRING := "UNUSED"; LPM_AVALUE: STRING := "UNUSED"; LPM_SVALUE: STRING := "UNUSED"; LPM_PVALUE: STRING := "UNUSED"; LPM_TYPE: STRING := "LPM_COUNTER"; LPM_HINT : STRING := "UNUSED"); PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); clock: IN STD_LOGIC; clk_en, cnt_en, updown: IN STD_LOGIC := '1'; sload, sset, sclr, aload, aset, aclr, cin: IN STD_LOGIC := '0'; cout: OUT STD_LOGIC; --eq: OUT STD_LOGIC_VECTOR (15 DOWNTO 0); q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)); END COMPONENT; COMPONENT jtag_master is generic (N : Integer := 2); -- up to 5 possible port ( clk : in std_logic; reset_n : in std_logic; ce : in std_logic; -- SCSN bus_addr : in std_logic_vector( 7 downto 0); bus_we : in std_logic; -- write enable bus_din : in std_logic_vector(31 downto 0); bus_dout : out std_logic_vector(31 downto 0); -- user IO EN1 : out std_logic; EN2 : out std_logic; EN3 : out std_logic; EN4 : out std_logic; EN5 : out std_logic; busy : out std_logic; TCK : out std_logic; TMS : out std_logic; TDI : out std_logic; TDO : in std_logic ); end COMPONENT; signal wdata : std_logic_vector(31 downto 0); signal word_addr : std_logic_vector( 7 downto 0); signal rdata_jtag : std_logic_vector(31 downto 0); signal rdata_scsn : std_logic_vector(15 downto 0); signal data_conf_i : std_logic_vector(15 downto 0); signal WE : std_logic; signal CS_scsn : std_logic; signal cs_jtag : std_logic; signal WE_pre_enc : std_logic; signal soft_rst_n : std_logic; signal qclkd : std_logic_vector(15 downto 0); begin jtg: jtag_master port map( clk => clk_pci, reset_n => reset_n, ce => cs_jtag, -- SCSN bus_addr => word_addr, bus_we => WE, bus_din => wdata, bus_dout => rdata_jtag, -- user IO EN1 => open, EN2 => open, EN3 => open, EN4 => open, EN5 => open, busy => open, TCK => TCK, TMS => TMS, TDI => TDI, TDO => TDO ); cdiv: lpm_counter GENERIC map(LPM_WIDTH => qclkd'length, LPM_DIRECTION => "UP") PORT map( clock => clk_scsn, q => qclkd); dis_clk <= qclkd(qclkd'high); dec: decoder port map( clk_pci => clk_pci, reset_n => reset_n , data_in_pci => data_in , addr_in_pci => addr_in , LT_TSR_pci => LT_TSR , LT_CMD_pci => LT_CMD , LT_ACQ_n_pci => LT_ACQ_n, LT_RDY_n_pci => LT_RDY_n, data_out_pci => data_out, digital_in => digital_in, digital_oe => digital_oe, wdata => wdata , word_addr => word_addr , rdata_scsn => rdata_scsn , rdata_jtag => rdata_jtag , data_conf => data_conf_i, WE => WE , CS_scsn => CS_scsn , CS_jtag => CS_jtag , WE_pre_enc => WE_pre_enc , SCLK => SCLK, SDAT => SDAT, SSTR => SSTR, soft_rst_n => soft_rst_n ); data_conf <= data_conf_i; scsn: mcm_excalibur_simulator port map( -- external Network Interface d_in_0 => d_in_0 , d_out_0 => d_out_0 , d_in_1 => d_in_1 , d_out_1 => d_out_1 , --- clock and reset Signals reset_n => soft_rst_n, clk => clk_scsn, -- CPU interface address => word_addr(3 downto 0), CLK_CPU => clk_pci, CS => CS_scsn, WE => WE, data_in => wdata(15 downto 0), data_out => rdata_scsn, IRQ => IRQ ); pre: pre_enc PORT map( CLK => clk_scsn, RSTn => soft_rst_n, WR => clk_pci, WE => WE_pre_enc, FUNC => wdata(2 downto 0), PRE => PreTrigg ); end;