LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;


-- Pre-trigger encoder
-- last modified: 16:01 / 08 May 2003 / V.Angelov


ENTITY pre_dir IS
PORT(
     CLK   : IN  STD_LOGIC; -- fast clock 120MHz
     RSTn  : IN  STD_LOGIC; -- global reset (active low)
     start : IN  STD_LOGIC;
     PRE   : OUT STD_LOGIC  -- pre-trigger output
        );
END pre_dir;


architecture a of pre_dir is

signal sm       : std_logic;
signal WR       : std_logic;
signal fnew     : std_logic;
signal fold     : std_logic;
signal fdata    : std_logic_vector(3 downto 0);
signal fall1    : std_logic_vector(3 downto 0);
signal fall0    : std_logic_vector(3 downto 0);
signal cnt      : Integer range 0 to 3;
begin
        fall1 <= (others => '1');
        fall0 <= (others => '0');

        process(clk, RSTn)
        begin
            if RSTn = '0' then
                 fdata <= (others => '0');
                 fnew  <= '0';
                 fold  <= '0';
                 WR    <= '0';
            elsif clk'event and clk= '1'  then
                 fdata <= fdata(fdata'high-1 downto 0) & start;
                 if fdata=fall1 or fdata=fall0 then fnew <= fdata(0); end if;
                 fold <= fnew;
                 WR <= fnew and not fold;
            end if;

        end process;

        process(clk, RSTn)
        begin
                if RSTn='0' then
                        cnt <= 0;
                        sm  <= '0';
                elsif clk'event and clk='1' then

                        if WR='1'   then sm <= '1';
                        elsif cnt=0 then sm <= '0'; end if;

                        if WR='1' then cnt <= 2;
                        elsif cnt>0 then cnt <= cnt - 1; end if;

                end if;
        end process;

        PRE <= sm;
end;