LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; entity decoder is port( clk_pci : in std_logic; reset_n : in std_logic; data_in_pci : in std_logic_vector(31 downto 0); addr_in_pci : in std_logic_vector(31 downto 0); LT_TSR_pci : in std_logic_vector(11 downto 0); LT_CMD_pci : in std_logic_vector( 3 downto 0); LT_ACQ_n_pci : in std_logic; -- L_Ldat_acq_n_pci : in std_logic; LT_RDY_n_pci : out std_logic; data_out_pci : out std_logic_vector(31 downto 0); wdata : out std_logic_vector(31 downto 0); word_addr : out std_logic_vector( 7 downto 0); rdata_scsn : in std_logic_vector(15 downto 0); rdata_jtag : in std_logic_vector(31 downto 0); data_conf : out std_logic_vector(15 downto 0); digital_in : in std_logic_vector(15 downto 0); digital_oe : out std_logic_vector(15 downto 0); WE : out std_logic; CS_scsn : out std_logic; CS_jtag : out std_logic; WE_pre_enc : out std_logic; SCLK : OUT STD_LOGIC; -- Serial Clock SDAT : OUT STD_LOGIC; -- Serial Data SSTR : OUT STD_LOGIC; -- Serial Strobe soft_rst_n : out std_logic ); end decoder; -------------------------------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------------------------------- architecture a of decoder is component tsr_translate is port( lt_tsr : in STD_LOGIC_VECTOR(11 downto 0); bar_hit : out STD_LOGIC_VECTOR(5 downto 0); exp_rom_hit : out STD_LOGIC; trans64 : out STD_LOGIC; targ_access : out STD_LOGIC; burst_trans : out STD_LOGIC; pxfr : out STD_LOGIC; dac : out STD_LOGIC ); end component; --component par2ser_pci is --GENERIC ( WIDTH : Integer := 19 -- Width of the 'Byte' -- ); --PORT ( -- CE : IN STD_LOGIC; -- Chip enable -- A0 : IN STD_LOGIC; -- bit 0 of the address -- WE : IN STD_LOGIC; -- Write enable -- D : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0); -- Data input bus -- CLK : IN STD_LOGIC; -- Clock -- RESET_n : IN STD_LOGIC; -- reset -- PQ : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0); -- Parallel outputs -- SCLK : OUT STD_LOGIC; -- Serial Clock -- SDAT : OUT STD_LOGIC; -- Serial Data -- SSTR : OUT STD_LOGIC);-- Serial Strobe --end component; CONSTANT INTERRUPT_ACC : STD_LOGIC_VECTOR(3 downto 0):="0000"; CONSTANT SPECIAL_CYCLE : STD_LOGIC_VECTOR(3 downto 0):="0001"; CONSTANT IO_READ : STD_LOGIC_VECTOR(3 downto 0):="0010"; CONSTANT IO_WRITE : STD_LOGIC_VECTOR(3 downto 0):="0011"; CONSTANT RESERVED_1 : STD_LOGIC_VECTOR(3 downto 0):="0100"; CONSTANT RESERVED_2 : STD_LOGIC_VECTOR(3 downto 0):="0101"; CONSTANT MEM_READ : STD_LOGIC_VECTOR(3 downto 0):="0110"; CONSTANT MEM_WRITE : STD_LOGIC_VECTOR(3 downto 0):="0111"; CONSTANT RESERVED_3 : STD_LOGIC_VECTOR(3 downto 0):="1000"; CONSTANT RESERVED_4 : STD_LOGIC_VECTOR(3 downto 0):="1001"; CONSTANT CONF_READ : STD_LOGIC_VECTOR(3 downto 0):="1010"; CONSTANT CONF_WRITE : STD_LOGIC_VECTOR(3 downto 0):="1011"; CONSTANT MEM_READ_MULT : STD_LOGIC_VECTOR(3 downto 0):="1100"; CONSTANT DAC : STD_LOGIC_VECTOR(3 downto 0):="1101"; CONSTANT MEM_READ_LINE : STD_LOGIC_VECTOR(3 downto 0):="1110"; CONSTANT MEM_WRITE_INV : STD_LOGIC_VECTOR(3 downto 0):="1111"; signal READorWRITE : std_logic; signal READ : std_logic; signal WRITE : std_logic; signal RST_dec : std_logic; signal bar_hit : std_logic_vector( 5 downto 0); signal rdata_conf : std_logic_vector(data_conf'range); signal digital_oe_i : std_logic_vector(digital_oe'range); signal WE_conf : std_logic; signal CS_scsn_i : std_logic; --signal CS_jtag_i : std_logic; signal CS_par2s : std_logic; signal tmp : std_logic; signal WE_pre : std_logic; signal wdata_i : std_logic_vector(wdata'range); signal Q_par2s : std_logic_vector(18+8 downto 0); signal data_out_32pci : std_logic_vector(31 downto 0); begin -- decode the PCI commands with LT_CMD_pci select READ <= '1' when IO_READ | MEM_READ | MEM_READ_MULT | MEM_READ_LINE, '0' when others; with LT_CMD_pci select WRITE <= '1' when IO_WRITE | MEM_WRITE | MEM_WRITE_INV, '0' when others; READorWRITE <= READ or WRITE; -- outputs to scsn master WE <= WRITE; wdata_i <= data_in_pci(wdata'range); wdata <= wdata_i; word_addr <= addr_in_pci(9 downto 2); -- read mux process(addr_in_pci, rdata_scsn, rdata_conf, digital_oe_i, rdata_jtag, digital_in) begin data_out_32pci <= (others => '0'); case addr_in_pci(10 downto 7) is when "0000" => data_out_32pci(rdata_scsn'range) <= rdata_scsn; when "0100" => data_out_32pci(digital_oe_i'range) <= digital_oe_i; data_out_32pci(31 downto 16 ) <= digital_in; when "0001" => data_out_32pci(rdata_conf'range) <= rdata_conf; data_out_32pci(31 downto 16 ) <= digital_in; when "1000" | "1001" | "1010" | "1011" | "1100" | "1101" | "1110" | "1111" => data_out_32pci(rdata_jtag'range) <= rdata_jtag; when others => data_out_32pci <= (others => '-'); end case; end process; data_out_pci <= data_out_32pci; -- PASA interface --p2s: par2ser_pci -- GENERIC map( WIDTH => Q_par2s'length) -- PORT map( -- CE => CS_par2s, -- A0 => addr_in_pci(2), -- WE => WRITE, -- D => data_in_pci(Q_par2s'range), -- CLK => clk_pci, -- RESET_n => RESET_n, -- PQ => Q_par2s, -- SCLK => SCLK, -- SDAT => SDAT, -- SSTR => SSTR -- ); tsr: tsr_translate port map( lt_tsr => LT_TSR_pci, bar_hit => bar_hit, exp_rom_hit => open, trans64 => open, targ_access => open, burst_trans => open, pxfr => open, dac => open ); -- address decoder for internal devices CS_jtag <= '1' when addr_in_pci(10) ='1' and LT_ACQ_n_pci='0' and bar_hit(0)='1' and READorWRITE='1' else '0'; CS_scsn_i <= '1' when addr_in_pci(10 downto 6)="00000" and LT_ACQ_n_pci='0' and bar_hit(0)='1' and READorWRITE='1' else '0'; CS_scsn <= CS_scsn_i; CS_par2s <= '1' when addr_in_pci(10 downto 6)="01000" and LT_ACQ_n_pci='0' and bar_hit(0)='1' and READorWRITE='1' else '0'; RST_dec <= '1' when addr_in_pci(10 downto 6)="00100" and LT_ACQ_n_pci='0' and bar_hit(0)='1' and WRITE='1' else '0'; WE_pre <= '1' when addr_in_pci(10 downto 6)="00001" and LT_ACQ_n_pci='0' and bar_hit(0)='1' and WRITE='1' else '0'; WE_pre_enc <= WE_pre; WE_conf <= '1' when addr_in_pci(10 downto 6)="00010" and LT_ACQ_n_pci='0' and bar_hit(0)='1' and WRITE='1' else '0'; -- synchronize soft reset output to avoid glitches process(clk_pci, reset_n) begin if reset_n = '0' then soft_rst_n <= '0'; elsif clk_pci'event and clk_pci='1' then soft_rst_n <= not RST_dec; end if; end process; -- configuration register and ready output process(clk_pci, reset_n) begin if reset_n = '0' then rdata_conf <= (others => '0'); digital_oe_i <= (others => '0'); LT_RDY_n_pci <= '1'; tmp <= '1'; elsif clk_pci'event and clk_pci='1' then if WE_conf='1' then rdata_conf <= wdata_i(rdata_conf'range); end if; if CS_par2s='1' and write='1' then digital_oe_i <= wdata_i(digital_oe_i'range); end if; tmp <= not Bar_hit(0); LT_RDY_n_pci <= tmp; end if; end process; digital_oe <= digital_oe_i; data_conf <= rdata_conf; end;