[Library] others = $MODEL_TECH/../modelsim.ini func = func [vcom] ; Turn on VHDL-1993 as the default. Default is off (VHDL-1987). VHDL93 = 1 ; Show source line containing error. Default is off. ; Show_source = 1 ; Turn off unbound-component warnings. Default is on. ; Show_Warning1 = 0 ; Turn off process-without-a-wait-statement warnings. Default is on. ; Show_Warning2 = 0 ; Turn off null-range warnings. Default is on. ; Show_Warning3 = 0 ; Turn off no-space-in-time-literal warnings. Default is on. ; Show_Warning4 = 0 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. ; Show_Warning5 = 0 ; Turn off optimization for IEEE std_logic_1164 package. Default is on. ; Optimize_1164 = 0 ; Turn on resolving of ambiguous function overloading in favor of the ; "explicit" function declaration (not the one automatically created by ; the compiler for each type declaration). Default is off. ; The .ini file has Explict enabled so that std_logic_signed/unsigned ; will match the behavior of synthesis tools. Explicit = 1 ; Turn off VITAL compliance checking. Default is checking on. ; NoVitalCheck = 1 ; Ignore VITAL compliance checking errors. Default is to not ignore. ; IgnoreVitalErrors = 1 ; Turn off VITAL compliance checking warnings. Default is to show warnings. ; Show_VitalChecksWarnings = false ; Keep silent about case statement static warnings. ; Default is to give a warning. ; NoCaseStaticError = 1 ; Keep silent about warnings caused by aggregates that are not locally static. ; Default is to give a warning. ; NoOthersStaticError = 1 ; Treat as errors: ; case statement static warnings ; warnings caused by aggregates that are not locally static ; Overrides NoCaseStaticError, NoOthersStaticError settings. ; PedanticErrors = 1 ; Turn off acceleration of the VITAL packages. Default is to accelerate. ; NoVital = 1 ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on some limited synthesis rule compliance checking. Checks only: ; -- signals used (read) by a process must be in the sensitivity list ; CheckSynthesis = 1 ; Activate optimizations on expressions that don't involve signals, ; waits, or function/procedure/task invocations. Default is off. ; ScalarOpts = 1 ; Require the user to specify a configuration for all bindings, ; and do not generate a compile time default binding for the ; component. This will result in an elaboration error of ; 'component not bound' if the user fails to do so. Avoids the rare ; issue of a false dependency upon the unused default binding. ; RequireConfigForAllDefaultBinding = 1 ; Inhibit range checking on subscripts of arrays. Range checking on ; scalars defined with subtypes is inhibited by default. ; NoIndexCheck = 1 ; Inhibit range checks on all (implicit and explicit) assignments to ; scalar objects defined with subtypes. ; NoRangeCheck = 1 [vlog] ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on Verilog hazard checking (order-dependent accessing of global vars). ; Default is off. ; Hazard = 1 ; Turn on converting regular Verilog identifiers to uppercase. Allows case ; insensitivity for module names. Default is no conversion. ; UpCase = 1 ; Turn on incremental compilation of modules. Default is off. ; Incremental = 1 ; Turns on lint-style checking. ; Show_Lint = 1 [vsim] ; Simulator resolution ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. Resolution = ns ; User time unit for run commands ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the ; unit specified for Resolution. For example, if Resolution is 100ps, ; then UserTimeUnit defaults to ps. UserTimeUnit = default ; Default run length RunLength = 100 ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 ; Directive to license manager: ; vhdl Immediately reserve a VHDL license ; vlog Immediately reserve a Verilog license ; plus Immediately reserve a VHDL and Verilog license ; nomgc Do not look for Mentor Graphics Licenses ; nomti Do not look for Model Technology Licenses ; noqueue Do not wait in the license queue when a license isn't available ; viewsim Try for viewer license but accept simulator license(s) instead ; of queuing for viewer license ; License = plus ; Stop the simulator after an assertion message ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal BreakOnAssertion = 3 ; Assertion Message Format ; %S - Severity Level ; %R - Report Message ; %T - Time of assertion ; %D - Delta ; %I - Instance or Region pathname (if available) ; %% - print '%' character ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" ; Assertion File - alternate file for storing assertion messages ; AssertFile = assert.log ; Default radix for all windows and commands... ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned DefaultRadix = symbolic ; VSIM Startup command ; Startup = do startup.do ; File for saving command transcript TranscriptFile = transcript ; File for saving command history ; CommandHistory = cmdhist.log ; Specify whether paths in simulator commands should be described ; in VHDL or Verilog format. For VHDL, PathSeparator = / ; for Verilog, PathSeparator = . PathSeparator = / ; Specify the dataset separator for fully rooted contexts. ; The default is ':'. For example, sim:/top ; Must not be the same character as PathSeparator. DatasetSeparator = : ; Disable assertion messages ; IgnoreNote = 1 ; IgnoreWarning = 1 ; IgnoreError = 1 ; IgnoreFailure = 1 ; Default force kind. May be freeze, drive, or deposit ; or in other terms, fixed, wired, or charged. ; DefaultForceKind = freeze ; If zero, open files when elaborated; otherwise, open files on ; first read or write. Default is 0. ; DelayFileOpen = 1 ; Control VHDL files opened for write ; 0 = Buffered, 1 = Unbuffered UnbufferedOutput = 0 ; Control number of VHDL files open concurrently ; This number should always be less than the ; current ulimit setting for max file descriptors. ; 0 = unlimited ConcurrentFileLimit = 40 ; Controls the number of hierarchical regions displayed as ; part of a signal name shown in the waveform window. The default ; value or a value of zero tells VSIM to display the full name. ; WaveSignalNameWidth = 0 ; Turn off warnings from the std_logic_arith, std_logic_unsigned ; and std_logic_signed packages. ; StdArithNoWarnings = 1 ; Turn off warnings from the IEEE numeric_std and numeric_bit packages. ; NumericStdNoWarnings = 1 ; Control the format of a generate statement label. Don't quote it. ; GenerateFormat = %s__%d ; Specify whether checkpoint files should be compressed. ; The default is to be compressed. ; CheckpointCompressMode = 0 ; List of dynamically loaded objects for Verilog PLI applications ; Veriuser = veriuser.sl ; Specify default options for the restart command. Options can be one ; or more of: -force -nobreakpoint -nolist -nolog -nowave ; DefaultRestartOptions = -force ; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs ; (> 500 megabyte memory footprint). Default is disabled. ; Specify number of megabytes to lock. ; LockedMemory = 1000 ; Turn on (1) or off (0) WLF file compression. ; The default is 1; compress WLF file. ; WLFCompress = 0 ; Specify whether to save all design hierarchy (1) in WLF file ; or only regions containing logged signals (0). ; The default is 0; log only regions with logged signals. ; WLFSaveAllRegions = 1 ; WLF file time limit. Limit WLF file by time, as closely as possible, ; to the specified amount of simulation time. When the limit is exceeded ; the earliest times get truncated from the file. ; If both time and size limits are specified the most restrictive is used. ; UserTimeUnits are used if time units are not specified. ; The default is 0; no limit. Example: WLFTimeLimit = {100 ms} ; WLFTimeLimit = 0 ; WLF file size limit. Limit WLF file size, as closely as possible, ; to the specified number of megabytes. If both time and size limits ; are specified then the most restrictive is used. ; The default is 0; no limit. ; WLFSizeLimit = 1000 ; Specify whether or not a WLF file should be deleted when the ; simulation ends. A value of 1 will cause the WLF file to be deleted. ; The default is 0; don't delete WLF file when simulation ends. ; WLFDeleteOnQuit = 1 [lmc] ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software libsm = $MODEL_TECH/libsm.sl ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) ; libsm = $MODEL_TECH/libsm.dll ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so ; Logic Modeling's SmartModel SWIFT software (Windows NT) ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll ; Logic Modeling's SmartModel SWIFT software (Linux) ; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so ; ModelSim's interface to Logic Modeling's hardware modeler SFI software libhm = $MODEL_TECH/libhm.sl ; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT) ; libhm = $MODEL_TECH/libhm.dll ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) ; libsfi = /lib/hp700/libsfi.sl ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) ; libsfi = /lib/rs6000/libsfi.a ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) ; libsfi = /lib/sun4.solaris/libsfi.so ; Logic Modeling's hardware modeler SFI software (Windows NT) ; libsfi = /lib/pcnt/lm_sfi.dll ; Logic Modeling's hardware modeler SFI software (Linux) ; libsfi = /lib/linux/libsfi.so