library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.std_logic_unsigned.all;

entity top_tb is
end top_tb;

architecture a of top_tb is

component mcm_excalibur_simulator is
 port(
        -- external Network Interface
        d_in_0  : in std_logic ;
        d_out_0 : out std_logic ;
        d_in_1  : in std_logic ;
        d_out_1 : out std_logic ;

        --- clock and reset Signals
        reset_n : in  std_logic;
        clk     : in  std_logic;

        address         : in  std_logic_vector(3 downto 0);
        CLK_CPU, CS, WE : in  std_logic;
        data_in         : in  std_logic_vector(15 downto 0);
        data_out        : out std_logic_vector(15 downto 0);
        IRQ             : out std_logic
     );
end component;

component mcm_network_interface is
 port(
        -- external Network Interface
        ser0_din        : in  std_logic ; --ring 0 data in
        ser0_dout       : out std_logic ; --ring 0 data out
        ser1_din        : in  std_logic ; --ring 1 data in
        ser1_dout       : out std_logic ; --ring 1 data out

        -- Bus interface
        bus_addr : out std_logic_vector(15 downto 0); -- address to read/write
        bus_dout : out std_logic_vector(31 downto 0); -- data out
        bus_din  : in  std_logic_vector(31 downto 0); -- data in
        bus_req  : out std_logic; -- bus request
        bus_we   : out std_logic; -- write enable

        bus_ack : in std_logic;

        chipRST_n: out std_logic;

        --- clock and reset Signals
        reset_n : in  std_logic;
        clk     : in  std_logic
     );
end component;

signal clk              : std_logic := '1';
signal reset_n          : std_logic := '1';
signal IRQ              : std_logic;

signal d_in_0           : std_logic;
signal d_out_0          : std_logic;
signal d_in_1           : std_logic;
signal d_out_1          : std_logic;


signal address          : std_logic_vector(3 downto 0);
signal CLK_CPU          : std_logic := '1';
signal CS, WE           : std_logic;
signal data_in          : std_logic_vector(15 downto 0);
signal data_out         : std_logic_vector(15 downto 0);

signal bus_addr         : std_logic_vector(15 downto 0); -- address to read/write
signal bus_dout         : std_logic_vector(31 downto 0); -- data out
signal bus_din          : std_logic_vector(31 downto 0); -- data in
signal bus_req          : std_logic; -- bus request
signal bus_we           : std_logic; -- write enable

signal bus_ack          : std_logic;

signal chipRST_n        : std_logic;

signal counter          : Integer range 0 to 4095;
constant counter_max    : Integer := 2000;
signal start            : std_logic;

begin
     clk     <= not clk     after  5 ns;
     clk_cpu <= not clk_cpu after 20 ns;

     reset_n <= '0' after  1 ns,
                '1' after 55 ns;

mast: mcm_excalibur_simulator
      port map(
        -- external Network Interface
        d_in_0           =>  d_in_0,
        d_out_0          =>  d_out_0,
        d_in_1           =>  d_in_1,
        d_out_1          =>  d_out_1,

        --- clock and reset Signals
        reset_n          =>  reset_n,
        clk              =>  clk,

        address          =>  address,
        CLK_CPU          =>  CLK_CPU,
        CS               =>  CS,
        WE               =>  WE,
        data_in          =>  data_in,
        data_out         =>  data_out,
        IRQ              =>  IRQ
     );

slav: mcm_network_interface
      port map(
        -- external Network Interface
        ser0_din         =>  d_out_0,
        ser0_dout        =>  d_in_0,
        ser1_din         =>  '0',
        ser1_dout        =>  open,

        -- Bus interface
        bus_addr         =>  bus_addr,
        bus_dout         =>  bus_dout,
        bus_din          =>  bus_din,
        bus_req          =>  bus_req,
        bus_we           =>  bus_we,

        bus_ack          =>  bus_ack,

        chipRST_n        =>  chipRST_n,

        --- clock and reset Signals
        reset_n          =>  reset_n,
        clk              =>  clk
     );

     process(clk, reset_n) -- slave environment
        begin
                if reset_n='0' then bus_din <= (others => '1');
                                    bus_ack <= '0';
                elsif clk'event and clk='1' then
                        bus_ack <= bus_req;
                        if bus_we='1' then bus_din <= bus_dout; end if; -- simple register
                end if;
        end process;

     process(clk_cpu, reset_n)
        begin
                if reset_n='0' then counter <= 10; start <= '0';
                elsif clk_cpu'event and clk_cpu='1' then
                        start <= '0';
                        if counter>0 then counter <= counter - 1;
                                     else
                                          counter <= counter_max;
                                          start <= '1';
                                     end if;
                end if;
        end process;

      process
        begin
          CS <= '0';
          WE <= '0';
          wait until start'event and start='1';
          CS <= '1';
          WE <= '1';
          address <= "0000";
          data_in <= (others => '1');
          wait until clk_cpu'event and clk_cpu='1';
          address <= "0001";
          data_in <= (others => '0');
          wait until clk_cpu'event and clk_cpu='1';
          address <= "0010";
          data_in <= (others => '0'); -- address
          wait until clk_cpu'event and clk_cpu='1';
          address <= "0011";
          data_in <= (others => '0');
          data_in(3 downto 0) <= "1001"; -- read
          wait until clk_cpu'event and clk_cpu='1';
          address <= "0100";
          data_in <= (others => '0');
          data_in(0) <= '1'; -- MCM 1
          wait until clk_cpu'event and clk_cpu='1';
          -- waiting
          address <= "0111";
          CS <= '1';
          WE <= '0';
          wait until data_out(0)='1';
          address <= "0000";
          wait until clk_cpu'event and clk_cpu='1';
          address <= "0001";
          wait until clk_cpu'event and clk_cpu='1';

          address <= "0111"; -- read status
          wait until clk_cpu'event and clk_cpu='1';
          WE <= '0'; -- was 1
          wait until clk_cpu'event and clk_cpu='1';
          WE <= '0';

          -- next frame
          wait until start'event and start='1';
          WE <= '1';
          address <= "0011";
          data_in <= (others => '0');
          data_in(3 downto 0) <= "1010"; -- write
          wait until clk_cpu'event and clk_cpu='1';
          address <= "0100";
          data_in <= (others => '0');
          data_in(0) <= '1'; -- MCM 1
          wait until clk_cpu'event and clk_cpu='1';
          address <= "0111";
          CS <= '1';
          WE <= '0'; -- read
          wait until start'event and start='1';
          wait until clk_cpu'event and clk_cpu='1';
          WE <= '1'; -- write
          wait until clk_cpu'event and clk_cpu='1';
          WE <= '0';
          wait;
        end process;

end;