library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity topSCSN is
generic(
    device_id  : Integer := 1;
    version_id : Integer := 1);
    Port (
       reset_n   : IN  std_logic;
       clk       : IN  std_logic;

       ser0_din  : IN  std_logic;
       ser1_din  : IN  std_logic;
       ser0_dout : OUT std_logic;
       ser1_dout : OUT std_logic;

       creg0d    : OUT std_logic_vector(31 downto 0);
       creg1d    : OUT std_logic_vector(31 downto 0);

       chipRST_n : OUT std_logic
                 );
end topSCSN;

architecture Behavioral of topSCSN is

COMPONENT mcm_network_interface
PORT(
        -- external Network Interface
        ser0_din  : in  std_logic ; --ring 0 data in
        ser0_dout : out std_logic ; --ring 0 data out
        ser1_din  : in  std_logic ; --ring 1 data in
        ser1_dout : out std_logic ; --ring 1 data out

        -- Bus interface
        bus_addr  : out std_logic_vector(15 downto 0); -- address to read/write
        bus_dout  : out std_logic_vector(31 downto 0); -- data out
        bus_din   : in  std_logic_vector(31 downto 0); -- data in
        bus_req   : out std_logic; -- bus request
        bus_we    : out std_logic; -- write enable

        bus_ack   : in std_logic;

        chipRST_n : out std_logic;

        --- clock and reset Signals
        reset_n   : in  std_logic;
        clk_buf_disable : out std_logic;
        clk_buf   : in  std_logic;
        clk       : in  std_logic
        );
END COMPONENT;

COMPONENT general_config is
generic(
    device_id  : Integer := 1;
    version_id : Integer := 1);
    port (
        clk             : in  std_logic;
        reset_n         : in  std_logic;
      -- enable
        bus_req         : in  std_logic;
        bus_ack         : out std_logic;

      -- internal bus
        bus_addr        : in  std_logic_vector(15 downto 0);
        bus_we          : in  std_logic;            -- write enable
        bus_din         : in  std_logic_vector(31 downto 0);
        bus_dout        : out std_logic_vector(31 downto 0);

      -- config registers
        creg0d          : out std_logic_vector(31 downto 0);
        creg1d          : out std_logic_vector(31 downto 0)
        );
end COMPONENT;

signal  wdata       : std_logic_vector(31 downto 0);
signal  rdata       : std_logic_vector(31 downto 0);
signal  bus_we      : std_logic;
signal  bus_req     : std_logic;
signal  bus_ack     : std_logic;
signal  bus_addr    :  std_logic_vector(15 downto 0); -- address to read/write

signal  chipRST_n_i :  std_logic;
signal  rst_n       :  std_logic;

signal  creg0d_i    :  std_logic_vector(31 downto 0);
signal  creg1d_i    :  std_logic_vector(31 downto 0);

begin

scsnslv: mcm_network_interface
        PORT MAP(
        ser0_din        => ser0_din,
        ser0_dout       => ser0_dout,
        ser1_din        => ser1_din,
        ser1_dout       => ser1_dout,

        bus_addr        => bus_addr,
        bus_dout        => wdata,
        bus_din         => rdata,
        bus_req         => bus_req,
        bus_we          => bus_we,
        bus_ack         => bus_ack,

        chipRST_n       => chipRST_n_i,
        reset_n         => reset_n,
        clk_buf_disable => open,
        clk_buf         => clk,
        clk             => clk
        );

    rst_n <= reset_n and chipRST_n_i;

conf: general_config
    generic map(
    device_id  => device_id,
    version_id => version_id)
    port map(
        clk             => clk,
        reset_n         => rst_n,
      -- enable
        bus_req         => bus_req,
        bus_ack         => bus_ack,

      -- internal bus
        bus_addr        => bus_addr,
        bus_we          => bus_we,
        bus_din         => wdata,
        bus_dout        => rdata,

      -- config registers
        creg0d          => creg0d_i,
        creg1d          => creg1d_i
        );

    creg0d <= creg0d_i;
    creg1d <= creg1d_i;
    chipRST_n <= chipRST_n_i;

end Behavioral;