LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity general_config is
generic(
    device_id  : Integer := 1;
    version_id : Integer := 1);
    port (
        clk             : in  std_logic;
        reset_n         : in  std_logic;
      -- enable
        bus_req         : in  std_logic;
        bus_ack         : out std_logic;

      -- internal bus
        bus_addr        : in  std_logic_vector(15 downto 0);
        bus_we          : in  std_logic;            -- write enable
        bus_din         : in  std_logic_vector(31 downto 0);
        bus_dout        : out std_logic_vector(31 downto 0);

      -- config registers
        creg0d          : out std_logic_vector(31 downto 0);
        creg1d          : out std_logic_vector(31 downto 0)
        );
end general_config;

architecture a of general_config is

signal  dev_id          : std_logic_vector(31 downto 0);
signal  version         : std_logic_vector(31 downto 0);

signal  creg0d_i        : std_logic_vector(31 downto 0);
signal  creg1d_i        : std_logic_vector(31 downto 0);

signal  cnt             : std_logic_vector( 7 downto 0);

constant creg0d_reset   : std_logic_vector(31 downto 0) := (others => '0');
constant creg1d_reset   : std_logic_vector(31 downto 0) := (others => '1');

begin
    version <= conv_std_logic_vector(version_id, version'length);
    dev_id  <= conv_std_logic_vector(device_id,  dev_id'length);

    process(clk, reset_n)
    begin
        if reset_n='0' then
          creg0d_i <= creg0d_reset;
          creg1d_i <= creg1d_reset;
          bus_ack  <= '0';
          cnt <= (others => '0');
        elsif clk'event and clk='1' then
          bus_ack <= bus_req;
          cnt <= cnt + 1;
          if bus_we='1' and bus_req='1' then
            case bus_addr(1 downto 0) is
            when "00" => creg0d_i <= bus_din(creg0d_i'range);
            when "01" => creg1d_i <= bus_din(creg1d_i'range);
            when others => NULL;
            end case;
          end if;
        end if;
    end process;

    creg0d <= creg0d_i;
    creg1d <= creg1d_i;

    process(creg0d_i, creg1d_i, bus_addr, version, dev_id, cnt)
    begin
        bus_dout <= (others => '0');
        case bus_addr(2 downto 0) is
        when "000"     =>  bus_dout(creg0d_i'range) <= creg0d_i;
        when "001"     =>  bus_dout(creg1d_i'range) <= creg1d_i;
        when "010"     =>  bus_dout(version'range)  <= version;
        when "011"     =>  bus_dout(dev_id'range)   <= dev_id;
        when "100"     => bus_dout(cnt'range) <= cnt;
        when others   =>  bus_dout                 <= (others => '-');
        end case;
    end process;

end;