LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY fpga;
use std.textio.all;

--USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_unsigned.all;
--USE ieee.numeric_std.ALL;

ENTITY topSCSN_tb_vhd IS
generic (Tperiod : time := 8 ns);
END topSCSN_tb_vhd;

ARCHITECTURE behavior OF topSCSN_tb_vhd IS

        -- Component Declaration for the Unit Under Test (UUT)
COMPONENT topSCSN
PORT(
        reset_n   : IN  std_logic;
        clk       : IN  std_logic;

        ser0_din  : IN  std_logic;
        ser1_din  : IN  std_logic;
        ser0_dout : OUT std_logic;
        ser1_dout : OUT std_logic;

        creg0d    : OUT std_logic_vector(31 downto 0);
        creg1d    : OUT std_logic_vector(31 downto 0);

        chipRST_n : OUT std_logic
        );
END COMPONENT;

COMPONENT ser_int
  generic (
    wait_delay :     integer := 100;
    init_delay :     integer := 4095;
    file_in    :     string  := "./DATA/sc_send.dat";
    file_out   :     string  := "./DATA/sc_recv.dat" );
 PORT(
         reset_n  : IN  std_logic;
         clk      : IN  std_logic;
         ready    : IN  std_logic;
         ser0din  : IN  std_logic;
         ser0dout : OUT std_logic
         );
 END COMPONENT;

--Inputs
SIGNAL reset_n   :  std_logic;
SIGNAL clk       :  std_logic := '1';
SIGNAL ready     :  std_logic := '0';
SIGNAL ser0_din  :  std_logic;
SIGNAL ser0_dout :  std_logic;
SIGNAL ser1_din  :  std_logic;
SIGNAL ser1_dout :  std_logic;

--Outputs
SIGNAL chipRST_n :  std_logic;
SIGNAL creg0d    :  std_logic_vector(31 downto 0);
SIGNAL creg1d    :  std_logic_vector(31 downto 0);

BEGIN

        ser1_dout <= '0';

scsnmast: ser_int
        PORT MAP(
        reset_n  => reset_n,
        clk      => clk,
        ready    => ready,
        ser0din  => ser0_din,
        ser0dout => ser0_dout
);

        -- Instantiate the Unit Under Test (UUT)
uut: topSCSN PORT MAP(
        reset_n   => reset_n,
        clk       => clk,

        ser0_din  => ser0_dout,
        ser0_dout => ser0_din,
        ser1_din  => ser1_dout,
        ser1_dout => ser1_din,

        creg0d    => creg0d,
        creg1d    => creg1d,

        chipRST_n => chipRST_n

        );

        clk <= NOT clk after Tperiod/2;
        reset_n <= '0' after 0 us,
                   '1' after 2 us,
                   '0' after 3 us,
                   '1' after 4 us;

END;