Project Information e:\tiserv\trigger\maxplus\top_pre.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 04/06/2005 13:51:44 Copyright (C) 1988-2002 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful ** DEVICE SUMMARY ** Chip/ Input Output Bidir Memory Memory LCs POF Device Pins Pins Pins Bits % Utilized LCs % Utilized top_pre EP1K100QC208-2 8 15 0 0 0 % 102 2 % User Pins: 8 15 0 Project Information e:\tiserv\trigger\maxplus\top_pre.rpt ** PROJECT COMPILATION MESSAGES ** Info: Reserved unused input pin 'LVDS_in3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'LVDS_in2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'LVDS_in0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Warning: Node 'LED_GRN' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem ** PROJECT TIMING MESSAGES ** Warning: Found ripple clock -- warning messages and Report File information on tco, tsu, and fmax may be inaccurate Project Information e:\tiserv\trigger\maxplus\top_pre.rpt ** PIN/LOCATION/CHIP ASSIGNMENTS ** Actual User Assignments Assignments (if different) Node Name top_pre@27 ADC_OEn top_pre@182 CLK top_pre@184 inp_sw top_pre@195 --------- LED_GRN top_pre@193 LED_RED top_pre@206 LVDS_EN top_pre@8 LVDS_in0 top_pre@7 LVDS_in1 top_pre@9 LVDS_in2 top_pre@10 LVDS_in3 top_pre@183 mode_sw top_pre@39 pre_in top_pre@25 pre_out top_pre@208 pre_out_lvds top_pre@192 R7S1 top_pre@180 R7S2 top_pre@186 R7S3 top_pre@187 R7S4 top_pre@189 R7S5 top_pre@191 R7S6 top_pre@190 R7S7 top_pre@125 SRAM_CEn top_pre@131 SRAM_OEn top_pre@37 tst_out Project Information e:\tiserv\trigger\maxplus\top_pre.rpt ** FILE HIERARCHY ** |21mux:ix459| |21mux:ix461| |21mux:ix463| |21mux:ix465| |21mux:ix467| |21mux:ix469| |21mux:ix471| |21mux:ix473| |21mux:ix475| |21mux:ix477| |lpm_counter:div_clk_ix7| |lpm_counter:div_clk_ix7|lpm_constant:scdw| |carry_sum:counter_add_29_ix31_carry_sum| |carry_sum:counter_add_29_ix35_carry_sum| |carry_sum:counter_add_29_ix39_carry_sum| |carry_sum:counter_add_29_ix43_carry_sum| |carry_sum:counter_add_29_ix47_carry_sum| |carry_sum:counter_add_29_ix51_carry_sum| |carry_sum:counter_add_29_ix55_carry_sum| |carry_sum:counter_add_29_ix59_carry_sum| |carry_sum:counter_add_29_ix29_carry_sum| Device-Specific Information: e:\tiserv\trigger\maxplus\top_pre.rpt top_pre ***** Logic for device 'top_pre' compiled without errors. Device: EP1K100QC208-2 ACEX 1K Configuration Scheme: Passive Serial Device Options: User-Supplied Start-Up Clock = OFF Auto-Restart Configuration on Frame Error = OFF Release Clears Before Tri-States = OFF Enable Chip_Wide Reset = OFF Enable Chip-Wide Output Enable = OFF Enable INIT_DONE Output = OFF JTAG User Code = 7f MultiVolt I/O = OFF Enable Lock Output = OFF p r e _ o R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R u E L E E E E E E E E E E L m E E E E E E E E E E E E E E E E E E E E t S V S S S S V S S S S S S E V i o S S S S S S S S S S S S S S S S S S S S _ E D E E E E C E E E E E E V D C n d E V E E E E E E E E E E E V E E E E E E E E l R S R R R R C R R R R R R C _ R R R R R R C p e R R C R R R R R R R R R R R C R R R R R R R R v V _ V V V V I V V V V V V C R 7 7 7 7 G 7 7 I _ _ C G 7 V C V V V V V V G V V V V V C V V V V V V V V d E E E E E E N E E E E E E I E S S S S N S S N s s L N S E I E E E E E E N E E E E E I E E E E E E E E s D N D D D D T D D D D D D O D 1 6 7 5 D 4 3 T w w K D 2 D O D D D D D D D D D D D D O D D D D D D D D ----------------------------------------------------------------------------------------------------------_ / 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_ / 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 | #TCK | 1 156 | ^DATA0 ^CONF_DONE | 2 155 | ^DCLK ^nCEO | 3 154 | ^nCE #TDO | 4 153 | #TDI VCCIO | 5 152 | VCCINT GND | 6 151 | GND LVDS_in1 | 7 150 | RESERVED LVDS_in0 | 8 149 | RESERVED LVDS_in2 | 9 148 | RESERVED LVDS_in3 | 10 147 | RESERVED RESERVED | 11 146 | VCCIO RESERVED | 12 145 | GND RESERVED | 13 144 | RESERVED RESERVED | 14 143 | RESERVED RESERVED | 15 142 | RESERVED RESERVED | 16 141 | RESERVED RESERVED | 17 140 | RESERVED RESERVED | 18 139 | RESERVED RESERVED | 19 138 | VCCIO GND | 20 137 | GND VCCINT | 21 136 | RESERVED VCCIO | 22 135 | RESERVED GND | 23 134 | RESERVED RESERVED | 24 133 | RESERVED pre_out | 25 132 | RESERVED RESERVED | 26 131 | SRAM_OEn ADC_OEn | 27 EP1K100QC208-2 130 | VCCINT RESERVED | 28 129 | GND RESERVED | 29 128 | RESERVED RESERVED | 30 127 | RESERVED RESERVED | 31 126 | RESERVED GND | 32 125 | SRAM_CEn VCCINT | 33 124 | VCCINT VCCIO | 34 123 | GND GND | 35 122 | RESERVED RESERVED | 36 121 | RESERVED tst_out | 37 120 | RESERVED RESERVED | 38 119 | RESERVED pre_in | 39 118 | VCCIO RESERVED | 40 117 | GND RESERVED | 41 116 | RESERVED VCCIO | 42 115 | RESERVED GND | 43 114 | RESERVED RESERVED | 44 113 | RESERVED RESERVED | 45 112 | RESERVED RESERVED | 46 111 | RESERVED RESERVED | 47 110 | VCCIO VCCINT | 48 109 | GND GND | 49 108 | ^MSEL0 #TMS | 50 107 | ^MSEL1 #TRST | 51 106 | VCCINT ^nSTATUS | 52 105 | ^nCONFIG | 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _| \ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 | \----------------------------------------------------------------------------------------------------------- R R R R R R G R R R R R R V R R R R R V R R R G V G G G G G R V R R R R R R V R R R R R R V R R R R R R E E E E E E N E E E E E E C E E E E E C E E E N C N N N N N E C E E E E E E C E E E E E E C E E E E E E S S S S S S D S S S S S S C S S S S S C S S S D C D D D D D S C S S S S S S C S S S S S S C S S S S S S E E E E E E E E E E E E I E E E E E I E E E _ _ E I E E E E E E I E E E E E E I E E E E E E R R R R R R R R R R R R O R R R R R N R R R C C R O R R R R R R N R R R R R R O R R R R R R V V V V V V V V V V V V V V V V V T V V V K K V V V V V V V T V V V V V V V V V V V V E E E E E E E E E E E E E E E E E E E E L L E E E E E E E E E E E E E E E E E E E D D D D D D D D D D D D D D D D D D D D K K D D D D D D D D D D D D D D D D D D D N.C. = No Connect. This pin has no internal connection to the device. VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts). VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts). GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which is tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. $ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant. Device-Specific Information: e:\tiserv\trigger\maxplus\top_pre.rpt top_pre ** RESOURCE USAGE ** Logic Column Row Array Interconnect Interconnect Clears/ External Block Logic Cells Driven Driven Clocks Presets Interconnect I32 8/ 8(100%) 0/ 8( 0%) 0/ 8( 0%) 1/2 0/2 0/26( 0%) I34 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 0/26( 0%) I35 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/26( 3%) I37 6/ 8( 75%) 2/ 8( 25%) 0/ 8( 0%) 2/2 0/2 3/26( 11%) L26 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 2/26( 7%) L28 5/ 8( 62%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 4/26( 15%) L29 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/26( 15%) L34 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 5/26( 19%) L35 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/26( 15%) L37 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 5/26( 19%) L38 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/26( 15%) L41 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 3/26( 11%) L42 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 10/26( 38%) L44 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 10/26( 38%) L45 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 13/26( 50%) L46 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 11/26( 42%) L47 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/26( 19%) L48 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 18/26( 69%) L52 3/ 8( 37%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 1/26( 3%) Embedded Column Row Array Embedded Interconnect Interconnect Read/ External Block Cells Driven Driven Clocks Write Interconnect Total dedicated input pins used: 3/6 ( 50%) Total I/O pins used: 20/141 ( 14%) Total logic cells used: 102/4992 ( 2%) Total embedded cells used: 0/192 ( 0%) Total EABs used: 0/12 ( 0%) Average fan-in: 2.34/4 ( 58%) Total fan-in: 239/19968 ( 1%) Total input pins required: 8 Total input I/O cell registers required: 0 Total output pins required: 15 Total output I/O cell registers required: 0 Total buried I/O cell registers required: 0 Total bidirectional pins required: 0 Total reserved pins required 0 Total logic cells required: 102 Total flipflops required: 56 Total packed registers required: 0 Total logic cells in carry chains: 26 Total number of carry chains: 2 Total number of carry chains of length 1-8 : 0 Total number of carry chains of length 9-16: 2 Total logic cells in cascade chains: 11 Total number of cascade chains: 5 Total single-pin Clock Enables required: 0 Total single-pin Output Enables required: 0 Synthesized logic cells: 1/4992 ( 0%) Logic Cell and Embedded Cell Counts Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC) A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 1 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23/0 J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0 L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 5 1 0 0 0 0 3 1 0 8 1 0 0 1 8 0 8 8 8 8 8 0 0 0 3 79/0 Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 5 1 0 0 8 0 11 2 0 14 1 0 0 1 8 0 8 8 8 8 8 0 0 0 3 102/0 Device-Specific Information: e:\tiserv\trigger\maxplus\top_pre.rpt top_pre ** INPUTS ** Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name 182 - - - -- INPUT G ^ 0 0 0 0 CLK 184 - - - -- INPUT ^ 0 0 0 1 inp_sw 8 - - A -- INPUT ^ 0 0 0 0 LVDS_in0 7 - - A -- INPUT ^ 0 0 0 1 LVDS_in1 9 - - A -- INPUT ^ 0 0 0 0 LVDS_in2 10 - - A -- INPUT ^ 0 0 0 0 LVDS_in3 183 - - - -- INPUT ^ 0 0 0 1 mode_sw 39 - - J -- INPUT ^ 0 0 0 1 pre_in Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell ^ = Increased input delay * = PCI I/O is enabled @ = Uses single-pin Clock Enable & = Uses single-pin Output Enable G = Global Source. Fan-out destinations counted here do not include destinations that are driven using global routing resources. Refer to the Auto Global Signals, Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals Sections of this Report File for information on which signals' fan-outs are used as Clock, Clear, Preset, Output Enable, and synchronous Load signals. Device-Specific Information: e:\tiserv\trigger\maxplus\top_pre.rpt top_pre ** OUTPUTS ** Fed By Fed By Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name 27 - - F -- OUTPUT 0 0 0 0 ADC_OEn 193 - - - 38 OUTPUT 0 1 0 0 LED_RED 206 - - - 50 OUTPUT 0 0 0 0 LVDS_EN 25 - - E -- OUTPUT 0 1 0 0 pre_out 208 - - - 52 OUTPUT 0 1 0 0 pre_out_lvds 192 - - - 37 OUTPUT 0 1 0 0 R7S1 180 - - - 26 OUTPUT 0 1 0 0 R7S2 186 - - - 27 OUTPUT 0 1 0 0 R7S3 187 - - - 28 OUTPUT 0 1 0 0 R7S4 189 - - - 30 OUTPUT 0 1 0 0 R7S5 191 - - - 35 OUTPUT 0 1 0 0 R7S6 190 - - - 33 OUTPUT 0 1 0 0 R7S7 125 - - F -- OUTPUT 0 0 0 0 SRAM_CEn 131 - - E -- OUTPUT 0 0 0 0 SRAM_OEn 37 - - I -- OUTPUT 0 1 0 0 tst_out Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell ^ = Increased input delay * = PCI I/O is enabled @ = Uses single-pin Clock Enable & = Uses single-pin Output Enable Device-Specific Information: e:\tiserv\trigger\maxplus\top_pre.rpt top_pre ** BURIED LOGIC ** Fan-In Fan-Out IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name - 2 - L 42 LCELL 0 2 0 1 nx910_lc (counter_add_29_ix31_lc) - 3 - L 42 LCELL 0 1 0 1 nx912_lc (counter_add_29_ix35_lc) - 4 - L 42 LCELL 0 1 0 1 nx914_lc (counter_add_29_ix39_lc) - 5 - L 42 LCELL 0 1 0 1 nx916_lc (counter_add_29_ix43_lc) - 6 - L 42 LCELL 0 1 0 1 nx918_lc (counter_add_29_ix47_lc) - 7 - L 42 LCELL 0 1 0 1 nx920_lc (counter_add_29_ix51_lc) - 8 - L 42 LCELL 0 1 0 1 nx922_lc (counter_add_29_ix55_lc) - 1 - L 44 LCELL 0 1 0 1 nx924_lc (counter_add_29_ix59_lc) - 5 - L 37 DFFE + 0 2 0 7 pre_in_fil (fin_reg_q) - 6 - L 37 DFFE + 2 1 0 2 fin_SAMPLES_0 (fin_reg_SAMPLES_0) - 7 - L 37 DFFE + 0 1 0 1 fin_SAMPLES_1 (fin_reg_SAMPLES_1) - 3 - L 26 DFFE 0 4 0 4 mode_sw_f (fmd_reg_q) - 1 - I 37 DFFE 1 1 0 2 fmd_SAMPLES_0 (fmd_reg_SAMPLES_0) - 1 - L 26 DFFE 0 2 0 2 fmd_SAMPLES_1 (fmd_reg_SAMPLES_1) - 2 - L 26 DFFE 0 2 0 1 fmd_SAMPLES_2 (fmd_reg_SAMPLES_2) - 6 - I 37 DFFE 0 4 0 1 inp_sw_f (fmi_reg_q) - 2 - I 37 DFFE 1 1 0 2 fmi_SAMPLES_0 (fmi_reg_SAMPLES_0) - 3 - I 37 DFFE 0 2 0 2 fmi_SAMPLES_1 (fmi_reg_SAMPLES_1) - 5 - I 37 DFFE 0 2 0 1 fmi_SAMPLES_2 (fmi_reg_SAMPLES_2) - 6 - L 47 LCELL 0 3 0 19 nx730_lc (ix778_lc) - 7 - L 47 LCELL 0 4 0 1 NOT_nx261_lc (ix779_lc) - 5 - L 47 LCELL 0 4 0 1 NOT_nx257_lc (ix780_lc) - 1 - L 47 LCELL 0 4 0 1 NOT_nx253_lc (ix781_lc) - 2 - L 37 LCELL 0 3 0 1 nx358_lc (ix782_lc) - 3 - L 37 LCELL 0 2 0 10 nx739_lc (ix783_lc) - 8 - L 37 LCELL 0 2 0 1 nx745_lc (ix785_lc) - 6 - L 38 LCELL 0 4 1 0 R7S_1_lc (ix786_lc) - 4 - L 26 LCELL 0 4 1 0 R7S_2_lc (ix787_lc) - 6 - L 28 LCELL 0 4 1 0 R7S_3_lc (ix788_lc) - 7 - L 28 LCELL 0 4 1 0 R7S_4_lc (ix789_lc) - 4 - L 29 LCELL 0 4 1 0 R7S_5_lc (ix790_lc) - 1 - L 35 LCELL 0 4 1 0 R7S_6_lc (ix791_lc) - 2 - L 34 LCELL 0 4 1 0 R7S_7_lc (ix792_lc) - 2 - L 47 LCELL 0 3 0 4 nx862_lc (ix793_lc) - 8 - L 46 LCELL 0 3 0 1 modgen_gt_26_nx98_lc (ix794_lc) - 5 - L 46 LCELL 0 3 0 1 NOT_modgen_gt_26_nx102_lc (ix795_lc) - 6 - L 45 LCELL 0 3 0 1 nx863_lc (ix796_lc) - 4 - L 44 LCELL 0 4 0 1 nx864_lc (ix797_lc) - 6 - L 44 LCELL 0 4 0 1 nx865_lc (ix798_lc) - 3 - L 44 LCELL 0 4 0 1 nx866_lc (ix799_lc) - 1 - L 45 CASCADE 0 4 0 1 nx867_cas (ix800_cas) - 2 - L 45 LCELL 0 5 0 3 NOT_nx155_lc (ix801_lc) - 7 - L 45 LCELL 0 2 0 1 nx738_lc (ix803_lc) - 8 - L 45 LCELL 0 4 0 3 nx736_lc (ix804_lc) - 1 - L 48 CASCADE 0 3 0 1 nx869_cas (ix805_cas) - 2 - L 48 LCELL 0 3 0 1 nx870_lc (ix806_lc) - 1 - L 46 CASCADE 0 2 0 1 nx872_cas (ix808_cas) - 2 - L 46 LCELL 0 5 0 5 modgen_gt_27_nx140_lc (ix809_lc) - 5 - L 44 LCELL 0 4 0 4 NOT_nx166_lc (ix810_lc) - 7 - L 46 LCELL 0 2 0 1 nx873_lc (ix811_lc) - 7 - L 48 CASCADE 0 2 0 1 nx874_cas (ix812_cas) - 4 - L 34 LCELL 0 2 0 1 nx875_lc (ix813_lc) - 8 - L 48 LCELL 0 5 0 1 nx876_lc (ix814_lc) - 3 - L 46 LCELL 0 3 0 1 nx877_lc (ix815_lc) - 4 - L 48 CASCADE 0 3 0 1 nx881_cas (ix819_cas) - 6 - L 48 LCELL 0 4 0 1 nx882_lc (ix820_lc) - 5 - L 48 LCELL 0 5 0 1 nx883_lc (ix821_lc) - 1 - I 32 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs0 - 2 - I 32 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs1 - 3 - I 32 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs2 - 4 - I 32 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs3 - 5 - I 32 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs4 - 6 - I 32 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs5 - 7 - I 32 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs6 - 8 - I 32 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs7 - 1 - I 34 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs8 - 2 - I 34 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs9 - 3 - I 34 DFFE + 0 0 0 1 |lpm_counter:div_clk_ix7|dffs10 - 4 - I 34 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs11 - 5 - I 34 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs12 - 6 - I 34 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs13 - 7 - I 34 DFFE + 0 0 0 0 |lpm_counter:div_clk_ix7|dffs14 - 8 - I 34 DFFE + 0 0 0 8 |lpm_counter:div_clk_ix7|dffs15 - 3 - L 45 DFFE + 0 3 0 3 counter_0 (reg_counter_0) - 4 - L 45 DFFE + 0 3 0 3 counter_1 (reg_counter_1) - 8 - L 44 DFFE + 0 3 0 3 counter_2 (reg_counter_2) - 5 - L 45 DFFE + 0 3 0 3 counter_3 (reg_counter_3) - 4 - L 46 DFFE + 0 3 0 7 counter_4 (reg_counter_4) - 1 - L 37 DFFE + 0 3 0 7 counter_5 (reg_counter_5) - 6 - L 46 DFFE + 0 3 0 8 counter_6 (reg_counter_6) - 2 - L 41 DFFE + 0 3 0 5 counter_7 (reg_counter_7) - 7 - L 44 DFFE + 0 3 0 6 counter_8 (reg_counter_8) - 2 - L 44 DFFE + 0 2 0 4 counter_9 (reg_counter_9) - 1 - L 42 DFFE + 0 3 0 2 c0 (reg_c0) - 4 - I 37 DFFE 0 1 1 1 reg_inp_sel - 8 - L 28 DFFE + 0 1 0 1 L0en (reg_L0en) - 8 - L 47 DFFE + 0 3 0 5 L0pass (reg_L0pass) - 1 - L 34 DFFE + 0 1 0 1 L1en (reg_L1en) - 4 - L 47 DFFE + 0 3 0 3 L1pass (reg_L1pass) - 2 - L 28 DFFE + 0 1 0 1 L2en (reg_L2en) - 3 - L 47 DFFE + 0 3 0 2 L2pass (reg_L2pass) - 6 - L 26 DFFE 0 4 0 11 mode_0 (reg_mode_0) - 7 - L 26 DFFE 0 4 0 11 mode_1 (reg_mode_1) - 8 - L 26 DFFE 0 3 0 11 mode_2 (reg_mode_2) - 5 - L 26 DFFE 0 4 0 10 mode_3 (reg_mode_3) - 1 - L 28 DFFE + 0 1 0 1 pre_en (reg_pre_en) - 4 - L 37 DFFE + 0 1 0 6 pre_in_fil_old (reg_pre_in_fil_old) - 8 - L 52 DFFE + 0 2 1 0 reg_pre_out_i - 1 - L 52 DFFE +s 0 2 1 0 reg_pre_out_i~1 - 3 - L 48 DFFE + 0 3 0 3 pre_start (reg_pre_start) - 2 - L 52 DFFE + 0 1 0 2 pre_start1 (reg_pre_start1) - 2 - I 35 DFFE + 0 1 1 0 reg_tst_out - 1 - L 42 CARRY 0 3 0 1 |carry_sum:counter_add_29_ix29_carry_sum|:31 - 2 - L 42 CARRY 0 3 0 1 |carry_sum:counter_add_29_ix31_carry_sum|:31 - 3 - L 42 CARRY 0 2 0 1 |carry_sum:counter_add_29_ix35_carry_sum|:31 - 4 - L 42 CARRY 0 2 0 1 |carry_sum:counter_add_29_ix39_carry_sum|:31 - 5 - L 42 CARRY 0 2 0 1 |carry_sum:counter_add_29_ix43_carry_sum|:31 - 6 - L 42 CARRY 0 2 0 1 |carry_sum:counter_add_29_ix47_carry_sum|:31 - 7 - L 42 CARRY 0 2 0 1 |carry_sum:counter_add_29_ix51_carry_sum|:31 - 8 - L 42 CARRY 0 2 0 1 |carry_sum:counter_add_29_ix55_carry_sum|:31 - 1 - L 44 CARRY 0 2 0 1 |carry_sum:counter_add_29_ix59_carry_sum|:31 - 1 - I 32 CARRY 0 0 0 1 |lpm_counter:div_clk_ix7|carrybit1 - 2 - I 32 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit2 - 3 - I 32 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit3 - 4 - I 32 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit4 - 5 - I 32 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit5 - 6 - I 32 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit6 - 7 - I 32 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit7 - 8 - I 32 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit8 - 1 - I 34 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit9 - 2 - I 34 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit10 - 3 - I 34 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit11 - 4 - I 34 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit12 - 5 - I 34 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit13 - 6 - I 34 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit14 - 7 - I 34 CARRY 0 1 0 1 |lpm_counter:div_clk_ix7|carrybit15 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell ^ = Increased input delay * = PCI I/O is enabled p = Packed register Device-Specific Information: e:\tiserv\trigger\maxplus\top_pre.rpt top_pre ** FASTTRACK INTERCONNECT UTILIZATION ** Row FastTrack Interconnect: Global Left Half- Right Half- FastTrack FastTrack FastTrack Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins A: 1/208( 0%) 0/104( 0%) 0/104( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%) B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) E: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%) F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%) G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) I: 2/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%) J: 1/208( 0%) 0/104( 0%) 0/104( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%) K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%) L: 46/208( 22%) 0/104( 0%) 3/104( 2%) 0/16( 0%) 0/16( 0%) 0/16( 0%) Column FastTrack Interconnect: FastTrack Column Interconnect Input Pins Output Pins Bidir Pins 01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 26: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 27: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 30: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 33: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 34: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 37: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 38: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 50: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 51: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 52: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%) EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) Device-Specific Information: e:\tiserv\trigger\maxplus\top_pre.rpt top_pre ** CLOCK SIGNALS ** Type Fan-out Name INPUT 43 CLK DFF 9 |lpm_counter:div_clk_ix7|dffs15 DFF 5 mode_sw_f DFF 2 inp_sw_f Device-Specific Information: e:\tiserv\trigger\maxplus\top_pre.rpt top_pre ** CARRY CHAINS ** Type Member Length Member Name: SUM, (CARRY) UP/DOWN COUNTER 1 |lpm_counter:div_clk_ix7|dffs0, (|lpm_counter:div_clk_ix7|carrybit1) UP/DOWN COUNTER 2 |lpm_counter:div_clk_ix7|dffs1, (|lpm_counter:div_clk_ix7|carrybit2) UP/DOWN COUNTER 3 |lpm_counter:div_clk_ix7|dffs2, (|lpm_counter:div_clk_ix7|carrybit3) UP/DOWN COUNTER 4 |lpm_counter:div_clk_ix7|dffs3, (|lpm_counter:div_clk_ix7|carrybit4) UP/DOWN COUNTER 5 |lpm_counter:div_clk_ix7|dffs4, (|lpm_counter:div_clk_ix7|carrybit5) UP/DOWN COUNTER 6 |lpm_counter:div_clk_ix7|dffs5, (|lpm_counter:div_clk_ix7|carrybit6) UP/DOWN COUNTER 7 |lpm_counter:div_clk_ix7|dffs6, (|lpm_counter:div_clk_ix7|carrybit7) UP/DOWN COUNTER 8 |lpm_counter:div_clk_ix7|dffs7, (|lpm_counter:div_clk_ix7|carrybit8) UP/DOWN COUNTER 9 |lpm_counter:div_clk_ix7|dffs8, (|lpm_counter:div_clk_ix7|carrybit9) UP/DOWN COUNTER 10 |lpm_counter:div_clk_ix7|dffs9, (|lpm_counter:div_clk_ix7|carrybit10) UP/DOWN COUNTER 11 |lpm_counter:div_clk_ix7|dffs10, (|lpm_counter:div_clk_ix7|carrybit11) UP/DOWN COUNTER 12 |lpm_counter:div_clk_ix7|dffs11, (|lpm_counter:div_clk_ix7|carrybit12) UP/DOWN COUNTER 13 |lpm_counter:div_clk_ix7|dffs12, (|lpm_counter:div_clk_ix7|carrybit13) UP/DOWN COUNTER 14 |lpm_counter:div_clk_ix7|dffs13, (|lpm_counter:div_clk_ix7|carrybit14) UP/DOWN COUNTER 15 |lpm_counter:div_clk_ix7|dffs14, (|lpm_counter:div_clk_ix7|carrybit15) NORMAL 16 |lpm_counter:div_clk_ix7|dffs15 UP/DOWN COUNTER 1 c0, (|carry_sum:counter_add_29_ix29_carry_sum|:31) ARITHMETIC 2 nx910_lc, (|carry_sum:counter_add_29_ix31_carry_sum|:31) ARITHMETIC 3 nx912_lc, (|carry_sum:counter_add_29_ix35_carry_sum|:31) ARITHMETIC 4 nx914_lc, (|carry_sum:counter_add_29_ix39_carry_sum|:31) ARITHMETIC 5 nx916_lc, (|carry_sum:counter_add_29_ix43_carry_sum|:31) ARITHMETIC 6 nx918_lc, (|carry_sum:counter_add_29_ix47_carry_sum|:31) ARITHMETIC 7 nx920_lc, (|carry_sum:counter_add_29_ix51_carry_sum|:31) ARITHMETIC 8 nx922_lc, (|carry_sum:counter_add_29_ix55_carry_sum|:31) ARITHMETIC 9 nx924_lc, (|carry_sum:counter_add_29_ix59_carry_sum|:31) NORMAL 10 counter_9 Device-Specific Information: e:\tiserv\trigger\maxplus\top_pre.rpt top_pre ** EQUATIONS ** CLK : INPUT; inp_sw : INPUT; LVDS_in0 : INPUT; LVDS_in1 : INPUT; LVDS_in2 : INPUT; LVDS_in3 : INPUT; mode_sw : INPUT; pre_in : INPUT; -- Node name is 'ADC_OEn' from file "top_pre.edf" line 108 -- Equation name is 'ADC_OEn', type is output ADC_OEn = VCC; -- Node name is 'reg_counter_0' = 'counter_0' from file "top_pre.edf" line 231 -- Equation name is 'reg_counter_0', location is LC3_L45, type is buried. counter_0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC); _EQ001 = counter_0 & !nx730_lc & !nx739_lc # !counter_0 & !c0 & nx730_lc # counter_0 & c0 & nx730_lc; -- Node name is 'reg_counter_1' = 'counter_1' from file "top_pre.edf" line 230 -- Equation name is 'reg_counter_1', location is LC4_L45, type is buried. counter_1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC); _EQ002 = counter_1 & !nx730_lc & !nx739_lc # nx730_lc & nx910_lc; -- Node name is 'reg_counter_2' = 'counter_2' from file "top_pre.edf" line 229 -- Equation name is 'reg_counter_2', location is LC8_L44, type is buried. counter_2 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC); _EQ003 = counter_2 & !nx730_lc & !nx739_lc # nx730_lc & nx912_lc; -- Node name is 'reg_counter_3' = 'counter_3' from file "top_pre.edf" line 228 -- Equation name is 'reg_counter_3', location is LC5_L45, type is buried. counter_3 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC); _EQ004 = counter_3 & !nx730_lc & !nx739_lc # nx730_lc & nx914_lc; -- Node name is 'reg_counter_4' = 'counter_4' from file "top_pre.edf" line 227 -- Equation name is 'reg_counter_4', location is LC4_L46, type is buried. counter_4 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC); _EQ005 = counter_4 & !nx730_lc & !nx739_lc # nx730_lc & nx916_lc; -- Node name is 'reg_counter_5' = 'counter_5' from file "top_pre.edf" line 226 -- Equation name is 'reg_counter_5', location is LC1_L37, type is buried. counter_5 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC); _EQ006 = counter_5 & !nx730_lc & !nx739_lc # nx730_lc & nx918_lc; -- Node name is 'reg_counter_6' = 'counter_6' from file "top_pre.edf" line 225 -- Equation name is 'reg_counter_6', location is LC6_L46, type is buried. counter_6 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC); _EQ007 = counter_6 & !nx730_lc & !nx739_lc # nx730_lc & nx920_lc; -- Node name is 'reg_counter_7' = 'counter_7' from file "top_pre.edf" line 224 -- Equation name is 'reg_counter_7', location is LC2_L41, type is buried. counter_7 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC); _EQ008 = counter_7 & !nx730_lc & !nx739_lc # nx730_lc & nx922_lc; -- Node name is 'reg_counter_8' = 'counter_8' from file "top_pre.edf" line 223 -- Equation name is 'reg_counter_8', location is LC7_L44, type is buried. counter_8 = DFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC); _EQ009 = counter_8 & !nx730_lc & !nx739_lc # nx730_lc & nx924_lc; -- Node name is 'reg_counter_9' = 'counter_9' from file "top_pre.edf" line 222 -- Equation name is 'reg_counter_9', location is LC2_L44, type is buried. counter_9 = DFFE( _EQ010, GLOBAL( CLK), VCC, VCC, VCC); _EQ010 = !counter_9 & _LC1_L44_CARRY & nx730_lc # counter_9 & !_LC1_L44_CARRY & nx730_lc # counter_9 & !nx730_lc & !nx739_lc; -- Node name is 'reg_c0' = 'c0' from file "top_pre.edf" line 221 -- Equation name is 'reg_c0', location is LC1_L42, type is buried. -- c0 is in Up/Down Counter Mode -- synchronous load = nx730_lc -- synchronous data = nx730_lc c0 = DFFE((!c0 & nx730_lc # nx730_lc & !nx730_lc), GLOBAL( CLK), VCC, VCC, nx358_lc); -- Node name is 'fin_reg_SAMPLES_0' = 'fin_SAMPLES_0' from file "top_pre.edf" line 254 -- Equation name is 'fin_reg_SAMPLES_0', location is LC6_L37, type is buried. fin_SAMPLES_0 = DFFE( _EQ011, GLOBAL( CLK), VCC, VCC, VCC); _EQ011 = pre_in & !reg_inp_sel # LVDS_in1 & reg_inp_sel; -- Node name is 'fin_reg_SAMPLES_1' = 'fin_SAMPLES_1' from file "top_pre.edf" line 253 -- Equation name is 'fin_reg_SAMPLES_1', location is LC7_L37, type is buried. fin_SAMPLES_1 = DFFE( fin_SAMPLES_0, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'fmd_reg_SAMPLES_0' = 'fmd_SAMPLES_0' from file "top_pre.edf" line 247 -- Equation name is 'fmd_reg_SAMPLES_0', location is LC1_I37, type is buried. fmd_SAMPLES_0 = DFFE( mode_sw, _LC8_I34, VCC, VCC, VCC); -- Node name is 'fmd_reg_SAMPLES_1' = 'fmd_SAMPLES_1' from file "top_pre.edf" line 246 -- Equation name is 'fmd_reg_SAMPLES_1', location is LC1_L26, type is buried. fmd_SAMPLES_1 = DFFE( fmd_SAMPLES_0, _LC8_I34, VCC, VCC, VCC); -- Node name is 'fmd_reg_SAMPLES_2' = 'fmd_SAMPLES_2' from file "top_pre.edf" line 245 -- Equation name is 'fmd_reg_SAMPLES_2', location is LC2_L26, type is buried. fmd_SAMPLES_2 = DFFE( fmd_SAMPLES_1, _LC8_I34, VCC, VCC, VCC); -- Node name is 'fmi_reg_SAMPLES_0' = 'fmi_SAMPLES_0' from file "top_pre.edf" line 251 -- Equation name is 'fmi_reg_SAMPLES_0', location is LC2_I37, type is buried. fmi_SAMPLES_0 = DFFE( inp_sw, _LC8_I34, VCC, VCC, VCC); -- Node name is 'fmi_reg_SAMPLES_1' = 'fmi_SAMPLES_1' from file "top_pre.edf" line 250 -- Equation name is 'fmi_reg_SAMPLES_1', location is LC3_I37, type is buried. fmi_SAMPLES_1 = DFFE( fmi_SAMPLES_0, _LC8_I34, VCC, VCC, VCC); -- Node name is 'fmi_reg_SAMPLES_2' = 'fmi_SAMPLES_2' from file "top_pre.edf" line 249 -- Equation name is 'fmi_reg_SAMPLES_2', location is LC5_I37, type is buried. fmi_SAMPLES_2 = DFFE( fmi_SAMPLES_1, _LC8_I34, VCC, VCC, VCC); -- Node name is 'fmi_reg_q' = 'inp_sw_f' from file "top_pre.edf" line 248 -- Equation name is 'fmi_reg_q', location is LC6_I37, type is buried. inp_sw_f = DFFE( _EQ012, _LC8_I34, VCC, VCC, VCC); _EQ012 = fmi_SAMPLES_0 & fmi_SAMPLES_1 & fmi_SAMPLES_2 # fmi_SAMPLES_2 & inp_sw_f # fmi_SAMPLES_1 & inp_sw_f # fmi_SAMPLES_0 & inp_sw_f; -- Node name is 'LED_RED' from file "top_pre.edf" line 106 -- Equation name is 'LED_RED', type is output LED_RED = reg_inp_sel; -- Node name is 'LVDS_EN' from file "top_pre.edf" line 107 -- Equation name is 'LVDS_EN', type is output LVDS_EN = VCC; -- Node name is 'reg_L0en' = 'L0en' from file "top_pre.edf" line 242 -- Equation name is 'reg_L0en', location is LC8_L28, type is buried. L0en = DFFE( mode_1, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'reg_L0pass' = 'L0pass' from file "top_pre.edf" line 232 -- Equation name is 'reg_L0pass', location is LC8_L47, type is buried. L0pass = DFFE( _EQ013, GLOBAL( CLK), VCC, VCC, NOT_nx261_lc); _EQ013 = !NOT_nx155_lc & nx730_lc; -- Node name is 'reg_L1en' = 'L1en' from file "top_pre.edf" line 241 -- Equation name is 'reg_L1en', location is LC1_L34, type is buried. L1en = DFFE( mode_2, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'reg_L1pass' = 'L1pass' from file "top_pre.edf" line 233 -- Equation name is 'reg_L1pass', location is LC4_L47, type is buried. L1pass = DFFE( _EQ014, GLOBAL( CLK), VCC, VCC, NOT_nx257_lc); _EQ014 = !NOT_nx166_lc & nx730_lc; -- Node name is 'reg_L2en' = 'L2en' from file "top_pre.edf" line 240 -- Equation name is 'reg_L2en', location is LC2_L28, type is buried. L2en = DFFE( mode_3, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'reg_L2pass' = 'L2pass' from file "top_pre.edf" line 234 -- Equation name is 'reg_L2pass', location is LC3_L47, type is buried. L2pass = DFFE( _EQ015, GLOBAL( CLK), VCC, VCC, NOT_nx253_lc); _EQ015 = modgen_gt_27_nx140_lc & nx730_lc; -- Node name is 'fmd_reg_q' = 'mode_sw_f' from file "top_pre.edf" line 244 -- Equation name is 'fmd_reg_q', location is LC3_L26, type is buried. mode_sw_f = DFFE( _EQ016, _LC8_I34, VCC, VCC, VCC); _EQ016 = fmd_SAMPLES_1 & mode_sw_f # fmd_SAMPLES_0 & mode_sw_f # fmd_SAMPLES_2 & mode_sw_f # fmd_SAMPLES_0 & fmd_SAMPLES_1 & fmd_SAMPLES_2; -- Node name is 'reg_mode_0' = 'mode_0' from file "top_pre.edf" line 219 -- Equation name is 'reg_mode_0', location is LC6_L26, type is buried. mode_0 = DFFE( _EQ017, mode_sw_f, VCC, VCC, VCC); _EQ017 = !mode_1 & !mode_2 & !mode_3 # mode_0 & mode_1 & !mode_3 # mode_0 & mode_1 & !mode_2; -- Node name is 'reg_mode_1' = 'mode_1' from file "top_pre.edf" line 218 -- Equation name is 'reg_mode_1', location is LC7_L26, type is buried. mode_1 = DFFE( _EQ018, mode_sw_f, VCC, VCC, VCC); _EQ018 = mode_0 & mode_1 & !mode_3 # mode_0 & !mode_2 & !mode_3 # mode_0 & mode_1 & !mode_2; -- Node name is 'reg_mode_2' = 'mode_2' from file "top_pre.edf" line 217 -- Equation name is 'reg_mode_2', location is LC8_L26, type is buried. mode_2 = DFFE( _EQ019, mode_sw_f, VCC, VCC, VCC); _EQ019 = mode_0 & mode_1 & !mode_2; -- Node name is 'reg_mode_3' = 'mode_3' from file "top_pre.edf" line 216 -- Equation name is 'reg_mode_3', location is LC5_L26, type is buried. mode_3 = DFFE( _EQ020, mode_sw_f, VCC, VCC, VCC); _EQ020 = mode_0 & mode_1 & !mode_2 & mode_3 # mode_0 & mode_1 & mode_2 & !mode_3; -- Node name is 'ix794_lc' = 'modgen_gt_26_nx98_lc' from file "top_pre.edf" line 494 -- Equation name is 'ix794_lc', location is LC8_L46, type is buried. modgen_gt_26_nx98_lc = LCELL( _EQ021); _EQ021 = !counter_4 & counter_5 & !counter_6; -- Node name is 'ix809_lc' = 'modgen_gt_27_nx140_lc' from file "top_pre.edf" line 508 -- Equation name is 'ix809_lc', location is LC2_L46, type is buried. modgen_gt_27_nx140_lc = LCELL( _EQ022C); _EQ022C = _EQ022 & CASCADE( _EQ023C); _EQ022 = !NOT_modgen_gt_26_nx102_lc # modgen_gt_26_nx98_lc & nx736_lc # counter_7; -- Node name is 'ix795_lc' = 'NOT_modgen_gt_26_nx102_lc' from file "top_pre.edf" line 495 -- Equation name is 'ix795_lc', location is LC5_L46, type is buried. NOT_modgen_gt_26_nx102_lc = LCELL( _EQ024); _EQ024 = !counter_4 & !counter_6 # !counter_5 & !counter_6; -- Node name is 'ix801_lc' = 'NOT_nx155_lc' from file "top_pre.edf" line 501 -- Equation name is 'ix801_lc', location is LC2_L45, type is buried. NOT_nx155_lc = LCELL( _EQ025C); _EQ025C = _EQ025 & CASCADE( _EQ026C); _EQ025 = !nx738_lc # !counter_5 & !nx736_lc # !counter_4 & !counter_5; -- Node name is 'ix810_lc' = 'NOT_nx166_lc' from file "top_pre.edf" line 509 -- Equation name is 'ix810_lc', location is LC5_L44, type is buried. NOT_nx166_lc = LCELL( _EQ027); _EQ027 = !nx866_lc # !nx864_lc & nx865_lc # !nx863_lc & nx865_lc; -- Node name is 'ix781_lc' = 'NOT_nx253_lc' from file "top_pre.edf" line 482 -- Equation name is 'ix781_lc', location is LC1_L47, type is buried. NOT_nx253_lc = LCELL( _EQ028); _EQ028 = !nx730_lc & pre_in_fil & !pre_in_fil_old # modgen_gt_27_nx140_lc & nx730_lc; -- Node name is 'ix780_lc' = 'NOT_nx257_lc' from file "top_pre.edf" line 481 -- Equation name is 'ix780_lc', location is LC5_L47, type is buried. NOT_nx257_lc = LCELL( _EQ029); _EQ029 = !NOT_nx166_lc & nx730_lc # !nx730_lc & pre_in_fil & !pre_in_fil_old; -- Node name is 'ix779_lc' = 'NOT_nx261_lc' from file "top_pre.edf" line 480 -- Equation name is 'ix779_lc', location is LC7_L47, type is buried. NOT_nx261_lc = LCELL( _EQ030); _EQ030 = !nx730_lc & pre_in_fil & !pre_in_fil_old # !NOT_nx155_lc & nx730_lc; -- Node name is 'ix782_lc' = 'nx358_lc' from file "top_pre.edf" line 483 -- Equation name is 'ix782_lc', location is LC2_L37, type is buried. nx358_lc = LCELL( _EQ031); _EQ031 = pre_in_fil & !pre_in_fil_old # nx730_lc; -- Node name is 'ix778_lc' = 'nx730_lc' from file "top_pre.edf" line 479 -- Equation name is 'ix778_lc', location is LC6_L47, type is buried. nx730_lc = LCELL( _EQ032); _EQ032 = !L0pass # !L1pass # !L2pass; -- Node name is 'ix804_lc' = 'nx736_lc' from file "top_pre.edf" line 503 -- Equation name is 'ix804_lc', location is LC8_L45, type is buried. nx736_lc = LCELL( _EQ033); _EQ033 = counter_2 # counter_3 # counter_0 # counter_1; -- Node name is 'ix803_lc' = 'nx738_lc' from file "top_pre.edf" line 502 -- Equation name is 'ix803_lc', location is LC7_L45, type is buried. nx738_lc = LCELL( _EQ034); _EQ034 = counter_6 & !L0pass; -- Node name is 'ix783_lc' = 'nx739_lc' from file "top_pre.edf" line 484 -- Equation name is 'ix783_lc', location is LC3_L37, type is buried. nx739_lc = LCELL( _EQ035); _EQ035 = pre_in_fil & !pre_in_fil_old; -- Node name is 'ix785_lc' = 'nx745_lc' from file "top_pre.edf" line 485 -- Equation name is 'ix785_lc', location is LC8_L37, type is buried. nx745_lc = LCELL( _EQ036); _EQ036 = pre_in_fil & !pre_in_fil_old; -- Node name is 'ix793_lc' = 'nx862_lc' from file "top_pre.edf" line 493 -- Equation name is 'ix793_lc', location is LC2_L47, type is buried. nx862_lc = LCELL( _EQ037); _EQ037 = L0pass & L1pass & L2pass; -- Node name is 'ix796_lc' = 'nx863_lc' from file "top_pre.edf" line 496 -- Equation name is 'ix796_lc', location is LC6_L45, type is buried. nx863_lc = LCELL( _EQ038); _EQ038 = counter_1 & !counter_4 # counter_0 & !counter_4; -- Node name is 'ix797_lc' = 'nx864_lc' from file "top_pre.edf" line 497 -- Equation name is 'ix797_lc', location is LC4_L44, type is buried. nx864_lc = LCELL( _EQ039); _EQ039 = counter_2 & counter_3 & counter_5 & !counter_6; -- Node name is 'ix798_lc' = 'nx865_lc' from file "top_pre.edf" line 498 -- Equation name is 'ix798_lc', location is LC6_L44, type is buried. nx865_lc = LCELL( _EQ040); _EQ040 = !counter_4 & !counter_6 & !counter_8 # !counter_5 & !counter_6 & !counter_8; -- Node name is 'ix799_lc' = 'nx866_lc' from file "top_pre.edf" line 499 -- Equation name is 'ix799_lc', location is LC3_L44, type is buried. nx866_lc = LCELL( _EQ041); _EQ041 = counter_8 & counter_9 & !L1pass # counter_7 & counter_9 & !L1pass; -- Node name is 'ix800_cas' = 'nx867_cas' from file "top_pre.edf" line 500 -- Equation name is 'ix800_cas', location is LC1_L45, type is buried. nx867_cas = LCELL( _EQ026C); _EQ026C = _EQ026; _EQ026 = L0pass # !counter_7 & !counter_8 & !counter_9; -- Node name is 'ix805_cas' = 'nx869_cas' from file "top_pre.edf" line 504 -- Equation name is 'ix805_cas', location is LC1_L48, type is buried. nx869_cas = LCELL( _EQ042C); _EQ042C = _EQ042; _EQ042 = !counter_7 & !counter_8 & !counter_9; -- Node name is 'ix806_lc' = 'nx870_lc' from file "top_pre.edf" line 505 -- Equation name is 'ix806_lc', location is LC2_L48, type is buried. nx870_lc = LCELL( _EQ043C); _EQ043C = _EQ043 & CASCADE( _EQ042C); _EQ043 = !counter_6 # !counter_5; -- Node name is 'ix808_cas' = 'nx872_cas' from file "top_pre.edf" line 506 -- Equation name is 'ix808_cas', location is LC1_L46, type is buried. nx872_cas = LCELL( _EQ023C); _EQ023C = _EQ023; _EQ023 = counter_8 & counter_9; -- Node name is 'ix811_lc' = 'nx873_lc' from file "top_pre.edf" line 510 -- Equation name is 'ix811_lc', location is LC7_L46, type is buried. nx873_lc = LCELL( _EQ044); _EQ044 = counter_4 & counter_6; -- Node name is 'ix812_cas' = 'nx874_cas' from file "top_pre.edf" line 511 -- Equation name is 'ix812_cas', location is LC7_L48, type is buried. nx874_cas = LCELL( _EQ045C); _EQ045C = _EQ045; _EQ045 = L0en & !L0pass; -- Node name is 'ix813_lc' = 'nx875_lc' from file "top_pre.edf" line 512 -- Equation name is 'ix813_lc', location is LC4_L34, type is buried. nx875_lc = LCELL( _EQ046); _EQ046 = L1en & !nx862_lc; -- Node name is 'ix814_lc' = 'nx876_lc' from file "top_pre.edf" line 513 -- Equation name is 'ix814_lc', location is LC8_L48, type is buried. nx876_lc = LCELL( _EQ047C); _EQ047C = _EQ047 & CASCADE( _EQ045C); _EQ047 = !nx862_lc & !nx870_lc # nx736_lc & !nx862_lc & nx873_lc; -- Node name is 'ix815_lc' = 'nx877_lc' from file "top_pre.edf" line 514 -- Equation name is 'ix815_lc', location is LC3_L46, type is buried. nx877_lc = LCELL( _EQ048C); _EQ048C = _EQ048 & CASCADE( _EQ022C); _EQ048 = L2en & !nx862_lc; -- Node name is 'ix819_cas' = 'nx881_cas' from file "top_pre.edf" line 515 -- Equation name is 'ix819_cas', location is LC4_L48, type is buried. nx881_cas = LCELL( _EQ049C); _EQ049C = _EQ049; _EQ049 = !nx730_lc & nx745_lc & pre_en; -- Node name is 'ix820_lc' = 'nx882_lc' from file "top_pre.edf" line 516 -- Equation name is 'ix820_lc', location is LC6_L48, type is buried. nx882_lc = LCELL( _EQ050); _EQ050 = !modgen_gt_27_nx140_lc & NOT_nx166_lc & nx876_lc # !modgen_gt_27_nx140_lc & !NOT_nx166_lc & nx875_lc; -- Node name is 'ix821_lc' = 'nx883_lc' from file "top_pre.edf" line 517 -- Equation name is 'ix821_lc', location is LC5_L48, type is buried. nx883_lc = LCELL( _EQ051C); _EQ051C = _EQ051 & CASCADE( _EQ049C); _EQ051 = !modgen_gt_27_nx140_lc & NOT_nx155_lc & NOT_nx166_lc # nx862_lc; -- Node name is 'counter_add_29_ix31_lc' = 'nx910_lc' from file "top_pre.edf" line 471 -- Equation name is 'counter_add_29_ix31_lc', location is LC2_L42, type is buried. nx910_lc = LCELL( _EQ052); _EQ052 = counter_1 & c0 & _LC1_L42_CARRY # counter_1 & !c0 & !_LC1_L42_CARRY # !counter_1 & !c0 & _LC1_L42_CARRY # !counter_1 & c0 & !_LC1_L42_CARRY; -- Node name is 'counter_add_29_ix35_lc' = 'nx912_lc' from file "top_pre.edf" line 472 -- Equation name is 'counter_add_29_ix35_lc', location is LC3_L42, type is buried. nx912_lc = LCELL( _EQ053); _EQ053 = !counter_2 & _LC2_L42_CARRY # counter_2 & !_LC2_L42_CARRY; -- Node name is 'counter_add_29_ix39_lc' = 'nx914_lc' from file "top_pre.edf" line 473 -- Equation name is 'counter_add_29_ix39_lc', location is LC4_L42, type is buried. nx914_lc = LCELL( _EQ054); _EQ054 = !counter_3 & _LC3_L42_CARRY # counter_3 & !_LC3_L42_CARRY; -- Node name is 'counter_add_29_ix43_lc' = 'nx916_lc' from file "top_pre.edf" line 474 -- Equation name is 'counter_add_29_ix43_lc', location is LC5_L42, type is buried. nx916_lc = LCELL( _EQ055); _EQ055 = !counter_4 & _LC4_L42_CARRY # counter_4 & !_LC4_L42_CARRY; -- Node name is 'counter_add_29_ix47_lc' = 'nx918_lc' from file "top_pre.edf" line 475 -- Equation name is 'counter_add_29_ix47_lc', location is LC6_L42, type is buried. nx918_lc = LCELL( _EQ056); _EQ056 = !counter_5 & _LC5_L42_CARRY # counter_5 & !_LC5_L42_CARRY; -- Node name is 'counter_add_29_ix51_lc' = 'nx920_lc' from file "top_pre.edf" line 476 -- Equation name is 'counter_add_29_ix51_lc', location is LC7_L42, type is buried. nx920_lc = LCELL( _EQ057); _EQ057 = !counter_6 & _LC6_L42_CARRY # counter_6 & !_LC6_L42_CARRY; -- Node name is 'counter_add_29_ix55_lc' = 'nx922_lc' from file "top_pre.edf" line 477 -- Equation name is 'counter_add_29_ix55_lc', location is LC8_L42, type is buried. nx922_lc = LCELL( _EQ058); _EQ058 = !counter_7 & _LC7_L42_CARRY # counter_7 & !_LC7_L42_CARRY; -- Node name is 'counter_add_29_ix59_lc' = 'nx924_lc' from file "top_pre.edf" line 478 -- Equation name is 'counter_add_29_ix59_lc', location is LC1_L44, type is buried. nx924_lc = LCELL( _EQ059); _EQ059 = !counter_8 & _LC8_L42_CARRY # counter_8 & !_LC8_L42_CARRY; -- Node name is 'reg_pre_en' = 'pre_en' from file "top_pre.edf" line 243 -- Equation name is 'reg_pre_en', location is LC1_L28, type is buried. pre_en = DFFE( mode_0, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'fin_reg_q' = 'pre_in_fil' from file "top_pre.edf" line 252 -- Equation name is 'fin_reg_q', location is LC5_L37, type is buried. pre_in_fil = DFFE( _EQ060, GLOBAL( CLK), VCC, VCC, VCC); _EQ060 = fin_SAMPLES_0 & pre_in_fil # fin_SAMPLES_1 & pre_in_fil # fin_SAMPLES_0 & fin_SAMPLES_1; -- Node name is 'reg_pre_in_fil_old' = 'pre_in_fil_old' from file "top_pre.edf" line 238 -- Equation name is 'reg_pre_in_fil_old', location is LC4_L37, type is buried. pre_in_fil_old = DFFE( pre_in_fil, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'pre_out' from file "top_pre.edf" line 104 -- Equation name is 'pre_out', type is output pre_out = reg_pre_out_i; -- Node name is 'pre_out_lvds' from file "top_pre.edf" line 103 -- Equation name is 'pre_out_lvds', type is output pre_out_lvds = _LC1_L52; -- Node name is 'reg_pre_start' = 'pre_start' from file "top_pre.edf" line 237 -- Equation name is 'reg_pre_start', location is LC3_L48, type is buried. pre_start = DFFE( _EQ061, GLOBAL( CLK), VCC, VCC, VCC); _EQ061 = nx883_lc # nx882_lc # nx877_lc; -- Node name is 'reg_pre_start1' = 'pre_start1' from file "top_pre.edf" line 236 -- Equation name is 'reg_pre_start1', location is LC2_L52, type is buried. pre_start1 = DFFE( pre_start, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'reg_inp_sel' from file "top_pre.edf" line 220 -- Equation name is 'reg_inp_sel', location is LC4_I37, type is buried. reg_inp_sel = DFFE(!reg_inp_sel, inp_sw_f, VCC, VCC, VCC); -- Node name is 'reg_pre_out_i' from file "top_pre.edf" line 235 -- Equation name is 'reg_pre_out_i', location is LC8_L52, type is buried. reg_pre_out_i = DFFE( _EQ062, GLOBAL( CLK), VCC, VCC, VCC); _EQ062 = pre_start1 # pre_start; -- Node name is 'reg_pre_out_i~1' from file "top_pre.edf" line 235 -- Equation name is 'reg_pre_out_i~1', location is LC1_L52, type is buried. -- synthesized logic cell _LC1_L52 = DFFE( _EQ063, GLOBAL( CLK), VCC, VCC, VCC); _EQ063 = pre_start1 # pre_start; -- Node name is 'reg_tst_out' from file "top_pre.edf" line 239 -- Equation name is 'reg_tst_out', location is LC2_I35, type is buried. reg_tst_out = DFFE( _LC3_I34, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is 'ix786_lc' = 'R7S_1_lc' from file "top_pre.edf" line 486 -- Equation name is 'ix786_lc', location is LC6_L38, type is buried. R7S_1_lc = LCELL( _EQ064); _EQ064 = mode_0 & !mode_1 & !mode_2 & !mode_3 # !mode_0 & !mode_1 & mode_2 & !mode_3 # mode_0 & !mode_1 & mode_2 & mode_3 # mode_0 & mode_1 & !mode_2 & mode_3; -- Node name is 'R7S1' from file "top_pre.edf" line 105 -- Equation name is 'R7S1', type is output R7S1 = R7S_1_lc; -- Node name is 'ix787_lc' = 'R7S_2_lc' from file "top_pre.edf" line 487 -- Equation name is 'ix787_lc', location is LC4_L26, type is buried. R7S_2_lc = LCELL( _EQ065); _EQ065 = mode_0 & !mode_1 & mode_2 & !mode_3 # !mode_0 & mode_2 & mode_3 # mode_0 & mode_1 & mode_3 # !mode_0 & mode_1 & mode_2; -- Node name is 'R7S2' from file "top_pre.edf" line 105 -- Equation name is 'R7S2', type is output R7S2 = R7S_2_lc; -- Node name is 'ix788_lc' = 'R7S_3_lc' from file "top_pre.edf" line 488 -- Equation name is 'ix788_lc', location is LC6_L28, type is buried. R7S_3_lc = LCELL( _EQ066); _EQ066 = !mode_0 & mode_1 & !mode_2 & !mode_3 # mode_1 & mode_2 & mode_3 # !mode_0 & mode_2 & mode_3; -- Node name is 'R7S3' from file "top_pre.edf" line 105 -- Equation name is 'R7S3', type is output R7S3 = R7S_3_lc; -- Node name is 'ix789_lc' = 'R7S_4_lc' from file "top_pre.edf" line 489 -- Equation name is 'ix789_lc', location is LC7_L28, type is buried. R7S_4_lc = LCELL( _EQ067); _EQ067 = mode_0 & !mode_1 & !mode_2 # !mode_0 & !mode_1 & mode_2 & !mode_3 # mode_0 & mode_1 & mode_2 # !mode_0 & mode_1 & !mode_2 & mode_3; -- Node name is 'R7S4' from file "top_pre.edf" line 105 -- Equation name is 'R7S4', type is output R7S4 = R7S_4_lc; -- Node name is 'ix790_lc' = 'R7S_5_lc' from file "top_pre.edf" line 490 -- Equation name is 'ix790_lc', location is LC4_L29, type is buried. R7S_5_lc = LCELL( _EQ068); _EQ068 = mode_0 & !mode_1 & !mode_2 # !mode_1 & mode_2 & !mode_3 # mode_0 & !mode_3; -- Node name is 'R7S5' from file "top_pre.edf" line 105 -- Equation name is 'R7S5', type is output R7S5 = R7S_5_lc; -- Node name is 'ix791_lc' = 'R7S_6_lc' from file "top_pre.edf" line 491 -- Equation name is 'ix791_lc', location is LC1_L35, type is buried. R7S_6_lc = LCELL( _EQ069); _EQ069 = mode_0 & !mode_2 & !mode_3 # mode_0 & mode_1 & !mode_3 # mode_1 & !mode_2 & !mode_3 # mode_0 & !mode_1 & mode_2 & mode_3; -- Node name is 'R7S6' from file "top_pre.edf" line 105 -- Equation name is 'R7S6', type is output R7S6 = R7S_6_lc; -- Node name is 'ix792_lc' = 'R7S_7_lc' from file "top_pre.edf" line 492 -- Equation name is 'ix792_lc', location is LC2_L34, type is buried. R7S_7_lc = LCELL( _EQ070); _EQ070 = !mode_0 & !mode_1 & mode_2 & mode_3 # !mode_1 & !mode_2 & !mode_3 # mode_0 & mode_1 & mode_2 & !mode_3; -- Node name is 'R7S7' from file "top_pre.edf" line 105 -- Equation name is 'R7S7', type is output R7S7 = R7S_7_lc; -- Node name is 'SRAM_CEn' from file "top_pre.edf" line 109 -- Equation name is 'SRAM_CEn', type is output SRAM_CEn = VCC; -- Node name is 'SRAM_OEn' from file "top_pre.edf" line 110 -- Equation name is 'SRAM_OEn', type is output SRAM_OEn = VCC; -- Node name is 'tst_out' from file "top_pre.edf" line 101 -- Equation name is 'tst_out', type is output tst_out = reg_tst_out; -- Node name is '|carry_sum:counter_add_29_ix29_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC1_L42_CARRY', type is buried -- |carry_sum:counter_add_29_ix29_carry_sum|:31 is in Up/Down Counter Mode _LC1_L42_CARRY = CARRY( _EQ071); _EQ071 = counter_0 & !c0; -- Node name is '|carry_sum:counter_add_29_ix31_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC2_L42_CARRY', type is buried _LC2_L42_CARRY = CARRY( _EQ072); _EQ072 = counter_1 & c0 # c0 & _LC1_L42_CARRY # counter_1 & _LC1_L42_CARRY; -- Node name is '|carry_sum:counter_add_29_ix35_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC3_L42_CARRY', type is buried _LC3_L42_CARRY = CARRY( _EQ073); _EQ073 = counter_2 & _LC2_L42_CARRY; -- Node name is '|carry_sum:counter_add_29_ix39_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC4_L42_CARRY', type is buried _LC4_L42_CARRY = CARRY( _EQ074); _EQ074 = counter_3 & _LC3_L42_CARRY; -- Node name is '|carry_sum:counter_add_29_ix43_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC5_L42_CARRY', type is buried _LC5_L42_CARRY = CARRY( _EQ075); _EQ075 = counter_4 & _LC4_L42_CARRY; -- Node name is '|carry_sum:counter_add_29_ix47_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC6_L42_CARRY', type is buried _LC6_L42_CARRY = CARRY( _EQ076); _EQ076 = counter_5 & _LC5_L42_CARRY; -- Node name is '|carry_sum:counter_add_29_ix51_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC7_L42_CARRY', type is buried _LC7_L42_CARRY = CARRY( _EQ077); _EQ077 = counter_6 & _LC6_L42_CARRY; -- Node name is '|carry_sum:counter_add_29_ix55_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC8_L42_CARRY', type is buried _LC8_L42_CARRY = CARRY( _EQ078); _EQ078 = counter_7 & _LC7_L42_CARRY; -- Node name is '|carry_sum:counter_add_29_ix59_carry_sum|:31' from file "carry_sum.tdf" line 11, column 9 -- Equation name is '_LC1_L44_CARRY', type is buried _LC1_L44_CARRY = CARRY( _EQ079); _EQ079 = counter_8 & _LC8_L42_CARRY; -- Node name is '|lpm_counter:div_clk_ix7|carrybit1' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC1_I32_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit1 is in Up/Down Counter Mode _LC1_I32_CARRY = CARRY( _LC1_I32); -- Node name is '|lpm_counter:div_clk_ix7|carrybit2' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC2_I32_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit2 is in Up/Down Counter Mode _LC2_I32_CARRY = CARRY( _EQ080); _EQ080 = _LC1_I32_CARRY & _LC2_I32; -- Node name is '|lpm_counter:div_clk_ix7|carrybit3' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC3_I32_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit3 is in Up/Down Counter Mode _LC3_I32_CARRY = CARRY( _EQ081); _EQ081 = _LC2_I32_CARRY & _LC3_I32; -- Node name is '|lpm_counter:div_clk_ix7|carrybit4' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC4_I32_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit4 is in Up/Down Counter Mode _LC4_I32_CARRY = CARRY( _EQ082); _EQ082 = _LC3_I32_CARRY & _LC4_I32; -- Node name is '|lpm_counter:div_clk_ix7|carrybit5' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC5_I32_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit5 is in Up/Down Counter Mode _LC5_I32_CARRY = CARRY( _EQ083); _EQ083 = _LC4_I32_CARRY & _LC5_I32; -- Node name is '|lpm_counter:div_clk_ix7|carrybit6' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC6_I32_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit6 is in Up/Down Counter Mode _LC6_I32_CARRY = CARRY( _EQ084); _EQ084 = _LC5_I32_CARRY & _LC6_I32; -- Node name is '|lpm_counter:div_clk_ix7|carrybit7' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC7_I32_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit7 is in Up/Down Counter Mode _LC7_I32_CARRY = CARRY( _EQ085); _EQ085 = _LC6_I32_CARRY & _LC7_I32; -- Node name is '|lpm_counter:div_clk_ix7|carrybit8' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC8_I32_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit8 is in Up/Down Counter Mode _LC8_I32_CARRY = CARRY( _EQ086); _EQ086 = _LC7_I32_CARRY & _LC8_I32; -- Node name is '|lpm_counter:div_clk_ix7|carrybit9' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC1_I34_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit9 is in Up/Down Counter Mode _LC1_I34_CARRY = CARRY( _EQ087); _EQ087 = _LC1_I34 & _LC8_I32_CARRY; -- Node name is '|lpm_counter:div_clk_ix7|carrybit10' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC2_I34_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit10 is in Up/Down Counter Mode _LC2_I34_CARRY = CARRY( _EQ088); _EQ088 = _LC1_I34_CARRY & _LC2_I34; -- Node name is '|lpm_counter:div_clk_ix7|carrybit11' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC3_I34_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit11 is in Up/Down Counter Mode _LC3_I34_CARRY = CARRY( _EQ089); _EQ089 = _LC2_I34_CARRY & _LC3_I34; -- Node name is '|lpm_counter:div_clk_ix7|carrybit12' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC4_I34_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit12 is in Up/Down Counter Mode _LC4_I34_CARRY = CARRY( _EQ090); _EQ090 = _LC3_I34_CARRY & _LC4_I34; -- Node name is '|lpm_counter:div_clk_ix7|carrybit13' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC5_I34_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit13 is in Up/Down Counter Mode _LC5_I34_CARRY = CARRY( _EQ091); _EQ091 = _LC4_I34_CARRY & _LC5_I34; -- Node name is '|lpm_counter:div_clk_ix7|carrybit14' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC6_I34_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit14 is in Up/Down Counter Mode _LC6_I34_CARRY = CARRY( _EQ092); _EQ092 = _LC5_I34_CARRY & _LC6_I34; -- Node name is '|lpm_counter:div_clk_ix7|carrybit15' from file "lpm_counter.tdf" line 246, column 14 -- Equation name is '_LC7_I34_CARRY', type is buried -- |lpm_counter:div_clk_ix7|carrybit15 is in Up/Down Counter Mode _LC7_I34_CARRY = CARRY( _EQ093); _EQ093 = _LC6_I34_CARRY & _LC7_I34; -- Node name is '|lpm_counter:div_clk_ix7|dffs0' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC1_I32', type is buried -- |lpm_counter:div_clk_ix7|dffs0 is in Up/Down Counter Mode _LC1_I32 = DFFE(!_LC1_I32, GLOBAL( CLK), VCC, VCC, VCC); -- Node name is '|lpm_counter:div_clk_ix7|dffs1' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC2_I32', type is buried -- |lpm_counter:div_clk_ix7|dffs1 is in Up/Down Counter Mode _LC2_I32 = DFFE( _EQ094, GLOBAL( CLK), VCC, VCC, VCC); _EQ094 = !_LC1_I32_CARRY & _LC2_I32 # _LC1_I32_CARRY & !_LC2_I32; -- Node name is '|lpm_counter:div_clk_ix7|dffs2' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC3_I32', type is buried -- |lpm_counter:div_clk_ix7|dffs2 is in Up/Down Counter Mode _LC3_I32 = DFFE( _EQ095, GLOBAL( CLK), VCC, VCC, VCC); _EQ095 = !_LC2_I32_CARRY & _LC3_I32 # _LC2_I32_CARRY & !_LC3_I32; -- Node name is '|lpm_counter:div_clk_ix7|dffs3' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC4_I32', type is buried -- |lpm_counter:div_clk_ix7|dffs3 is in Up/Down Counter Mode _LC4_I32 = DFFE( _EQ096, GLOBAL( CLK), VCC, VCC, VCC); _EQ096 = !_LC3_I32_CARRY & _LC4_I32 # _LC3_I32_CARRY & !_LC4_I32; -- Node name is '|lpm_counter:div_clk_ix7|dffs4' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC5_I32', type is buried -- |lpm_counter:div_clk_ix7|dffs4 is in Up/Down Counter Mode _LC5_I32 = DFFE( _EQ097, GLOBAL( CLK), VCC, VCC, VCC); _EQ097 = !_LC4_I32_CARRY & _LC5_I32 # _LC4_I32_CARRY & !_LC5_I32; -- Node name is '|lpm_counter:div_clk_ix7|dffs5' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC6_I32', type is buried -- |lpm_counter:div_clk_ix7|dffs5 is in Up/Down Counter Mode _LC6_I32 = DFFE( _EQ098, GLOBAL( CLK), VCC, VCC, VCC); _EQ098 = !_LC5_I32_CARRY & _LC6_I32 # _LC5_I32_CARRY & !_LC6_I32; -- Node name is '|lpm_counter:div_clk_ix7|dffs6' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC7_I32', type is buried -- |lpm_counter:div_clk_ix7|dffs6 is in Up/Down Counter Mode _LC7_I32 = DFFE( _EQ099, GLOBAL( CLK), VCC, VCC, VCC); _EQ099 = !_LC6_I32_CARRY & _LC7_I32 # _LC6_I32_CARRY & !_LC7_I32; -- Node name is '|lpm_counter:div_clk_ix7|dffs7' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC8_I32', type is buried -- |lpm_counter:div_clk_ix7|dffs7 is in Up/Down Counter Mode _LC8_I32 = DFFE( _EQ100, GLOBAL( CLK), VCC, VCC, VCC); _EQ100 = !_LC7_I32_CARRY & _LC8_I32 # _LC7_I32_CARRY & !_LC8_I32; -- Node name is '|lpm_counter:div_clk_ix7|dffs8' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC1_I34', type is buried -- |lpm_counter:div_clk_ix7|dffs8 is in Up/Down Counter Mode _LC1_I34 = DFFE( _EQ101, GLOBAL( CLK), VCC, VCC, VCC); _EQ101 = _LC1_I34 & !_LC8_I32_CARRY # !_LC1_I34 & _LC8_I32_CARRY; -- Node name is '|lpm_counter:div_clk_ix7|dffs9' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC2_I34', type is buried -- |lpm_counter:div_clk_ix7|dffs9 is in Up/Down Counter Mode _LC2_I34 = DFFE( _EQ102, GLOBAL( CLK), VCC, VCC, VCC); _EQ102 = !_LC1_I34_CARRY & _LC2_I34 # _LC1_I34_CARRY & !_LC2_I34; -- Node name is '|lpm_counter:div_clk_ix7|dffs10' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC3_I34', type is buried -- |lpm_counter:div_clk_ix7|dffs10 is in Up/Down Counter Mode _LC3_I34 = DFFE( _EQ103, GLOBAL( CLK), VCC, VCC, VCC); _EQ103 = !_LC2_I34_CARRY & _LC3_I34 # _LC2_I34_CARRY & !_LC3_I34; -- Node name is '|lpm_counter:div_clk_ix7|dffs11' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC4_I34', type is buried -- |lpm_counter:div_clk_ix7|dffs11 is in Up/Down Counter Mode _LC4_I34 = DFFE( _EQ104, GLOBAL( CLK), VCC, VCC, VCC); _EQ104 = !_LC3_I34_CARRY & _LC4_I34 # _LC3_I34_CARRY & !_LC4_I34; -- Node name is '|lpm_counter:div_clk_ix7|dffs12' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC5_I34', type is buried -- |lpm_counter:div_clk_ix7|dffs12 is in Up/Down Counter Mode _LC5_I34 = DFFE( _EQ105, GLOBAL( CLK), VCC, VCC, VCC); _EQ105 = !_LC4_I34_CARRY & _LC5_I34 # _LC4_I34_CARRY & !_LC5_I34; -- Node name is '|lpm_counter:div_clk_ix7|dffs13' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC6_I34', type is buried -- |lpm_counter:div_clk_ix7|dffs13 is in Up/Down Counter Mode _LC6_I34 = DFFE( _EQ106, GLOBAL( CLK), VCC, VCC, VCC); _EQ106 = !_LC5_I34_CARRY & _LC6_I34 # _LC5_I34_CARRY & !_LC6_I34; -- Node name is '|lpm_counter:div_clk_ix7|dffs14' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC7_I34', type is buried -- |lpm_counter:div_clk_ix7|dffs14 is in Up/Down Counter Mode _LC7_I34 = DFFE( _EQ107, GLOBAL( CLK), VCC, VCC, VCC); _EQ107 = !_LC6_I34_CARRY & _LC7_I34 # _LC6_I34_CARRY & !_LC7_I34; -- Node name is '|lpm_counter:div_clk_ix7|dffs15' from file "lpm_counter.tdf" line 234, column 10 -- Equation name is '_LC8_I34', type is buried _LC8_I34 = DFFE( _EQ108, GLOBAL( CLK), VCC, VCC, VCC); _EQ108 = !_LC7_I34_CARRY & _LC8_I34 # _LC7_I34_CARRY & !_LC8_I34; Project Information e:\tiserv\trigger\maxplus\top_pre.rpt ** TIMING ASSIGNMENTS ** INFORMATION: One or more paths have been found between register controlled by different clocks--can't calculate fmax for those paths User Actual Type Location Assignment Value Status Critical Path fmax CLK 90.00 MHz 95.23 MHz CLK to register |lpm_counter:div_clk_ix7|dffs15.Q to register L1en.Q Project Information e:\tiserv\trigger\maxplus\top_pre.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Multi-Level Default Synthesis Style = FAST Logic option settings in 'FAST' style for 'ACEX1K' family CARRY_CHAIN = auto CARRY_CHAIN_LENGTH = 32 CASCADE_CHAIN = auto CASCADE_CHAIN_LENGTH = 2 DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on REDUCE_LOGIC = on REFACTORIZATION = off REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SUBFACTOR_EXTRACTION = off IGNORE_SOFT_BUFFERS = on USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = off Automatic Register Packing = off Automatic Open-Drain Pins = off Automatic Implement in EAB = off Optimize = 5 Default Timing Specifications: Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = off Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Use Quartus Fitter = on Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = on Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:00 Database Builder 00:00:00 Logic Synthesizer 00:00:00 Partitioner 00:00:00 Fitter 00:00:06 Timing SNF Extractor 00:00:00 EDIF Netlist Writer 00:00:01 Assembler 00:00:01 -------------------------- -------- Total Time 00:00:08 Memory Allocated ----------------- Peak memory allocated during compilation = 49,728K