LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

entity top_pre is
    port (
        clk             : in  std_logic; -- 80 MHz

        -- user IO
        mode_sw         : in  std_logic;
        inp_sw          : in  std_logic;
        pre_in          : in  std_logic; -- ADC1_D0, ADC connector pin 19
        tst_out         : out std_logic; -- ADC1_D2, ADC connector pin 17
        LVDS_in         : in  std_logic_vector(3 downto 0); -- LVDS connector, bit 1, pins 5-6 (p-n)
        pre_out_lvds    : out std_logic; -- LVDS connector, pins 13-14 (n-p)
        pre_out         : out std_logic; -- ADC2_D0, ADC connector pin 11
        R7S             : out std_logic_vector(1     to 7);

        LED_RED         : out std_logic; -- 0 is on, TTL input (ADC connector) activ
        LVDS_EN         : out std_logic;
        ADC_OEn         : out std_logic;
        SRAM_CEn        : out std_logic;
        SRAM_OEn        : out std_logic
        );
end top_pre;


architecture a of top_pre is

component dbl7seg IS
        PORT(
                CL, CR  : IN    STD_LOGIC_VECTOR(3 downto 0); -- code for left/right
                mx      : IN    STD_LOGIC; -- 100Hz
                dis     : IN    STD_LOGIC; -- disable outputs (switch off)
                mx_out  : OUT   STD_LOGIC;
                Q       : OUT   STD_LOGIC_VECTOR(1 to 7) -- output to 7segm ind.
                );
END component;

component filt2s IS
        PORT(
                clk, d          : IN    STD_LOGIC;
                q               : OUT   STD_LOGIC);
END component;

component filt3s IS
        PORT(
                clk, d          : IN    STD_LOGIC;
                q               : OUT   STD_LOGIC);
END component;

constant L0time         : Integer :=  80;
constant L1time         : Integer := 684;
constant L2time         : Integer := 800;

signal  counter         : Integer range 0 to 1023;
signal  pre_start       : std_logic;
signal  pre_start1      : std_logic;
signal  pre_in_s        : std_logic;
signal  pre_in_fil      : std_logic;
signal  pre_in_fil_old  : std_logic;
signal  c0              : std_logic;
signal  L0pass          : std_logic;
signal  L1pass          : std_logic;
signal  L2pass          : std_logic;
signal  L_pass          : std_logic;
signal  pre_en          : std_logic;
signal  L0en            : std_logic;
signal  L1en            : std_logic;
signal  L2en            : std_logic;
signal  mode            : std_logic_vector(3 downto 0);
signal  mode_sw_f       : std_logic;

signal  div_clk         : std_logic_vector(15 downto 0);
signal  clk_slow        : std_logic;

signal  pre_out_i       : std_logic;
signal  inp_sel         : std_logic;
signal  inp_sw_f        : std_logic;
signal  pre_in_lvds     : std_logic; -- LVDS connector, pins 5-6 (p-n)

begin

        pre_in_lvds <= LVDS_in(1);
        LVDS_EN  <= '1';
        ADC_OEn  <= '1';
        SRAM_CEn <= '1';
        SRAM_OEn <= '1';
        process(mode_sw_f)
        begin
            if mode_sw_f'event and mode_sw_f='1' then
                case mode is
                when "0000"     => mode <= "0001"; -- only pretrigger
                when "0001"     => mode <= "0011"; -- pretrigger and L0A
                when "0011"     => mode <= "0111"; -- ptretrigger, L0A and L1A
                when "0111"     => mode <= "1011"; -- ptretrigger, L0A and L2A
                when "1011"     => mode <= "1111"; -- ptretrigger, L0A, L1A and L2A
                when others     => mode <= "0000";
                end case;
            end if;
        end process;

        clk_slow <= div_clk(div_clk'high);

sg:    dbl7seg
        PORT map(
                CL     => mode,
                CR     => mode,
                mx     => '0',
                dis    => '0',
                mx_out => open,
                Q      => R7S);

fmd:    filt3s
        PORT map(
                clk  => clk_slow,
                d    => mode_sw,
                q    => mode_sw_f);

        process(inp_sw_f)
        begin
            if inp_sw_f'event and inp_sw_f='1' then
                inp_sel <= not inp_sel;
            end if;
        end process;
        LED_RED <= inp_sel;

fmi:    filt3s
        PORT map(
                clk  => clk_slow,
                d    => inp_sw,
                q    => inp_sw_f);

        with inp_sel select
        pre_in_s <= pre_in when '0',
                    pre_in_lvds when others;


fin:    filt2s
        PORT map(
                clk  => clk,
                d    => pre_in_s,
                q    => pre_in_fil);

        L_pass <= L0pass and L1pass and L2pass;
        process(clk)
        begin
            if clk'event and clk= '1'  then
                pre_en <= mode(0);
                L0en   <= mode(1);
                L1en   <= mode(2);
                L2en   <= mode(3);
                div_clk <= div_clk + 1;
                tst_out  <= div_clk(10);
                pre_in_fil_old <= pre_in_fil;
                pre_start <= '0';
                pre_start1 <= pre_start;
                pre_out_i <= pre_start or pre_start1;
                if pre_in_fil='1' and pre_in_fil_old='0' and L_pass='1' then
                    c0 <= '0';
                    counter <= 0;
                    L0pass  <= '0';
                    L1pass  <= '0';
                    L2pass  <= '0';
                    pre_start <= pre_en;
                end if;
                if L_pass='0' then
                    if L0pass='0' and counter > L0time then
                        L0pass <='1';
                        pre_start <= L0en;
                    end if;
                    if L1pass='0' and counter > L1time then
                        L1pass <='1';
                        pre_start <= L1en;
                    end if;
                    if counter > L2time then
                        L2pass <='1';
                        pre_start <= L2en;
                    end if;
                    if c0='0' then counter <= counter + 1;
                              else counter <= counter + 2;
                    end if;
                    c0 <= not c0;
                end if;
            end if;
        end process;
        pre_out      <= pre_out_i;
        pre_out_lvds <= pre_out_i;

end;